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select the proper choice (s)

1- updating data occurs on -- ?

(A) Virtual memory (B) Main memory (C) Auxiliary memory (D) Cache memory

2- DRAM is used as main memory in a computer because it

(A) Consumes less power (B) has higher speed (C) has lower cell density (D) needs refreshing circuit

3- The main memory in a Personal Computer (PC) is made of

(A) cache memory. (B) static RAM (C) Dynamic Ram (D) both (C) and (B).

4- Memory unit accessed by content is called

(A) Read only memory (B) Programmable Memory (C) Virtual Memory (D) Associative Memory

5- the interface that provides transfer of data directly to and from a memory is :
(A) DDA. (B) Serial interface. (C) BR. (D) DMA.

6- The average time required to reach a storage in memory and obtain its contents is called
(A) Latency time. (B) Access time. (C) Turnaround time. (D) Response time.

7- The cache memory of 1K words uses direct mapping with a block size of 4 words. How many
blocks can the cache accommodate.
(A) 256 words. (B) 512 words. (C) 1024 words. (D) 128 words

8- Why read and write control lines in a DMA controller are bidirectional?
A) To communicate with the CPU and I/O device.
B) The word count register specifies the number of words that must be transferred.
C) The registers in the DMA are selected by the CPU through the address bus by enabling inputs.
D) The CPU can communicate with the DMA registers through the data bus to (read from or write to the DMA
registers.

9-A Computer uses a memory unit with 256 K words. word size is 32 bits. An instruction is stored in one
word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part
to specify one of 128 registers, and address part to memory. How many operations can be performed?
a- 7 b- 6 c=32 d- 128

10- what are aspects of Disks

a)Larger capacity, Lower price per bit, Permanent, Disks are clustered in cylinders, tracks and sectors.
b)Access time = rotational delay + transfer time c)Disk latency time=3 s/rotation
d) RAID use 40 bits for a word of 32 bits with Hamming code, and mirror parity.

11- errors may occur on disk due to

a)Programming errors b)Seek error :arm moves to a wrong sector
 c) non existing sector, dust particles, bad sectors d) all the previous

12-_______ keeps track of the instructions stored in program.

(A) AR (Address Register) (B) XR (Index Register) (C) PC (Program Counter) (D) AC (Accumulator)

13-Cache memory acts between

(A) CPU and RAM (B) RAM and ROM (C) ROM and Hard Disk (D) None of these

14- -bus is characterized with?

a) Bandwidth b)access protocols c)clock rates d) all the previous

15-bus may be?

a) Synchronized or asynchronized , Dedicated or switched, Simplex or duplex
b) Wired or wireless c)Data bus, address bus, control bus d) All the above

16- faster bus includes:

a) more wires b)more bandwidth buffers c) less clock rate, d)All the above

17- a bus buffer with clock rate 100MHz , can handle data at rates:
a) 100Mb/s b) 100Mword /s c)0.1 nsec d) depending on number of buffer bits

18-bus operations may:

a)transfer and store data b) change mode (serial to parallel) c) change transfer rate d) all previous

19-bus with BW= 100Mb/s can handle 10MB file in:

a)0.8sec b)10sec c) 0.1 sec d) any time

20- the sequence of send process is done as:

a)request to send, ready in buffer, send , acknowledge b)request, send
c)identify, send d) request, transfer

21-bus system is an interface between:

a)peripherals and processor b)i/O and printer c)memory and cache d)non

22- transfer via bus :

a) Need handshaking (request to send, ready in buffer, send, ack)
b) Select data and transfer only c) Check if channel busy or not d)All above

23-increasing bus bandwidth is done by:

a)increasing clock rate b)increasing buffer size, c) handle multiple words per cycle
d)all the above

24- Write-through cache is:

a) any changes to cache are written through to memory, used for Uniform Memory Access [UMA]
b)Make a copy of information to increase availability.
c) Copy information for SPI (Serial Peripheral Interface) d)all the above
25-RAM is characterized with?
a) number of addressed words, word size, number of address registers
b) number of caches, number of memory controllers
c)number of buffers , number of independent modules d) all the above

26-multiple processors categories are:

a)parallel b) MIMD c)pipelined D)all the above

27-MIMD categories are:

a)master/ slave b)cluster/ distributed c) switched d) all above

28- independent processors aspects?

a)avoid deadlocks and speed up execution b) share modular data
c)share local and remote procedure calls (RPC, LPC) d) all the previous

29-process states are:

a)remote, local b)new, ready, wait, run, terminate,
c) ready, run , allocate, d) all above

30- accessibility is
a) 1- rate of fail to access b) 1- fail rate c) rate of updating system d) all previous

31- Scalability is
a) 1- rate of fail to access b) 1- fail rate c) rate of upgrading system d) all previous

32- To reduce the entire memory access time we use :

a) SDRAM’s b) Heaps c) Cache’s d) Higher capacity RAM’s

33 - The VLIW architecture follows _____ , to achieve parallelism.

a) SISD b) MIMD c) MISD d) SIMD

34- Which of the following form CISC?

a) Complex Instruction Sequential Compilation b) Complete Instruction Sequential Compilation
c) Computer Integrated Sequential Compiler d) Complex Instruction Set Computer

35-During a write operation if the required block is not present in the cache then ______ occurs.
a) Write miss b) Write latency c) Write hit d) Write delay

36- central processing unit and memory are located on the

a) expansion board b) motherboard c) storage device d) None of these

37-Which unit is used to measure the CPU’s processing power?

a) GIPS b) GUI c) MIPS d) Nanoseconds

38-The unit of clock rate of CPU is measured in?

a) Milliseconds b) Micro-hertz c) Nanoseconds d) GHz

39- Which of the following special-purpose register is used by CPU?

 a) Program counter (PC) b) Stack pointer (SP) c) Memory address register d) All of the above

40 Which of the following is a bidirectional bus?

a) Address bus b) Data bus c) Control bus d) Both b and c

41- An instruction cycle consists of?

a) fetching, and decoding b) decoding, and executing
c) fetching, decoding, executing, and storing d) fetching, and storing

42- n bits in operation code imply that there are ----- possible operations
a)2n b)2n c)n/2 d)n2

43- MIMD stands for?

a)multiple instruction multiple data b) multiple instructions memory data
c)memory information multiple data d)multiple information memory data

44- if memory access time=20ns, cache access time=10ns, main memory access time=110ns, then ,
the ratio of using cache is?
a)93% b)90% c)88% d)80%

45- processor executes set of jobs in 2.4sec, after adding floating point co-processor, it executes the
same set of jobs in 1,8 sec., using relation : , the speed up ratio is:
a)1.33 b)0.75 c)1.8 d) 2.4

46- performance is estimated as:

a) 1/ execution time b) execution time c)Waiting time d) service time

47- CPI is abbreviation for:

a)average cycles per instruction b)centralized instruction
c-cycle performance / instruction d-non of the above

48- memory speeding up is done by:

a)increasing memory size b)increasing number of caches and cache size
c) reduce number of memory modules d)all the above

49- to improve processor performance?

a) Increase effective speed of Parallelism, clock rate b) Increase size and speed of caches
c)reduce Cache access times , MFLOPS d) all the above

50- - which of the following is correct?

a) Read miss : Processor P reads data at address A; make P a read and arrange to send data back
b) Write miss: Processor P writes data at address A; make P to arrange to send data back
c) Fetch : Fetch the block at address A and send it to its home directory, invalidate the block in the cache
d) Data write-back: Write-back a data value for address A