A Game-Changer For IP Designers: Design-Stage Verification

DIGITAL INDUSTRIES SOFTWARE
A game-changer for IP
designers: design-stage
verification
Executive summary
Whether you use commercial IP or design IP in-house, ensuring your IP is signoff-
compliant and ready for integration into larger designs is critical to success. Precise
physical verification ensures that IP cells are robust enough for use in many different
design styles and adaptable to all the dynamics of the larger design’s usage. However,
designers also need to reduce the time and resources required to design, implement,
and verify IP.
Calibre Shift Left solutions combine proven Calibre technologies for consistent and
thorough verification of IP designs while maximizing productivity and efficiency.
Integration with all major design and place and route (P&R) environments lets
designers apply design-stage verification in familiar environments while ensuring
Calibre signoff quality. With the trusted Calibre nmPlatform, design companies can
create a best-in-class shift left strategy that improves IP designer productivity and
design quality with faster runtimes and increased resource efficiency, all with Calibre
confidence.
Author: Terry Meeks
siemens.com/software
Technical Paper – A game-changer for IP designers: design-stage verification
Contents
IP design
Shift left verification
Shift left verification in the IP design flow
Shift left verification for IP designers
Shift left verification for IP design types
Conclusion
SIEMENS DIGITAL INDUSTRIES SOFTWARE 2

IP design
Intellectual property (IP) is a standalone reusable component that can be

incorporated into many larger integrated circuit (IC) designs. IP designers create
standard cell libraries and blocks that are placed into larger macro blocks and full chip
designs. An IP may contain heavily analog-focused applications, digital logic blocks,
various memory blocks, or standard libraries consisting of hundreds of logical gates
and functions. All design companies use IP in their IC designs to eliminate the need to
create their functionality over and over again with each new IC layout.
IP can be acquired from dedicated IP design companies, or developed in-house. In

either case, developing IP requires specialized knowledge and experience to maximize
IP capabilities in a minimized space. Because IP is intended to be used in multiple
designs, IP cells must be robust enough to be used in many different design styles,
with the flexibility to adapt to all the dynamics of the larger design’s usage. IP must
also be fully verified against signoff requirements to enable it to be integrated into
larger designs with minimal work.
IP design types
Each IP falls into one of three categories: hard, soft, or custom.
Hard IP, such as cores and standard cells, are typically custom designs certified by a
foundry at the time a process technology is defined. Most foundries and IC design
companies request or require IP that has passed Calibre® nmPlatform signoff
verification. Commercial IP is often ranked by confidence scores, so IP providers
seeking a 100% score typically use the foundry-preferred Calibre nmPlatform toolsuite
for (at a minimum) design rule checking (DRC), layout vs. schematic (LVS) verification,
and reliability/electrical rule checking (ERC). Similarly, customers purchasing IP
created by IP design companies typically expect Calibre signoff verification of the IP as
part of the delivery. This verification provides Calibre confidence that when the IP is
instantiated in the final design, there will be no unpleasant surprises when the full-
chip design is verified with the Calibre toolsuite.

Soft IP typically consists of SRAM compiled from a library of pre-defined cells (bit cells,
IO cells, etc.) to create the hard IP. To validate that the hard IP generated by the SRAM
complier is exactly as validated by the foundry during process development, IP
designers use tools like the Calibre Pattern Matching tool to analyze the layout against
requirements. As designers integrate the SRAM, subtle modifications to the SRAM can
occur, either intentionally or unintentionally. These changes often consist of very
slight misalignments (such as a 1nm shift) that can be easily missed, but because
SRAM is built right at the limits of what is manufacturable, can result in catastrophic
failure in either performance or yield. Foundries consider such changes to be errors
that must be fixed.
Custom IP is typically created for a specific design, or to implement functionality that

is patented or provides a competitive advantage. Traditional custom IP cell design
requires manually creating a layout in a custom editor, then running DRC and LVS
verification to identify any construction errors. This process is still largely a manual
and sequential process that often requires multiple iterations.
IP design flow
Figure 1 depicts a traditional IP design flow through signoff physical verification (PV).
Circuit designers create the logical circuit and run it through simulation to validate
that the design will meet its functional and performance requirements. Depending on
design type, IP designs are then physically implemented using various tools, such as
full-custom editors, memory compilers, or place and route (P&R) automation tools. As
the physical design is created, the physical implementation is checked against
foundry design rules and the logical design using DRC, LVS, and reliability verification
tools. The exchange of data between the design creation tool and the PV tools
requires translation to an intermediate format, typically GDSII or OASIS, which
requires designer time and effort to complete.
If the PV tools find discrepancies, designers return to the design tool and implement
corrections. This entire process iterates until the design is clean (no errors returned
from PV tools). Next, parasitic extraction (PEX) is run, and post-layout simulation
begins. Engineering change orders (ECOs) can introduce design changes at any point

in this flow, requiring further design adjustments and verification iterations. Once all
design requirements are met and the design passes verification, the IP can be released
for use.
Figure 1. Traditional IP design verification flow.
While this design and verification flow has worked well for decades, the challenges of
design size and complexity combined with increasing pressure of a faster time-to-
market delivery demand new verification solutions that provide greater efficiency,
enhance productivity, and reduce time to market while ensuring design quality and
performance.

Shift left verification
At Siemens EDA, we collaborate with design companies and foundries every day to
understand what designers need and want to achieve business and design goals, and
to provide an EDA ecosystem that supports every designer where they are with the
tools they need. To bring IP designs to market faster, and achieve the ramp to volume
production sooner, Calibre Design Solutions provides tools and functionalities that
enable IP designers to shift selected physical verification and design optimization
earlier in their design and implementation flows (figure 2).
Figure 2. Calibre Shift Left solutions enable design teams to enhance productivity and
design quality while reducing time to market.

With the trusted and proven Calibre nmPlatform, design companies have the freedom
and flexibility to create a best-in-class shift left solution that improves IP designer
productivity and design quality, provides faster runtimes and increased resource
efficiency, and allows their designers to work within familiar design and
implementation environments, all while achieving Calibre confidence throughout the
IP design implementation flow.
Shift left verification in the IP design

flow
The integrated circuit (IC) design flow is commonly depicted as a serial process where
one stage completes before going to the next. While a linear flow simplifies the
illustrations and narration of the process, the reality is that time to market and
resource restraints require a simultaneous execution of all aspects of the design
stages. IP designs, whether developed in-house or purchased for integration, are only
one part of a flow that must be synchronized between multiple design stages (figure
3).

Figure 3. IP design or integration is performed in parallel with multiple design

processes in SOC design.
When developed in-house, IP cells are often designed concurrently with the macro
blocks and top-level system-on-chip (SOC) designs. For example, top-level power
distribution and clock trees must often be determined—and signed off—before the
cells and blocks are completed, which causes ramifications in the cells below.
Alternatively, changes in lower cells may affect the pin locations, which affects the
routing at the higher levels. Each iteration affects others, requiring more iterations of

the verification tools as each stage evolves. Because verification is constantly

happening at different levels, efficiency and productivity require consistency in the
verification tools and processes, regardless of when they are used.
Commercial IP companies who produce IP for the semiconductor market are rarely
aware of all the downstream requirements for designs that may incorporate their IP.
However, IC companies that buy external IP rely on the quality and performance of
those IP, so failure to meet expectations directly impacts the market success of
commercial IP companies. For commercial IP designers, using a single foundry-trusted
verification toolsuite ensures design rules are checked and errors corrected
consistently and with signoff-level quality at every stage of the IP design flow.
The Calibre® nmPlatform is used by all major foundries to develop new technology
node processes, solidifying its position as the foundry-preferred toolsuite for signoff
verification accuracy. Over 90% of semiconductor design companies use the Calibre
nmPlatform for their signoff physical verification and design optimization. Enabling
early design stage access to the same advanced verification and optimization
functionalities, as well as the underlying rule decks and engines, used by the Calibre
nmPlatform for signoff verification allows IP design teams, whether external or in-
house, to perform early design stage verification with the confidence that design
issues will be accurately identified and corrected with signoff-quality fixes (figure 4).
Fixes made during early design stages remain compliant with block/chip design and
signoff requirements when the IP is placed into larger components. Avoiding late-
stage conflicts and unexpected results during signoff verification is a key factor in
achieving the full benefits of a shift left verification strategy.

Figure 4. Shift left physical verification in IP design flows.
Shift left verification for IP designers
Targeted verification
The Calibre nmDRC Recon and nmLVS Recon tools provide automated ruleset
selection that focuses on running rule checks for rules with local scope that target
critical and systemic errors (figure 5). By running these targeted checks during early
design stages, designers can not only significantly reduce runtimes, but also generate
results that are geometrically close to the source of the issue, reducing debug time as
well. The Calibre nmDRC Recon tool automatically selects design rule checks with the
highest priority in the implementation stage, while the Calibre nmLVS Recon tool lets
designers target and analyze the most significant nets and focus on specific early
design circuit issues, such as short isolation analysis and debugging, selective (well)
connectivity extraction and analysis, and targeted electrical rules checking (ERC).

Because these tools rely on the same Calibre engines and rule decks used for signoff
verification, they enable design teams to dramatically speed up early design analysis
and reduce overall design closure time, while ensuring Calibre confidence in the
results.
On-demand DRC verification

The Calibre RealTime Digital and RealTime Custom tools are integrated with all major
design and P&R tools. The Calibre RealTime tools provide immediate feedback for DRC
violations in the design or implementation tool. This feedback enables designers to
quickly analyze and correct DRC errors using Calibre signoff engines and rule decks,
ensuring any fixes remain DRC-compliant. The ability to analyze and correct DRC
errors with signoff-quality fixes ensures that IP will not generate those DRC errors at
the next design level. In addition, enabling designers to work within their familiar
design or implementation environment enhances productivity and reduces overall
verification time.
Integration and runtime invocation

The Calibre Interactive interface supports the integration of Calibre tools into design
and implementation environments, and enables automated PV flows by providing
user-friendly configurable interfaces for runset invocation, as well as automated pre-
and post-run operations. Standardizing PV flow invocation not only reduces the
learning curve for design engineers, but also reduces maintenance costs, while
ensuring consistency of results and design methodologies.
Debug integration and guidance

The Calibre RVE results viewer provides error debugging within all major design and
implementation environments, enabling design engineers to work in a familiar design
cockpit to debug and correct errors. Automated error categorization and filtering
capabilities help designers perform targeted debugging in a systematic way by
organizing results based on most likely root cause. Fix suggestions in plain text help
designers quickly and accurately correct errors, while the ability to view and highlight
errors lets them validate fixes quickly and efficiently.

Automated waiver management

The Calibre Auto-Waivers® tool can be used in conjunction with the Calibre nmDRC
Recon tool to define and maintain design rule waivers in collaboration with IP library
providers and the foundries, all within a familiar PV environment. The Calibre Auto-
Waivers flow benefits everyone in the IP design flow by standardizing the waiver
process:
• IP providers can generate known waivers and provide these definitions to their
downstream customers and foundries to preserve these constraints
• IC and SoC designers can add to the waivers database and make their
processing more efficient and focused
• Foundries can utilize this data and automatically benefit from these waiver
definitions in their Calibre runs.
Pattern matching
Symmetry in IP design is a core component of IP quality. The Calibre Pattern Matching
tool simplifies complex design requirements through interactive pattern-enabled
checking. Verifying transistor or even complex multi-layer device symmetry is a point-
and-click check accessible directly in the layout design environment. IP designers use
the Calibre RealTime Custom tool to visualize the axis of symmetry and debug
symmetry differences with immediate feedback. Verified fixes remain DRC-clean
throughout signoff verification. Downstream verification of proper IP integration is a
simple executable confirming the existence of the IP within the design, location, and
specific modifications, if any, within or above each instance. Providing this integration
confirmation without the need for rule coding or tool expertise provides designers
with the ability to complete IP integration easier and earlier.
Reliability verification
The Calibre PERC™ reliability platform provides a powerful suite of electrical checks
combined with the ability to apply context-aware checking that enable IP designers to
find and eliminate reliability impacts such as electrostatic discharge (ESD) and latch-
up during early design stages, reducing the time and resources needed to capture
these issues in simulation.

Automated design layout optimization

Design for manufacturing (DFM) optimization consists of design adjustments that are
not required, but that can improve a design’s manufacturability and/or performance
and reliability. While DFM optimization traditionally occurs during signoff verification,
the Calibre DesignEnhancer® tool offers three use models that enable designers to
apply selected automated DFM optimizations during early design stages.
• Automated via insertion adds Calibre nmDRC-clean vias to moderate the

impact of via resistance, improving manufacturing robustness and reducing
the effects of electromigration (EM) and voltage (IR) drop on design reliability
• Automated via and metal insertion in open areas creates parallel run lengths
that help lower resistance on power grid structures, further reducing EM and
IR drop issues
• Automated filler cell and decoupling capacitor (DCAP) cell insertion replaces
time-consuming and limited P&R filler cell insertion with Calibre-correct filler
and DCAP cells to support density targets and multi-height cells
Advanced fill functionality

The Calibre YieldEnhancer tool offers additional specialized layout optimizations:
• Calibre YieldEnhancer SmartFill and engineering change order (ECO) fill

capabilities allow designers to maintain most of their timing analysis when an
ECO occurs. By removing only the planarization fill around the affected areas,
designers can stabilize the parasitics around critical nets. This ability to
minimize refill processing improves the ECO process productivity and
minimizes impacts on the rest of the timing analysis.
• Calibre YieldEnhancer programmable edge modification (PEM) uses layout
analysis to move edges or polygons to optimize manufacturability
Multi-patterning color assignment

Coloring assignment for multi-patterning is an important aspect in IP design because
block/full chip designers must be able to color IP cells correctly in many various
orientations and configurations. If some interaction or orientation does not allow for
coloring flexibility, then additional variations to the cell must be provided, enlarging
the size and complexity of the standard cell library. If coloring issues are not detected

and avoided early, they can cause huge time delays and require redesigns when
implementing the downstream principal levels of the larger design (figure 5). The
Calibre Multi-Patterning tool provides IP designers the ability to determine and color
the layouts for mask assignment in advanced technology processes. If discrepancies
are determined, the Calibre Multi-Patterning flow conflict and warning rings provide
intuitive assistance in resolving coloring conflicts.
Figure 5. IP coloring for multi-patterning assignment must anticipate multiple

orientations and configurations.

Shift left verification for IP design

types
Introducing a shift left strategy into the IP design verification process also provides
specific benefits for each IP design type.
Hard IP
Early design stage IP verification enables hard IP designers to quickly identify modified
IP components in an updated IP, minimizing the number of components requiring
retesting for certification. Automated assistance for fixing or waiving newly identified
errors, such as that provided by the Calibre Pattern Matching and Calibre Auto-
Waivers tools, allows hard IP designers to quickly fix violations, or waive errors in IP
that has been proven in silicon. Because these errors are resolved or waived before
the IP is incorporated into an IC/SoC layout, block and full chip designers do not have
to worry about encountering these IP errors during their verification flow.
Soft IP
Soft IP designers can compile a SRAM IP as a standalone design, then check the
integrity of that SRAM using the Calibre SRAM Checker tool and other automated
Calibre pattern and alignment checking capabilities to find and correct any
misalignment or compilation issues early, before the IP design is complete.
Custom IP
Custom IP designers can use the Calibre RealTime Custom tool with a pre-loaded
qualified Calibre rule deck within their design environment for quick verification while
they design. As they create geometries, a single button click lets them instantly see
any error, view fix hints, and correct errors with immediate feedback. This
instantaneous access to qualified verification by itself greatly improves IP designer
productivity, but such in-line checking can further reduce the time and effort of the
designers for specific verification situations.

Analog or radio frequency (RF) custom design requires validation of symmetry. For
instance, with a differential pair, designers must ensure that not just the devices, but
also the surroundings of those devices, match exactly to eliminate any electrical
differences due to varying parasitic impacts. This comparison is not easily handled in
a foundry-provided rule file because the information is design-specific. In a traditional
custom IP design flow, designers use manual measurements, or manually create
specific rule decks for each case. Using the Calibre RealTime Custom interface in
conjunction with the Calibre Pattern Matching tool, IP designers can simply specify a
line-of-symmetry and region of interest directly in the layout editor to immediately
identify any mismatch between corresponding shapes. The ability to access advanced
fill techniques from the same tool also allows IP designers to add required fill shapes
in a manner that ensures symmetry compliance.
Another custom IP design challenge is the inadvertent creation of short circuits.

Unlike DRC, where only the layout is required, LVS verification typically requires a
corresponding schematic netlist. This netlist may not exist for a cell still in early
development. However, IP designers using the Calibre nmLVS Recon tool with short
isolation (SI) functionality can quickly identify potential shorts without a netlist. The
Calibre nmLVS Recon SI functionality quickly extracts connectivity from the layout and
identifies any contradicting text labels on the same physically connected net. Once
these errors are identified, one or more paths associated with the conflicting texts can
be broken down and easily traced to identify the specific polygon responsible for the
short. Not only is this technique very fast, but it also eliminates many potential errors
related to the connectivity errors, which significantly improves the runtime and debug
cycles of later LVS, ERC, and even DRC verification.
Performance optimization
Optimization of the design flow is not a new aspect of the Calibre nmPlatform. From
the very beginning, Calibre Design Solutions introduced automated optimizations to
the design verification process. At the start of every Calibre run, the rules are
compiled and optimized to reduce processing of layer data, combining operations on
the same input data, minimizing memory usage, and providing optimal performance
and resource usage (figure 6). Current Calibre engines are the result of numerous
reinventions and improvements, all with the goal of creating minimal impact on the
design teams that use them.

Figure 6. Continuous improvement in the Calibre nmPlatform engines not only

reduces runtimes, but also minimizes memory use for optimal resource utilization.
The Siemens standard verification rules format (SVRF) language has grown over the
years, and is highly respected throughout the physical verification (PV) industry. The
Calibre nmPlatform maintains upward compatibility across rule files, providing
consistency in the PV flow.
By taking the same approach to its shift left solutions, the Calibre nmPlatform
continuously implements innovative performance optimizations and automated
operations that reduce the time needed to run early design stage verification. At the
same time, user-friendly GUIs and process automation simplify and speed up the
management and execution of time-consuming and complex operations. Integration
with all major design and place and route (P&R) environments enable IP designers to
apply early design stage verification in familiar environments while ensuring Calibre
signoff-quality results.

Conclusion
Commercial IP design is a highly competitive market, while in-house IP design allows

design companies to achieve a competitive advantage by implementing innovative
functionality in their IC designs. Either way, ensuring that the IP they create is signoff-
compliant and ready for integration into larger designs is a critical success factor.
Reducing the time and resources required to design, implement, and verify IP can
directly affect marketability and profitability.
Time to market dictates that there is no time to fix mistakes more than once. Ensuring
that a design is correct in the least amount of time possible requires design teams to
detect and fix problems as early as possible in the design flow, to avoid having to
correct them during signoff, when error fixing becomes exponentially more difficult
and time-consuming. Using the same PV toolsuite as the majority of IP customers and
their foundries simplifies and standardizes the exchange of information and the
consistency of the processing of IP designs, reducing both critical time to market and
the required resources. The Calibre Shift Left solutions combine with proven Calibre
technology to create an environment that supports consistent and thorough
verification of IP designs while maximizing productivity and efficiency.
Block/chip designers and 3DIC designers can also take advantage of Calibre Shift Left
solutions for their unique verification challenges.
For more details about the full range of Calibre Shift Left solutions, and the tools and
strategies available, visit our Shift left with Calibre solutions page. The shift left
resource library provides direct access to papers, videos, and other shift left
resources.

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About the author
Terry Meeks
Terry Meeks is a product engineering director for the
Calibre LVS applications at Siemens EDA, a part of
Siemens Digital Industries Software. Terry works with
customers and engineering to develop new and
enhanced EDA tools that solve the growing challenges in
advanced physical verification, circuit modeling, and
analysis. Terry has over 27 years in working with the
Calibre tools and has also worked in the industry for over
45 years. Terry received his BSCS and his MSCS from
California State University in Fullerton. He may be
reached at terry.meeks@siemens.com.
© Siemens 2023.
© Siemens 2023
A list of relevant Siemens trademarks can be found here.
Other trademarks belong to their respective owners.
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DIGITAL INDUSTRIES SOFTWARE

Author: Terry Meeks

Shift left verification

Shift left verification in the IP design flow

Shift left verification for IP designers

Shift left verification for IP design types

SIEMENS DIGITAL INDUSTRIES SOFTWARE 2

Intellectual property (IP) is a standalone reusable component that can be

IP can be acquired from dedicated IP design companies, or developed in-house. In

SIEMENS DIGITAL INDUSTRIES SOFTWARE 3

Custom IP is typically created for a specific design, or to implement functionality that

SIEMENS DIGITAL INDUSTRIES SOFTWARE 4

Figure 1. Traditional IP design verification flow.

SIEMENS DIGITAL INDUSTRIES SOFTWARE 5

Shift left verification

SIEMENS DIGITAL INDUSTRIES SOFTWARE 6

Shift left verification in the IP design

SIEMENS DIGITAL INDUSTRIES SOFTWARE 7

Figure 3. IP design or integration is performed in parallel with multiple design

SIEMENS DIGITAL INDUSTRIES SOFTWARE 8

the verification tools as each stage evolves. Because verification is constantly

SIEMENS DIGITAL INDUSTRIES SOFTWARE 9

Figure 4. Shift left physical verification in IP design flows.

Shift left verification for IP designers

SIEMENS DIGITAL INDUSTRIES SOFTWARE 10

On-demand DRC verification

Integration and runtime invocation

Debug integration and guidance

SIEMENS DIGITAL INDUSTRIES SOFTWARE 11

Automated waiver management

SIEMENS DIGITAL INDUSTRIES SOFTWARE 12

Automated design layout optimization

• Automated via insertion adds Calibre nmDRC-clean vias to moderate the

Advanced fill functionality

• Calibre YieldEnhancer SmartFill and engineering change order (ECO) fill

Multi-patterning color assignment

SIEMENS DIGITAL INDUSTRIES SOFTWARE 13

Figure 5. IP coloring for multi-patterning assignment must anticipate multiple

SIEMENS DIGITAL INDUSTRIES SOFTWARE 14

Shift left verification for IP design

SIEMENS DIGITAL INDUSTRIES SOFTWARE 15

Another custom IP design challenge is the inadvertent creation of short circuits.

SIEMENS DIGITAL INDUSTRIES SOFTWARE 16

Figure 6. Continuous improvement in the Calibre nmPlatform engines not only

SIEMENS DIGITAL INDUSTRIES SOFTWARE 17

Commercial IP design is a highly competitive market, while in-house IP design allows

SIEMENS DIGITAL INDUSTRIES SOFTWARE 18

siemens.com/software Siemens Digital Industries Software helps

About the author

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