Microprocessor Programming

and Interfacing
Lecture 02 & 03
19/01/23 - 21/01/23

Prof. Runa Kumari

Associate Professor
EEE Department
BITS Pilani Hyderabad Campus
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
 Recap
Previous Lecture
• Course details.
• Block diagram of a computer.
• Historical background including ENIAC, Intel 4004, 8008, 8080, 8085, 8086.
• Alternate Microprocessors: Motorola 68000.

Today’s Lecture
• Block diagrams of a microprocessor and instruction cycles
• Different buses and the nature of data transmission in them.
• Size of a P.
• Processor Memory
• Instruction Set Architecture (ISA): RISC, CISC
• Basic Parallel Techniques
• Flynn’s Taxonomy

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 Instructions in Microprocessor
What is an instruction?

Tells the microprocessor or p what action to perform.

How does a microprocessor handle an instruction?

1. Fetch Cycle
The fetch cycle takes the instruction required from memory, stores it in the
instruction register.

2. Execute Cycle
The actual actions which occur during the execution cycle of an instruction.

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 Add
Bus Microprocessor

-Fetches Instruction
Microprocessor Data
Bus

-Executes Instruction
Control
signals

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 Introduction to Microprocessors

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 Introduction to Microprocessors

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 Size of Microprocessor
SIZE OF A MICROPROCESSOR

• Size of Data Bus

• Size of Registers
• Size of ALU

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 Microprocessor Bus
PROCESSOR BUS ADDRESS BUS:
No of Address lines
• 20 lines –A19–A0
• 1 M Byte of memory can be addressed

DATA BUS:
No of Data lines
• 16 lines –D15–D0
• 64K

CONTROL LINES:
-Active low signals
• MEMR
• MEMW
• IOR
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 Memory of Microprocessors
 PROCESSOR MEMORY
• ROM
Non-Volatile
Read Only
• RAM
Volatile
Random Access Memory

 MEMORY DATA SIZE

• Bit Organized
• Nibble Organized
• Byte Organized
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 Interface Connections to Memory

Add Bus

Memory -
Registers to hold bits
Data Bus
Memory
Read

Write

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 Instruction Set Architecture
What is ISA (Instruction Set Architecture)?
An agreement about how the software will communicate with
the processors.

Description of ISA addresses the followings:

• What instructions are available?
• What addressing modes are available?
• What is the format of data?
• How many and what kind of registers are available?
• What condition codes, if any, are defined?
• How are exceptions handled?
• How are interrupts handled?

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 Instruction Set Architecture
What are the points not specified in ISA?
• How fast will a particular instruction go?
• How is an instruction implemented?
• What are procedure calling conventions?
• What are cache replacement policies?
• What happens on a page fault?

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 Recap
Previous Lecture
• Block diagrams of a microprocessor and instruction cycles
• Different buses and the nature of data transmission in them.
• Size of a P.
• Processor Memory

Today’s Lecture
• Instruction Set Architecture (ISA): RISC, CISC
• Basic Parallel Techniques
• Flynn’s Taxonomy

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 ISA Continued…
Types of Instructions sets
 Stack
 Only of historical interests.
 Java Virtual Machine operates on a stack-based ISA.
 Accumulator
 Only of historical interests.
 x86 architecture has some aspects of accumulator architecture.
 Registers are referred to as special-purpose registers.
 General Purpose Register
 Load/Store (Register to Register)
 Only load and store instructions access main memory.
 Rest all instructions act only on registers.
 RISC architecture is based on Load/Store architecture
 Examples: SPARC, MIPS, AlphaXP, PowerPC etc.
 Register-Memory
 Any instruction may access main memory.
 CISC architecture is based on this.
 Examples: VAX, x86, MC68000
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 Processors

ISA

 CISC (Complex Instruction Set Computer)

Operands for Arithmetic/Logic operation can be in Register/ Memory

 RISC (Reduced Instruction Set Computer)

Operands for Arithmetic/Logic operation only in Registers
Register –Register Architecture

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 RISC vs CISC
Goal: Multiply data in mem A with B
and put it back in A

CISC:
MUL A,B

RISC:
LDA R0,A
LDA R1,B
MUL R0,R1
STR A,R0

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 RISC vs CISC

CPU-SPEEDUP

1 Instruction Per Cycle (1 IPC)

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 ISA Continued…
Brief Idea about RISC and CISC
 RISC: Reduced Instruction Set Computer
 It has simpler instructions and thus simple instruction decoding.
 More general-purpose registers.
 Instruction takes one clock cycle in order to get executed.
 Instruction comes under the size of a single word.
 Pipeline can be easily achieved.
 Few data types and thus simpler addressing modes.

 CISC: Complex Instruction Set Computer

 Instructions are complex, and thus complex instruction decoding.
 Instructions may take more than one clock cycle in order to get executed.
 Instruction is larger than a one-word size.
 Lesser general-purpose registers since the operations get performed only in
the memory.
 More data types and thus complex addressing modes.
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 ISA Continued…

What is Operand?
 An operand is a value that an instruction operates on.
 By giving an instruction type and an addressing mode, we have somehow specified
some operands for the instruction.

Various Operand Types

 Integers: 8-bit (characters), 16-bit (words), 32-bit (doubleword), 64-bit (quadword).

 Single or double precision floating point numbers: Generally 32 or 64-bit.
 Binary coded decimal or BCD: Packed or Unpacked.
 Strings: Variable length (not all ISA supports).

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 ISA Continued…
Memory Addressing
 One of most important functions of ISA.
 Most computers divide memory into 8-bit.
 ISA decides how to format these bytes into larger structures.

 Endianness
 Big Endian or Little Endian.
 MSB at first or last.
 Alignment
 Some ISAs, for implementation reasons, require that memory accesses be
aligned.
 Ex: Access to an 8-byte quadword must be through an address divisible by 8
in Alpha, otherwise the offending load or store instruction will generate an
exception resulting in an error.
 Addressing Modes
 The way in which a machine instruction accesses memory.
 Instruction contains some data that is used to come up with the effective
address that will be used in some transactions with the memory system.
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 ISA Continued…
Types of Instructions
 Data transfer instructions.
 Arithmetic and logical instructions.
 Control transfer instructions.
 Floating point instructions.

Instructions Encoding

 We shall take an example: MIPS Instruction Set.

 The instruction set is 32-bit long (Consider 0 to be LSB and 31 to be MSB)
 32 integer registers with most of them being general purpose.
 Register R0 is always set to 0.
 First 6 bits and bits 31-26 specify an opcode giving information about what
instruction is supposed to be executed.
 MIPS register and addresses are 64-bit.
 MIPS is byte-addressable and requires aligned access with the capability to switch
between Big or Little Endian.
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 ISA Continued…
Instructions Encoding Continued…

 I-type Instruction: Instructions with immediate operand.

 R-type Instruction: Register-Register Arithmetic and logic instructions.
 J-type Instruction: Jump to PC-relative address.

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 ISA Continued…
Instructions Encoding Continued…

I-Type: MOV AX, 2050H

R-Type: MOV AX, BX

J-Type: JMP BX

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 Basic Parallel Techniques
How to improve computational speed?

 Usage of faster circuitry, multiple registers, cache memory etc.

 Instruction pipelining.
 New inputs are accepted at one end before previously accepted inputs
appear as outputs at the other end.
 Improves speed dramatically
 Susceptible to hazards like resource, data, and control.

Example: Parallel Execution

Serial Execution

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 Basic Parallel Techniques

• Pipelining
• Replication

INSTRUCTION PIPELINES

Instruction:
• Fetch
• Decode
• Execute

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 Basic Parallel Techniques
Instruction Pipelining Operations

1. Fetching the instruction from memory (IF)

2. Decoding the obtained instruction (ID)
3. Calculating the effective address (EA)
4. Fetching the operands from the given memory (OF)
5. Execution of the instruction (EX or IE)
6. Storing the result in a proper place (WB or OS)

Example:

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 VLIW & SUPERSCALAR ARCHITECTURE

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 Parallel Computing: Flynn’s Taxonomy
Parallel Computing

 Jobs are broken into discrete parts that can be executed concurrently.
 Each part is further broken down into a series of instructions.
 Instructions from each part are executed simultaneously on different
CPUs.

 Parallel computing can be achieved using

 A single computer with multiple processors or
 Multiple computers connected via a common network or
 Combination of both

 Parallel systems are more difficult to program than computers with a

single processor because the architecture of parallel computers varies
accordingly and the processes of multiple CPUs must be coordinated
and synchronized.
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 Parallel Computing: Flynn’s Taxonomy
Flynn’s Classifications

 Based on the number of instructions and data streams.

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 Parallel Computing: Flynn’s Taxonomy

SISD SIMD

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 Parallel Computing: Flynn’s Taxonomy

MISD

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 Parallel Computing: Flynn’s Taxonomy

MIMD

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 EVOLUTION OF MICROPROCESSOR

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 Quad- core
microprocessor

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 End of Lecture 3

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