SIZING A CHAIN OF INVERTERS

DELAY OPTIMIZATION IN A DATA

PATH

References
Weste and Rabaey
A chain of inverters
Key Points
Choosing the Right Number of Stages in an
Inverter Chain
• The optimum value can be found by differentiating the minimum delay
expression by the number of stages, and setting the result to 0.

• It is found that the optimal number of stages equals N = ln(H), and the
effective fan out (h) of each stage is set to = 2.71828 = e.

N = ln(H)

• However, it unneccarily leads to large size inverters in the chain which is

not practically possible. So FO4 (N=4) factor is used.

• Example for super buffer: lets see document 4

 Example for super buffer: Document 4
Example: The sum of tPHL + tPLH for the inverter driving a load capacitance of 20
pF.

With the super buffer inserted between on chip and off chip load

Delay is approximately 0.27 ns

Much faster !
Picking up the right number of stages
Method of logical effort
• Designing a circuit to achieve the greatest speed or to meet a delay
constraint presents a bewildering array of choices.
• Which of several circuits that produce the same logic function will be
fastest?
• How large should a logic gate’s transistors be to achieve least delay?
And how many stages of logic should be used to obtain least delay?
Sometimes, adding stages to a path reduces its delay!
• The method of logical effort is an easy way to estimate delay in a
CMOS circuit. We can select the fastest candidate by comparing delay
estimates of different logic structures.
• The method also specifies the proper number of logic stages on a path
and the best transistor sizes for the logic gates.
Generalized expression to analyse the multipath delays
We modify the basic delay equation
• Electrical Effort/stage effort (h)
The electrical effort h describes how the electrical environment of the
logic gate affects performance.

where Cout is the capacitance that loads the output of the logic gate and Cin
is the capacitance presented by the input terminal of the logic gate.
Electrical effort is also called fan out by many CMOS designers

• Parasitic delay (p)

The parasitic delay is defined as the unloaded delay of the complex gates to
the inverter.
• The logical effort (g)
It represents the fact, for a given load, complex gates have to work harder
than an inverter to produce a similar response. It captures the effect of the
logic gate’s topology on its ability to produce output current.

• Effort delay (f)

The effort delay depends on the load and on properties of the logic gate
driving the load.
 𝐶𝑖𝑛𝑡,𝑔𝑎𝑡𝑒
Calculation of p values: 𝑝 =
𝐶𝑖𝑛𝑡,𝑖𝑛𝑣

𝑝=

𝑝=

𝑝=
 𝐶𝑖𝑛,𝑔𝑎𝑡𝑒
Calculation of g values: g=
𝐶𝑖𝑛,𝑖𝑛𝑣

𝑔=

𝑔=

𝑔=
Example
Estimate the delay of a fanout-of-4 (FO4) inverter. Each inverter is identical.
Multistage Logic Networks
• Path Logical Effort (G)
The logical effort along a path compounds by multiplying the logical efforts
of all the logic gates along the path. We use the uppercase symbol G to
denote the, path logical effort, so that it is distinguished from g, the logical
effort of a single gate in the path. The subscript i indexes the logic stages
along the path.

• Path Electrical Effort (H)

The electrical effort along a path through a network is simply the ratio of
the capacitance that loads the last logic gate in the path to the input
capacitance of the first gate in the path. We use an uppercase symbol H to
indicate the electrical effort along a path.
 Multistage Logic Networks
• Branching Effort (B)
When fan out occurs within a logic network, some of the available drive
current is directed along the path we are analyzing, and some is directed off
that path. We define the branching effort b at the output of a logic gate to be

where Con_path is the load capacitance along the path we are analyzing and
Coff_path is the capacitance of connections that lead off the path.
Note that if the path does not branch, the branching effort is one. The
branching effort along an entire path B is the product of the branching effort
at each of the stages along the path.
 Multistage Logic Networks
• We can now define the path effort F

The path delay D is the sum of the delays of each of the stages of logic in
the path.

The path effort delay is simply

and the path parasitic delay is

Condition for Minimum Delay
• Optimizing the design of an N-stage logic network proceeds from a very
simple principle that we have already proved in sizing for delay of chain of
inverters:
The path delay is least when each stage in the path bears the same stage effort.
This minimum delay is achieved when the stage effort is:

A hat over a symbol indicate an expression that achieves minimum delay.

Combining these equations, we obtain the principal result of the method of

logical effort, which is an expression for the minimum delay achievable along a
path:
Example: Consider the path from A to B involving three two-input NAND gates shown in
figure. The input capacitance of the first gate is C, and the load capacitance is also C.
(i) What is the least delay of this path?
(ii) How should the transistors be sized to achieve least delay?
Example: A control unit generates a signal from a unit-sized
inverter. The signal must drive unit-sized loads in each bit-slice of a
64-bit datapath. The designer can add inverters to buffer the signal
to drive the large load. Assuming polarity of the signal does not
matter, what is the best number of inverters to add and what delay
can be achieved?
Given: 𝜏𝑝0 = 1 𝑝𝑠, G=1, H=64, B=1

Design (a) (b) (c) (d)

N 1 2 3 4
F 64 64 64 64
𝑓መ 64 8 4 2.8
P 1 2 3 4
෡
𝐷 65 18 15 15.3
THANK YOU!