492 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO.

3, MARCH 2007

Analytic Charge Model for

Surrounding-Gate MOSFETs
Bo Yu, Student Member, IEEE, Wei-Yuan Lu, Student Member, IEEE,
Huaxin Lu, Student Member, IEEE, and Yuan Taur, Fellow, IEEE

Abstract—This paper presents an analytic charge model for

surrounding-gate MOSFETs. Without the charge sheet approxi-
mation, the model is based on closed-form solution of Poisson’s
equation, current continuity equation, and Ward–Dutton linear
charge partition. It continuously covers all the operation regions,
i.e., linear, saturation, and subthreshold, with unique analytic
expressions. The physics-based nature makes this model free of
fitting parameters and hence predictive. In addition, it is inher-
ently not source-referenced to avoid asymmetries. It is shown that
the current–voltage characteristics generated by this model agree
with the numerical simulation results.
Index Terms—Compact model, MOSFETs, surrounding-
gate (SG).

I. INTRODUCTION

A S SINGLE-GATE CMOS scaling is approaching the

limit imposed by gate oxide tunneling, multiple-gate
MOSFETs such as double-gate (DG), triple-gate, quadruple-
Fig. 1. Schematic diagram of an SG MOSFET.

gate, and surrounding-gate (SG) MOSFETs are becoming
intense research subjects because of their better gate con-
trol ability and scaling potential [1]. Among these advanced
structures, DG MOSFETs are the most feasible in terms of
technology, whereas in theory, SG MOSFETs can provide the
best electrostatic integrity.
To avoid severe numerical problems like convergence,
CMOS compact modeling has shifted from piecewise solutions
to unified ones. Fortunately, continuous analytic drain–current
models have been developed for DG [2] and SG [3] MOSFETs,
respectively. These two models are derived directly from the
Pao–Sah integral [4] for DG and SG MOSFETs with undoped
(or lightly doped) silicon body. It has been validated by nu-
merical simulations that these models are accurate in all of
the three operation regions and properly describe the transition
behaviors.
However, drain–current model is not enough for circuit sim-
ulation [5]. In order to calculate the dynamic behavior of the
device and hence to enable ac and transient circuit simulation,
terminal-charge model for DG MOSFETs has been developed
very recently [6]. To define the terminal charges for DG
Manuscript received July 19, 2006; revised December 5, 2006. This work
was supported in part by Semiconductor Research Corporation (SRC) Project
under Grant 2005-VJ-1352.001. The review of this paper was arranged by
Editor C. McAndrew.
The authors are with the Department of Electrical and Computer Engineer-
MOSFETs, the model uses Ward–Dutton charge partition
method [7] and has been proven to be very accurate by numer-
ical simulation results. However, the resulting expressions for
the terminal charges and capacitance coefficients are not com-
posed of fundamental functions but of numerical integrations,
which are time-consuming to be carried out.
In this paper, an analytic charge model for SG MOSFETs
will be proposed. Starting from the exact solution of Poisson’s
equation, we derive the model from Ward–Dutton charge parti-
tion and current continuity equation without the need for charge
sheet approximation [8]. Every terminal charge or capacitance
coefficient is described by one analytic function, which con-
tinuously covers all the operation regions in the absence of
nonphysical fitting parameters. Our model is analogous with
that for DG MOSFETs [6], but fortunately, there are only power
functions and logarithmic functions in the final expressions.
The model has been validated by numerical simulations.
II. ANALYTIC CHARGE MODEL FOR SG MOSFETs
Consider an undoped (or lightly doped) cylindrical SG
MOSFET schematically shown in Fig. 1. Under the gradual
channel approximation, Poisson’s equation takes the following
form with only the mobile-charge (electrons) term:
d2 ψ 1 dψ q q(ψ−V )

ing, University of California, San Diego, La Jolla, CA 92093 USA (e-mail: 2

+ = ni e kT (1)
dρ ρ dρ si
boyu@ucsd.edu; taur@ece.ucsd.edu).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. where q is the electronic charge, si is the permittivity of silicon,
Digital Object Identifier 10.1109/TED.2006.890264 ni is the intrinsic carrier density, ψ(ρ) is the electrostatic

0018-9383/$25.00 © 2007 IEEE

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 YU et al.: ANALYTIC CHARGE MODEL FOR SURROUNDING-GATE MOSFETs 493

potential, and V is the electron quasi-Fermi potential, which

is constant in the ρ-direction. Here, we consider an nMOSFET
with qψ/kT
1 so that the hole density is negligible.
The solution of (1) has been presented in a previous paper by
Jimenez et al. [3]. We reorganize it as

  
2kT R q 2 ni (1−α)ρ2
ψ(ρ) = V − ln 1−
q 2 2si kT (1−α) R2
(2)

where α is to be determined by the boundary condition which

has a final form as

1 1−α
ln(1 − α) − ln α + s
2 α
  
Fig. 2. Normalized terminal charges Qg , Qs , and Qd of an SG MOSFET as
q(Vg − ∆φ − V ) 2 2si kT functions of Vds . The normalization constant is 8πsi L(kT /q)(1 − αs )/αs .
= − ln . (3)
2kT R q 2 ni
dy = −µ(2πR)Qi dV /Ids leads to y = L[f (α) − f (αs )]/
Here, s = 2si ln(1 + (tox /R))/ox is a structural parameter, [f (αd ) − f (αs )]. With this result, we can calculate the terminal
ox is the permittivity of oxide, Vg is the voltage applied to charges as
the gate, R is the radius of silicon cylinder, tox is the oxide
L
thickness, and ∆φ is the work function of gate electrode with
respect to the intrinsic silicon. The range of α is 0 < α < 1. Qg = − 2πR Qi (y)dy
Because (3) is an implicit equation of α, the general approach to 0
solve α is Newton–Ralphson numerical method. But recently, αd
we have developed an accurate explicit solution for α [9]. µ 2 dV
= (2πR) Q2i (α) dα
From Gauss’ law, the total mobile charge per unit gate Ids dα
αs
area Qi = 2si (2kT /q)(1 − α)/α/R. dV /dα can also be ex-
pressed as a function of α by differentiating (3): dV /dα = kT g(αd )−g(αs )
= 8πsi L
(kT /q)[1/(1 − α) + 2/α + 2s/α2 ]. Therefore, the drain cur- q f (αd )−f (αs )
rent can be calculated as L
y kT
Vd Qd = 2πR Qi (y)dy = 8πsi L Wsd
2πR L q
Ids = µ Qi (V )dV 0
L
Vs L
y kT
αd Qs = 2πR 1− Qi (y)dy = 8πsi L Wds (5)
2πR dV L q
=µ Qi (α) dα 0
L dα
αs
 2 where
8πsi kT
=µ [f (αd ) − f (αs )] (4)
L q f (αi ) [g(αj ) − g(αi )] + [h(αj ) − h(αi )]
Wij = (6)
[f (αj ) − f (αi )]2
where µ is the effective mobility, L is the channel length,
Vs and Vd are the voltages applied to the source and drain,
and functions g(α) and h(α) are defined as
respectively, αs and αd are the solutions to (3) corresponding
to V = Vs and V = Vd , respectively, and f (α) = (−2/α −    
1 3 2 2 2
ln α) + s(−1/α2 + 2/α). g(α) = + − + ln α + s − + −
α2 α 3α3 α2 α
Analytic expressions for the three terminal charges, i.e., Qg ,
 
Qs , and Qd , associated with gate, source, and drain, respec- 4 5 1 1 − 3α (ln α)2
tively, are required for circuit simulation of SG MOSFETs. h(α) = − 3 + 2 + − ln α +
3α 2α α α2 2
The gate charge can be computed directly by integrating the  
charge density along the channel. For the source and drain 3 43 9 2 − 6α + 6α2
−s − 3+ 2+ ln α
charges, it is physically sound to adopt Ward–Dutton linear- 2α4 9α 2α 3α3
charge-partition method, which is widely accepted for bulk  
MOSFETs [7] and has also been proven to be reasonable for 2 2 10 2
−s2
− 4+ 3− 2 . (7)
DG MOSFETs [6]. Integrating the current continuity equation 5α5 α 3α α

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 494 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 3, MARCH 2007

Fig. 3. Normalized capacitance coefficients of an SG MOSFET as functions of Vgs obtained from the analytic model (solid lines) in comparison with the 2-D
numerical simulation results (open circles). The normalization constant is 4πsi L/s. (a) Vds = 2 V. (b) Vds = 1 V. (c) Vds = 0 V.

The imaginary component of the small-signal behavior of L2 gds

2
Qg gds (Qs − Qd )gm
a three-terminal device can be characterized by nine non- Cdg = − + −
µIds Ids Ids
reciprocal capacitance coefficients. Here, we shall adopt the
1 − αd [(1 − αd )/αd + Wsd + Wds ]
convention in which the capacitance coefficient Cmn is defined = 8πsi L
as δmn × ∂Qm /∂Vn , where m, n = g, s, d, and δmn is equal αd f (αs ) − f (αd )
to 1 if m = n, and −1, otherwise. For simplicity, we will only 1/αs − 1/αd
list the results of four linearly independent components from + (Wds − Wsd )
f (αs ) − f (αd )
which all the nine capacitance coefficients can be obtained
directly based on the charge conservation law [5]: (Qs − Qd )gds
Csd =
Ids
1 − αd (Wds − Wsd )
L2 (gds + gm )2 Qg (gds + gm ) = 8πsi L . (8)
Cgs = − αd f (αd ) − f (αs )
µIds Ids

1 − αs [(1 − αs )/αs + Wsd + Wds ] Here, transconductance gm and conductance gds are given by
= 8πsi L
αs f (αd ) − f (αs )  
∂Ids 8πsi kT 1 1
gm = =µ −
L2 gds
2
Qg gds ∂Vgs Vds L q αs αd
Cgd = − +
µIds Ids ∂Ids 8πsi kT 1 − αd
gds = =µ (9)
∂Vds L q αd
1 − αd [(1 − αd )/αd + Wsd + Wds ] Vgs
= 8πsi L
αd f (αs ) − f (αd ) where Vgs = Vg − Vs and Vds = Vd − Vs .

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 YU et al.: ANALYTIC CHARGE MODEL FOR SURROUNDING-GATE MOSFETs
Fig. 4. Normalized capacitance coefficients of an SG MOSFET as functions
of Vds obtained from the analytic model (solid lines) in comparison with the
2-D numerical simulation results (open circles). The normalization constant is
4πsi L/s.
Until now, the analytic charge and capacitance coefficient
model for SG MOSFETs has been derived. Compared with
the model for DG MOSFETs [6], this model is more suitable
for the implementation in circuit-simulation programs because
no numerical integrations are involved in the final expressions
anymore, and the most time-consuming parts are just loga-
rithmic functions. It is worthy to mention that this model is
nonsource-referenced and automatically preserves the symme-
try with respect to source–drain interchange. This property can
be obviously observed in the final expressions of the terminal
charges as well as the capacitance coefficients.
All these analytic expressions have infinite order of continu-
ity; however, they become the form 0/0, i.e., both the numerator
and denominator are zero, when Vs = Vd . Inasmuch as the
indeterminacies of type 0/0 will cause problems in numerical
implementation, we have to provide expressions for the exact
values at Vs = Vd , which are the limits of general expressions
as Vd approaches Vs . These limits can be calculated through
L’Hospital’s rule or Taylor expansion. After a lengthy deriva-
tion, we finally obtain the results as
kT 1 − αs
Qg = − 2Qs = −2Qd = 8πsi L (10)
q αs
Cgg = 2Cgs = 2Cgd = 2Csg = 2Cdg = −6Csd = −6Cds
1 − αs
= 3Css = 3Cdd = 8πsi L . (11)
2αs − αs2 + 2s(1 − αs )
Fig. 2 plots the terminal charges as functions of drain volt-
age. In this case, αs is small. When Vds = 0, Qg = −2Qs =
−2Qd  8πsi LkT /qαs . When the device enters saturation re-
gion, Qg  −10Qs /6  −10Qd /4  10(8πsi LkT /qαs )/15
according to (5). These approximate relations are exactly the
same as those for bulk MOSFETs [5] and DG MOSFETs [6]
and are clearly reflected in Fig. 2.
In Figs. 3 and 4, we have compared our capacitance coef-
ficient model with the numerical simulation results of a long-
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495
channel SG MOSFET. Because we use cylindrical coordinate
instead of Cartesian coordinate, the numerical simulation is
essentially 2-D. Fig. 3(a), where Vds = 2 V, shows that the gen-
eral expressions of the model are in complete agreement with
the numerical simulations. In this case, the device is always in
saturation region, and it is reasonable to assume that αd = 1.
Under this approximation, we can easily obtain the simple
relation between capacitance coefficients from (8): Cgg = Cgs ,
Csg = Css , Cdg = −Cds , and Cgd = Csd = Cdd = 0. If we
further consider the well-above threshold region, where αs is
small, we can even derive the simplified approximate expres-
sions for these capacitance coefficients as follows:
10 10 10 4πsi L αs
Cgg  Csg  Cdg  1− . (12)
6 4 15 s s
Fig. 3(b) has proven our model to be accurate for the transi-
tion from saturation to nonsaturation, whereas Fig. 3(c) indi-
cates the validity of (11) for the special case of Vs = Vd . In
Fig. 4, the capacitance coefficients from both analytic model
and numerical simulation are compared as functions of Vds .
We can clearly observe the transition between two degenerate
cases, which have been introduced above: One degeneracy is
from source–drain-interchange symmetry at Vds = 0; another
is induced by saturation at the drain end.
III. CONCLUSION
In conclusion, we have presented an analytic charge model
for SG MOSFETs beyond charge sheet approximation. Inas-
much as the essential physics has been preserved, it has been
verified by numerical simulations that charge and capacitance
coefficient behaviors in all the operation and transition re-
gions are properly described by continuous functions without
ad hoc fitting parameters. These continuous functions are sim-
ply composed of fundamental functions, making it suitable and
easy to implement this predictive model in circuit-simulation
programs. Furthermore, the model is nonsource-referenced and
preserves the source–drain symmetry inherently. With all these
favorable features, the model is an ideal candidate of compact
model for ac and transient circuit simulation.
R EFERENCES
[1] J.-P. Colinge, “Multiple gate SOI MOSFETs,” Solid State Electron.,
vol. 48, no. 6, pp. 897–905, Jun. 2004.
[2] Y. Taur, X. Liang, W. Wang, and H. Lu, “A continuous, analytic drain-
current model for DG MOSFETs,” IEEE Electron Device Lett., vol. 25,
no. 2, pp. 107–109, Feb. 2004.
[3] D. Jimenez, B. Iniguez, J. Sune, L. F. Marsal, J. Pallares, J. Roig,
and D. Flores, “Continuous analytic I−V model for surrounding-gate
MOSFETs,” IEEE Electron Device Lett., vol. 25, no. 8, pp. 571–573,
Aug. 2004.
[4] H. C. Pao and C. T. Sah, “Effects of diffusion current on characteristics of
metal-oxide (insulator)-semiconductor transistors,” Solid State Electron.,
vol. 9, no. 10, pp. 927–937, Oct. 1966.
[5] Y. Tsividis, Operation and Modeling of the MOS Transistor. Boston, MA:
McGraw-Hill, 1999.
[6] H. Lu and Y. Taur, “An analytic potential model for symmetric and asym-
metric double gate MOSFETs,” IEEE Trans. Electron Devices, vol. 53,
no. 5, pp. 1161–1168, May 2006.
[7] D. E. Ward and R. W. Dutton, “A charge-oriented model for MOS tran-
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pp. 703–708, Oct. 1978.
 496
[8] J. R. Brews, “A charge sheet model of the MOSFET,” Solid State Electron.,
vol. 21, no. 2, pp. 345–355, Feb. 1978.
[9] B. Yu, H. Lu, M. Liu, and Y. Taur, Accurate explicit models for double-gate
and surrounding-gate MOSFETs. in preparation.
Bo Yu (S’05) received the B.E. degree in electrical
engineering and the M.S. degree in physics from
the University of Science and Technology of China,
Hefei, China, in 2001 and 2004, respectively. He
is currently working toward the Ph.D. degree in
electrical and computer engineering at the University
of California, San Diego, La Jolla, CA.
His current research interests focus on nanoelec-
tronics, including design and modeling of novel
nanometer-scale MOSFETs based on III–V com-
pound as well as silicon. He is currently with the
University of California.
Wei-Yuan Lu (S’04) received the B.S. and M.S. de-
grees in electrical engineering from National Cheng
Kung University, Tainan, Taiwan, R.O.C., in 1994
and 1996, respectively. He is currently working to-
ward the Ph.D. degree in electrical and computer en-
gineering at the University of California, San Diego,
La Jolla, CA.
His research interests include analyses, design,
and physical modeling of ultrathin-body fully de-
pleted silicon-on-insulator (SOI) and multiple-gate
MOSFETs. He is currently with the University of
California.
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 3, MARCH 2007
Huaxin Lu (S’02) received the B.S. degree in elec-
trical engineering from Tsinghua University, Beijing,
China, in 2002. He is currently working toward
the Ph.D. degree in electrical and computer engi-
neering at the University of California, San Diego,
La Jolla, CA.
His research interests include compact modeling
of bulk, double-gate (DG), and multigate MOSFETs.
He is currently with the University of California.
Yuan Taur (M’83–SM’90–F’98) received the B.S.
degree in physics from National Taiwan University,
Taipei, Taiwan, R.O.C., in 1967 and the Ph.D. de-
gree in physics from the University of California,
Berkeley, in 1974.
From 1975 to 1979, he was with the NASA
Goddard Institute for Space Studies, New York, NY,
working on low-noise Josephson junction mixers for
millimeter-wave detection. From 1979 to 1981, he
was with the Rockwell International Science Center,
Thousand Oaks, CA, working on II–VI semicon-
ductor devices for infrared sensor applications. From 1981 to 2001, he was
with the Silicon Technology Department, IBM Thomas J. Watson Research
Center, Yorktown Heights, New York, where he was the Manager of exploratory
devices and processes. The areas in which he has worked and published include
latchup-free 1-µm CMOS, self-aligned TiSi2 , 0.5-µm CMOS and BiCMOS,
shallow trench isolation, 0.25-µm CMOS with n+ /p+ polygates, SOI, low-
temperature CMOS, and 0.1-µm CMOS. Since October 2001, he has been a
Professor with the Department of Electrical and Computer Engineering, Uni-
versity of California, San Diego, La Jolla, CA. He has authored or coauthored
over 130 technical papers and is the holder of 12 U.S. patents. He coauthored
the book Fundamentals of Modern VLSI Devices (New York: Cambridge
University Press, 1998). He is currently with the University of California.
Dr. Taur is currently the Editor-in-Chief of the IEEE ELECTRON DEVICE
LETTERS. He has served on the technical program committees, has been a
Panelist for the Device Research Conference and the International Electron De-
vice Meeting, and has been a Program Chairman for the Symposium on VLSI
Technology. He was a recipient of four Outstanding Technical Achievement
Awards and six Invention Achievement Awards over his IBM career and was
profiled in Marquis Who’s Who in the World (2001).