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Computer Architecture
A Quantitative Approach
SIXTH EDITION
John L. Hennessy
Stanford University
David A. Patterson
University of California, Berkeley
WITH CONTRIBUTIONS BY
Krste Asanović
University of California, Berkeley
Jason D. Bakos
University of South Carolina
Robert P. Colwell
R&E Colwell & Assoc. Inc.
Abhishek Bhattacharjee
Rutgers University
Thomas M. Conte
Georgia Tech
José Duato
Proemisa
Diana Franklin
University of Chicago
David Goldberg
eBay
Norman P. Jouppi
Google
Sheng Li
Intel Labs
Naveen Muralimanohar
HP Labs
Gregory D. Peterson
University of Tennessee
Timothy M. Pinkston
University of Southern California
Parthasarathy Ranganathan
Google
David A. Wood
University of Wisconsin–Madison
Cliff Young
Google
Amr Zaky
University of Santa Clara
Copyright
Morgan Kaufmann is an imprint of Elsevier
50 Hampshire Street, 5th Floor, Cambridge, MA 02139, United States
Notices
Knowledge and best practice in this field are constantly changing.
As new research and experience broaden our understanding,
changes in research methods, professional practices, or medical
treatment may become necessary.
To the fullest extent of the law, neither the Publisher nor the
authors, contributors, or editors, assume any liability for any injury
and/or damage to persons or property as a matter of products
liability, negligence or otherwise, or from any use or operation of
any methods, products, instructions, or ideas contained in the
material herein.
ISBN: 978-0-12-811905-1
Cover
Title
Copyright
Dedication
Foreword
Preface
Why We Wrote This Book
This Edition
Chapter Structure
Supplemental Materials
Concluding Remarks
Acknowledgments
1.1 Introduction
1.7 Dependability
References
2.1 Introduction
2.6 Putting It All Together: Memory Hierarchies in the ARM Cortex-A53 and
Intel Core i7 6700
References
3.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation
3.12 Putting It All Together: The Intel Core i7 6700 and ARM Cortex-A53
References
4.1 Introduction
4.7 Putting It All Together: Embedded Versus Server GPUs and Tesla Versus
Core i7
4.8 Fallacies and Pitfalls
References
5. Thread-Level Parallelism
Abstract
5.1 Introduction
References
6. Warehouse-Scale Computers to Exploit Request-Level and Data-
Level Parallelism
Abstract
6.1 Introduction
References
7. Domain-Specific Architectures
Abstract
7.1 Introduction
7.9 Putting It All Together: CPUs Versus GPUs Versus DNN Accelerators
References
A.1 Introduction
References
B.1 Introduction
References
C.1 Introduction
References
References
References
F.9 Internetworking
Exercises
References
Exercises
References
Reference
References
References
Acknowledgments
References
References
References
References
References
References
References
M.10 The History of Magnetic Storage, RAID, and I/O Buses (Appendix D)
References
References
Index
“Hennessy and Patterson wrote the first edition of this book when
graduate students built computers with 50,000 transistors. Today,
warehouse-size computers contain that many servers, each consisting
of dozens of independent processors and billions of transistors. The
evolution of computer architecture has been rapid and relentless, but
Computer Architecture: A Quantitative Approach has kept pace, with
each edition accurately explaining and analyzing the important
emerging ideas that make this field so exciting.”
James Larus, Microsoft Research