IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO.
4, APRIL 2018 3125
Ripple Mitigation With Improved Line-Load
Transients Response in a Two-Stage
DC–DC–AC Converter: Adaptive SMC Approach
Aditya R. Gautam, Student Member, IEEE, Kumar Gourav, Josep M. Guerrero
and Deepak Maganlal Fulwani , Member, IEEE
Abstract—A substantial pulsation of the second-order
harmonic current ripple with angular frequency 2ω is re-
flected at the input of a single-phase inverter when loads
are supplied at its output with angular frequency ω. More-
over, this ripple back-propagates and injects into the source
in the absence of a bulky dc-link passive filter, an ac-
tive compensator or a suitable digital controller with a
front-end converter in the two-stage converter. This pa-
per proposes a new adaptive sliding mode control for a
two-stage dc–dc–ac converter to reduce proliferation of
ripple without compromising dynamic performance. The
front-end boost converter in the considered two-stage con-
verter interfaces a battery bank and single-phase inverter
fed loads. The control shapes the output impedance of
the boost converter to reduce the ripple component at
battery input. Second, the proposed controller achieves
good dynamic performance at line and load transients. A
fast voltage recovery with small undershoot/overshoot can
be achieved at transients using the proposed controller.
The proposed technique is validated using a hardware of
the 1-kW two-stage converter.
Index Terms—Adaptive sliding mode control (SMC), dc–
dc–ac converter, improvement in system dynamics, low-
frequency current ripple.
I. INTRODUCTION
INGLE-PHASE pulsewidth modulation (PWM) inverters
S are widely used to feed ac loads using dc source directly or
through some front-end dc–dc converter, e.g., a two-stage dc–
dc–ac converter. In such systems, reflection of the second-order
harmonic current (SHC) ripple at dc input of the inverter is in-
herent and inevitable. For instance, an inverter supplying power
Manuscript received May 9, 2017; revised July 23, 2017; accepted
August 20, 2017. Date of publication September 13, 2017; date of current
version January 5, 2018. This work was supported in part by the Ministry
of New and Renewable Energy under Project S/MNRE/LC/2011007.
(Corresponding author: Deepak M. Fulwani.)
A. R. Gautam and D. M. Fulwani are with the Department of Electrical
Engineering, Indian Institute of Technology Jodhpur, Jodhpur 342037,
India (e-mail: df@iitj.ac.in; pg201381001@iitj.ac.in).
K. Gourav is with Mando Softech India Pvt. Ltd., Gurgaon, Haryana
122002, India (e-mail: kumar.gaurav28@outlook.com).
J. M. Guerrero is with the Department of Energy Technology, Aalborg
University, Aalborg 9220, Denmark (e-mail: joz@et.aau.dk).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2017.2752125
0278-0046 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
, Fellow, IEEE,
to an ac load at 50 Hz/60 Hz reflects a power ripple pulsating
at 100 Hz/120 Hz over the average dc input power. A bulky
electrolytic capacitor is generally used at dc link to bypass and
absorb the ripple. However, low ripple handling capability and
high equivalent series resistance (ESR) of electrolytic capacitor
shorten its life (< 1000 h) [1].
Distributed generators (DGs) (e.g., solar photovoltaic (PV),
fuel cell stack, etc.) and battery storage are generally used in lo-
cal power entities, e.g., microgrids. These DGs require front-end
dc–dc power converters to meet the power or voltage require-
ments of inverter loads. For this, the front-end converter plays
several object-oriented roles, e.g., voltage regulator, maximum
power point tracker (MPPT), and output impedance shaping
tool, etc. However, in the absence of a suitable digital com-
pensator with a front-end converter, an active compensator or
a bulky filter at dc link may cause the injection of detrimen-
tal SHC ripple into the source. This causes several problems,
for instance, a solar PV system accommodated with the maxi-
mum power point tracker may show nuisance tripping of circuit
breakers due to substantial oscillations over MPPT operating
points [2], [3]. Similarly, this ripple forces the operation of the
fuel cell in concentration or the mass-transport region [4], [5].
This causes fuel starvation and stack overheating. The SHC rip-
ple greater than 8% of average current supplied by fuel cell
stack may cause excessive losses in fuel cell [6]. A flickering
effect may occur in LED light [1]. The continuous periodic
short charge and discharge caused by SHC ripple lead to acid
stratification and battery wear [7]. The ripple deteriorates the
electrolyte and electrodes of the battery [8]. This ripple forces
use of overrated sizing of components in the system. Moreover,
substantial power pulsation may induce instability to the whole
system.
Some efforts have been made to address these issues upto
some extent by the community. Incorporation of active com-
pensation circuits like a dc-link ripple port [9], [10] or a bidirec-
tional converter [11] reduce SHC ripple at the source. However,
these techniques again add extra circuitry, cost, and complexity
to the system. Alternatively, a digital control scheme modifies
only the control input at low power end and can be imple-
mented in two-stage converters (without adding extra circuitry)
for the ripple compensation. In such systems, a dual-loop con-
trol scheme is one of the options. In this method, the bandwidths
3126 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 4, APRIL 2018
Fig. 1. SHC ripple: (a) uncompensated and (b) compensated systems.
of inner loop (faster) and outer loop (slower) are separated by
at least half a decade from the ripple frequency [12]. The band-
width of voltage/outer loop is reduced far below the bandwidth
of the current/inner loop. This reduces ripple at the input but
also degrades the system dynamic performance. In [13], Wang
et al. proposed a technique to reduce SHC ripple without re-
duction in bandwidth of a voltage loop by inserting a notch
filter in the voltage loop. However, this adds a large nega-
tive phase shift for the frequencies lower than the frequency
of the ripple, and hence, may introduce instability to the system
[14]. Recently, several techniques based on output impedance
shaping of the front-end converter for ripple reduction have
been proposed, see [15]–[18]. These add virtual impedance
or increase the output impedance of the front-end converter
that resists back-propagation of ripple to the source. In such
cases, the ripple is forced to bypass through an output filter
capacitor.
Only a few techniques, partially, address the problem using
linear controllers. These controllers ensure ripple mitigation but
degrades the dynamics performance, and ensure stability about
the operating points only. Uncertain working characteristics of
DGs and the presence of a substantial ripple in the system may
to lead nuisance tripping of protection circuits. Furthermore, a
large variation in line and load may result into substantial os-
cillations. This may induce instability to the system with the
linear controller. Controller needs to consider ripple mitigation
and system performance together. Therefore, there is a need of
a technique that mitigates the effect of ripple without compro-
mising the dynamic performance and has sufficient robustness
with respect to uncertainty. A sliding mode controller is one
of the established techniques [19]. This paper proposes an out-
put impedance shaping technique of a front-end converter of
the two-stage dc–dc–ac converter for ripple reduction at source
(input) using a robust adaptive sliding mode controller. The
control technique aims to shape the output impedance of the
front-end boost converter in adaptive manner, and hence, re-
sist back-propagation of ripple toward the input. Moreover, the
adaptive nature of the proposed controller improves system dy-
namics at line and load transients. The proposed controller en-
sures fast voltage recovery with small undershoot/overshoot at
load transients. The performance of the proposed controller is
compared with the existing controllers. The proposed controller
is validated using a 1-kW-hardware setup. The rest of this paper
is organized as follows. In Section II, background of the SHC
ripple is discussed. The concept of output impedance shaping
is covered in Section III. The proposed controller and its role
Fig. 2. SHC ripple in (a) single-stage dc–ac converter and (b) two-
stage dc–dc–ac converter.
Fig. 3. Circuit of the two-stage dc–dc–ac converter.
in the output impedance shaping of the front-end converter is
discussed in Section IV. The stability and load transient analysis
are covered in Section V. Sections VI and VII cover simulation
and experimental results, respectively. Section VIII concludes
this paper.
The major contributions of this paper are as follows:
1) a nonlinear adaptive sliding mode controller;
2) SHC ripple reduction at input;
3) improvement in the system dynamics performance;
4) validation of the proposed controller.
II. BACKGROUND OF SHC RIPPLE
The product of fundamental component of sinusoidal output
current (i ac ) and output voltage (vac ) of the inverter results into
the appearance of the second-order harmonic power ripple at
input of the inverter. This power ripple pulsates over the average
input power. For an inverter, the instantaneous output power is
vac i ac = Vm cos (ωt)Im cos (ωt − φ) (1a)
= 0.5Vm Im cos φ + 0.5Vm Im cos (2ωt − φ) (1b)
where Vm and Im are the peak values of instantaneous output
voltage and output current of the inverter, respectively, ω is an-
gular frequency of voltage, and φ is phase difference between
vac and i ac . For an ideal inverter, input dc power is equal to out-
put ac power. The second term in right-hand side (RHS) of (1b)
is SHC ripple power that pulsates over the dc average power
at the input side. In order to comprehend this, Fig. 1 shows
experimental results of a two-stage converter for (a) uncompen-
sated and (b) compensated system. In Fig. 1, x1 is the input
current and x0 is the output current of the front-end converter,
and Vac is the output voltage of the inverter. The frequency
of Vac is 50 Hz. The ripple in x1 [see Fig. 1(a)] and x0 (see
Fig. 1) is of 100 Hz. The ripple in x0 is the second term in RHS
of (1b) that back-propagates to source and pollutes the source
current (x1 ). Fig. 2 shows how ripple is generated and how it
propagates.
GAUTAM et al.: RIPPLE MITIGATION WITH IMPROVED LINE-LOAD TRANSIENTS RESPONSE IN A TWO-STAGE DC–DC–AC CONVERTER 3127

III. CONCEPT OF THE OUTPUT IMPEDANCE SHAPING

A circuit of a two-stage converter is shown in Fig. 3. The
front-end converter is a boost converter that feeds an inverter.
The dynamic model of the boost converter in error coordinates
is as follows:
1
e˙1 = (E − r (e1 + x1r ) − (1 − u)(e2 + x2r )) (2a)
L
1 (e2 + x2r )
e˙2 = ((1 − u)(e1 + x1r ) − ). (2b)
C Z0
The state variables are the inductor current error (e1 )brk and
output capacitor voltage error (e2 ), such that e1 = x1 − x1r and
e2 = x2 − x2r . Here, x1 is the inductor (or input) current and
x1r is its reference value. x2 is the output capacitor voltage
(or bus voltage) and x2r is its reference value. The Z 0 is the
dynamic load impedance at the output of the boost converter. u
is control input and E is input voltage. L is inductance and C
is output capacitance. r and rC are the ESR of the inductor and Fig. 4. Typical profiles of (a) α versus per unit bus output voltage, x2
(p.u.) and (b) output impedance (per unit), Z out (p.u.) versus α.
output capacitor, respectively. The ESR of film capacitor (used
in experimentation) is generally very small. In such case, the
output capacitor voltage can be considered equal to the output A. Proposed Adaptive Switching Function
voltage of the boost converter. The controller is designed using the sliding mode control
It should be noted that increase in the output impedance of (SMC) approach. The SMC is one of the nonlinear and robust
the front-end converter has a significant impact in the reduction control approaches. A switching function and a control law are
of ripple at the dc source side. However, it is not efficient and two important design steps of the SMC. The proposed switching
cost effective to increase the size of passive components in the function is defined by
physical circuit for ripple mitigation. Alternatively, a suitable
design of control input (duty of the front-end converter) can play σ : = e1 + αe2 (4a)
an important role in the ripple reduction. The output impedance β β
α : = γ (x2 − x2r ) = γ e2 . (4b)
of the front-end boost converter seen by the load (as shown in
Fig. 3) depends on the duty cycle of the front-end converter and where α > 0 is a time-varying power function of e2 . γ is a
can be given by [20] positive constant and β is an even positive integer. γ limits the
value of the α, and steers its value monotonically. The parameter
Z out =
ZL
(3) β helps in shaping the profile of α such that α maintains a very
(1 − D)2 small value (say αmin ) within x2r (1 ± R%) (i.e., allowed voltage
variation range (AVVR)] at steady state. Here, the symbol %R
where Z L = (r + s L) is the impedance of inductor and D is
represents percentage output voltage regulation of the front-
the duty. Clearly, Z out is the function of D. A slight change in
end converter. The value of α increases monotonically when
duty can modify the output impedance of the front-end dc–dc
x2 departs from AVVR. In Fig. 4(a), a typical profile of the
converter. A high output impedance resists the ripple injection
α with respect to per unit bus voltage, x2 (p.u.) is shown. The
into the source and forces its flow through bus capacitor as
base voltage for per unit conversion is x2r . For the purpose
shown in Fig. 3 using arrow. However, this substantial amount
of illustration, the profile of α is plotted for base or reference
of SHC ripple, passing through the output capacitor may cause
voltage, x2r = 380 V , γ = 10−10 , ±R% = ±5%, and β = 6.
poor voltage regulation with the insufficient filter capacitance at
We will prove that the output impedance of the front-end con-
dc bus. There is a tradeoff between ripple reduction and voltage
verter is high for very low α values. This is why a small value of
regulation using digital control. Second, in many cases, the tech-
α should be maintained in AVVR. Second, we will also prove
nique employed for ripple reduction may degrade the dynamic
that the value of α should be increased monotonically when
performance of the system. Therefore, an adaptive controller is
bus voltage departs from the AVVR at line or load transients
needed to achieve both the objectives simultaneously.
such that a fast convergence of bus voltage with low under-
shot/overshoot can be achieved. This is the motivation behind
IV. PROPOSED CONTROLLER AND ITS ROLE IN THE OUTPUT the selection of the profile of α as defined by (4b). The range of
IMPEDANCE SHAPING α is depicted in Fig. 4(a). In Fig. 4(b), a typical plot of per unit
The proposed controller and its role in the ripple reduction at output impedance, Z out (p.u.) versus α is shown. Now, the time
input by the output impedance shaping of the front-end dc–dc derivative of the switching function is
converter is investigated in this section. σ̇ = e˙1 + α e˙2 + α̇e2 . (5)
3128 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 4, APRIL 2018

The time derivative of α is βα ee˙22 . Using this in (5), we obtain Now, using (3) and (11), the output impedance of the boost
converter is given by
σ̇ = e˙1 + α(β + 1)e˙2 . (6)
Z out = Z L 0 (1 − δ)2 (13)
We have chosen the reaching dynamics given as follows [19]:
where Z L 0 = (1−DZL
0)
2 and 0 < δ < D0 < 1. The δ is the func-

σ̇ = −σ − Qsgn(σ ) , Q ∈ R − {0}. +

(7) tion of α. The value of δ increases/decreases with the in-
crease/decrease in the value of α for the range given by (12). This
Here, the aforementioned equation ensures the reaching of the implies, Z out increases/decreases with the decrease/increase in
system dynamics on the sliding surface (σ = 0) in finite time, the α. This implies that a high value of Z out can be obtained at
where  is the tuning parameter and Q depends on maximum α ≈ 0. It is noted that α cannot be zero as it contributes to the
value of disturbance. By solving (2), (6), and (7), the duty of the convergence of voltage error [see (4 a)]. This proves the suit-
controller is calculated. ability of the α as shown in Fig. 4(a), that maintains the value of
α nearly zero for the 5%-voltage regulation, i.e., within AVVR.
B. Control Law This concludes that the proposed switching function can achieve
The control input, u, is deduced using (2), (6), and (7) as high Z out in AVVR range, this implies the reduction in ripple at
follows: the input.
 αμ 
− Z 0 (e2 + x2r ) − r (e1 + x1r ) + E V. STABILITY AND TRANSIENT RESPONSE ANALYSIS
u =1−
(e2 + x2r ) − αμ(e1 + x1r ) In this section, stability of the sliding mode and existence of
  sliding mode are established. Thereafter, study on the system
L(σ + Qsgn(σ ))
− (8) dynamics response at line or load transitions is carried out near
(e2 + x2r ) − αμ(e1 + x1r ) to the sliding manifold, σ = 0.
where μ = (β+1)L
C
.
A. Existence of Sliding Mode
C. Output Impedance Shaping of the The existence of sliding mode for the switching function
Front-End Converter given by (4a) can be guaranteed if the η− reachability condition
[21]
During sliding mode σ ≈ 0, then (8) reduces to
σ T σ̇ < −η|σ |, η > 0 (14)
− αμ (e + x2r ) − r (e1 + x1r ) + E
Z0 2
u =1− (9) holds for the reaching dynamics given by (7). To establish the
(e2 + x2r ) − αμ(e1 + x1r )
condition for the existence, we consider the left-hand side (LHS)
where for e1 = e2 = 0, the u is equal to D0 for ideal converter part of the (14) and substituting (7) into it gives
(r = 0). D0 is equal to (1 − xE2r ) and (1 − Zx02rx1r ). However, in
σ T σ̇ = −σ T σ − σ T Qsgn(σ ) (15)
this particular problem, ripple component cannot be neglected
completely. Suppose, sliding mode is stable and steady state is where σ is the scalar quantity, this implies σ T = σ . Also,
reached. During steady-state operation, e1 is equal to ripple in σ sgn(σ ) = |σ |, this gives
input current say, 1 and e2 is equal to output voltage ripple value
say, 2 . At steady state, these ripples pulsate over average values σ T σ̇ = −(|σ | + Q)|σ |. (16)
of current and voltage, respectively. Also, parasitic resistance of Comparing the (14) with (16), we have η ≥ |σ | + Q. This
inductor (r ) is negligible. Considering these in (9) and dividing implies that the existence of sliding mode is guaranteed for all
numerator and denominator by x2r , we have the control input at η > |σ | + Q provided , Q > 0.
steady state (say, D)
  B. Stability of the Sliding Mode
− 1 + x2r2 αμ Z0
+ xE2r
D =1−    . (10) Here, the stability of the sliding mode is proved using the
1 + x2r2 − αμ xx1r2r + x2r1 Lyapunov approach.
Theorem 1: During sliding mode (σ = 0), system dynamics
Here, | x2r2 | << 1 and can be neglected. Also, D0 = (1 − xE2r ) = are stable (i.e., e1 converges to e1 ≈ 0 and e2 converges to e2 ≈
(1 − Zx02rx1r ) < 1. Using these in the aforementioned equation, we 0, if errors satisfy the bounds
have x2r
e1 ∈ [κ¯1 κ¯2 ], e2 ∈ [κ¯3 κ¯4 ], for 0 < α < (17)
D0 − δ μx1r
D≈ (11)
1−δ where κ¯1 = − (1−Dκ20 )κ1 α , κ¯2 = κD20+κ
κ1 α
3
0 κ1
, κ¯3 = − κD2 +κ 3
, and κ¯4 =
where δ = x2r αμ 1
and 0 < D < 1. This implies 0 < δ < D0 .
(1−D0 )κ1
κ2
, where κ1 = C(x2r − μαx1r ), κ2 = Z 0 , and κ3 =
Cμα
−αμx1r
Furthermore, solving this inequality for α gives C(1 + μα 2 ).
Proof: During sliding mode, (σ = 0)
D0 x2r
0<α< . (12) e1 + αe2 = 0, or e1 = −αe2 .
μ(D0 x1r + 1)
(18)
GAUTAM et al.: RIPPLE MITIGATION WITH IMPROVED LINE-LOAD TRANSIENTS RESPONSE IN A TWO-STAGE DC–DC–AC CONVERTER 3129

Using the aforementioned equation, it is obvious that conver-

gence of e2 results into convergence of e1 . Hence, we need to
prove the convergence of e2 only.
Choose a Lyapunov function, V = 12 e22 . Its derivative is

V̇ = e2 ė2 . (19)
Using (2b), (18), and (19), we have
 
e2 1 x2r
V̇ = − 2 (1 − u)α + − e2 − (1 − u)x1r . (20)
C Z0 Z0
Further simplifying (20) using x1r = Z 0 (1−D
x2r
0)
, we have Fig. 5. Locus of eigen values with variations in α.
  
e22 1 x2r 1−u
V̇ = − (1 − u)α + − e2 1− . Alternatively, the analysis of the system stability and sys-
C Z0 Z0 1 − D0
(21) tem transients response is carried out using equivalent dynamic
Here, (1 − u) lies between 0 and 1. The first term in the RHS equations of the closed-loop system about the operating points.
of (21) is negative for 0 < (1 − u) < 1. Second, it should be Using system dynamic equations of (2) and equivalent control
noted that output voltage increases with the decrease in (1 − u) input (for σ = 0) given by (9), the closed-loop dynamics are
for boost converter, and vice versa. The x2r is the output voltage  
αμ (e2 +x
2
of boost converter for u = D0 . This implies (1 − u) < (1 − Z0
2r )
− (e1 + x1r )(E − r (e1 + x1r ))
D0 ) for e2 (i.e.x2 − x2r ) > 0, and (1 − u) > (1 − D0 ) for e2 < e˙1 = (25a)
L((e2 a + x2r ) − αμ(e1 + x1r ))
0. Using these relations in (21), the second term in the RHS
(e2 +x2r )2
of (21) also becomes negative. This implies that V̇ < 0 for (e1 + x1r )(E − r (e1 + x1r )) − Z0
e˙2 = . (25b)
0 < 1 − u < 1. Now, to ensure 0 < (1 − u) < 1 for stability of C((e2 + x2r ) − αμ(e1 + x1r ))
the sliding mode, the condition can be deduced as follows.
Equation (9) can further be simplified in the form of compli- The system dynamic equations of (25) are linearized about
mentary of input signal as the operating points ( 1 , 2 ). 2 can be obtained using (4b) for a
suitable value of α, and 1 can be obtained using (25) for given
(1 − D0 )κ1 − κ2 e2 2 at steady state (by equating e˙1 = 0 or e˙2 = 0). A generalized
1−u = . (22)
κ1 + κ3 e2 Jacobian matrix, (Acj ) about ( 1 j , 2 j ) for some α = α j can be
In (9), the value of r is negligible, and hence, neglected. obtained as follows:
 
In order to satisfy 0 < 1 − u < 1, the range of e2 can be J11 j J12 j
defined using (22) as Acj = .
J21 j J22 j
D 0 κ1 (1 − D0 )κ1
− < e2 < . (23) Suppose the two eigen values of the closed-loop system matrix,
κ2 + κ3 κ2
Acj are λ j+ and λ j− . Now using Acj , an eigen values plot for
Here, κ2 and κ3 are positive terms. In (23), κ1 = C(x2r − μαx1r ) α = 0.001 to α = 0.05, is obtained and shown in Fig. 5. From
is positive for α < μx
x2r
1r
. Also, the range of e1 is obtained using Fig. 5, it can be observed that the system is stable as the all
(18). This implies the system is stable when e1 and e2 respect eigen values are real and negative. Second, for the analysis of
the range given by (17). This completes the proof. system performance, the locus of eigen values (λ j+ , λ j− ) with
variations in α is observed. From Fig. 5, it can be concluded
C. Transient Response Analysis that for high values of α, eigen values are relatively farther from
the imaginary axis and vice versa. This indicates that the system
It is noted that α is the convergence factor of voltage error
convergence is faster for higher values of α.
(e2 ) in (4a). A small value of α makes the voltage error part
less significant. This causes sluggish system dynamics at load
transients. To investigate the effect of α on system dynamics, D. System Robustness Analysis
we consider (21) again. We have already proved that In this section, the robustness analysis, in the presence of
   uncertainty in the system parameters (C, L) is carried out. The
e2 1 x2r 1−u
V̇ = − 2 (1 − u)α + − e2 1− <0 objective of this analysis is to verify whether the sliding mode
C Z0 Z0 1 − D0 σ = 0 is established in spite of this uncertainty. This can be
(24)
done using the reachability condition given by (14). It should
for 0 < α < μx x2r
. Now, using (24), it can be concluded that the
1r be noted that the sliding mode (σ = 0) exists if reachability
increase in the value of α (from 0 to μx x2r
1r
) makes the value of V̇ condition is satisfied. For this, we rewrite the dynamic model of
more negative, hence, system dynamics converge at the faster (2) as follows:
rate. This follows that the undershoot or overshoot dies out at
faster rate and system dynamics improve. ė = M( f + gu). (26)
3130 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 4, APRIL 2018

Here, f, g, and u are the function of e and t, such that

     
e1 f1 E − r (e1 + x1r ) − (e2 + x2r )
e: = , f := =
e2 f2 (e1 + x1r ) − ( e2 +x
Z0
2r
)
     
g (e2 + x2r ) a0 1 1
g:= 1 = , M := ,a = ,b= .
g2 −(e1 + x1r ) 0b L C
Variations in L and C will change a bya and b by b. 
a + a 0
This implies M changes to M + M = .
0 b + b
Considering this in (26), the dynamic model becomes
ė = (M + M)( f + gu). (27)
Now, using (26), (8) becomes
Fig. 6. Schematic of the proposed control scheme.
u = −(N Mg)−1 (σ + Qsgn(σ ) + N M f ) (28)
TABLE I
where N is the row vector, i.e., N = [1 (β + 1)α]. It is to be SYSTEM PARAMETERS
noted that controller is derived based on the nominal model of
the system. It is to be established that this controller brings slid- Parameter Value
ing mode in finite time even with uncertainty in the parameters. (A) Boost Converter
Now, using (6) and (27) Rating of lead acid battery 110 V, 26 A·h
Nominal dc bus voltage 350 V
σ̇ = N (M + M)( f + gu). (29) Inductance (L), (r ) 150 μH; 25 m
Output or bus capacitor (C) 1.9 mF
The robustness of the system against the variation in the system Switching frequency ( f s ) 25 kHz
parameters (L , C) is ensured if reachability condition given by (B) Single-Phase PWM Inverter
(14) is satisfied. Using LHS of (14), (28), and (29) Output voltage (Vac ) 220 V, 50 Hz
Modulation index, (MI) 0.88
σ T σ̇ = −σ T ((σ + Qsgn(σ ))y − x). (30) Switching frequency ( f sinv ) 5 kHz
−1
Here, x = N M f − N Mg(N M G) N M f and y =
1 + N Mg(N Mg)−1 . σ is the scalar quantity. Therefore,
σ T = σ . Also, σ sgn(σ ) = |σ |. Using this in (30) yields VI. SIMULATION RESULTS

x The simulation results are obtained using the parameters
σ σ̇ = − (|σ | + Q)y − |σ | (31a) given in Table I for a 2.5-kW-two-stage converter. A lead-acid
sgn(σ )

battery available under SimPowersystems library of simulink
σ σ̇ = −η |σ |. (31b) is used as the source in the simulation [22]. The profile of

Here, η = ((|σ | + Q)y − sgn(σx
). α chosen is similar as in Fig. 4(a). The design parameters
are:  = 3200, Q = 10, γ = 3 ∗ 10−6 , and β = 4. Two differ-
)
The reachability condition given by (14) satisfies, provided

that η > 0. Suppose x
y
= ρmax . ρmax is the maximum tolerable ent cases are shown in simulation results: 1) Case I—Impact
 of the variation in α on ripple reduction; and 2) Case II—Load
parametric uncertainty in the system. Using (31), for η > 0, the
transients test for the analysis of the system dynamics perfor-
following condition must be fulfilled:
mance.
|ρmax | < ||σ | + Q|. (32)
Here, |sgn(σ )| = 1. By design Q > ρmax such that this respects A. Test Case-I: Ripple Reduction Test (Impact of α
on Ripple)
the condition given by (32).
From the aforementioned discussion, it is clear that the ripple The bus/output voltage (x2 ), input/battery voltage (E), in-
reduction is possible by reducing the value of α. On the other put/battery current (x1 ), and bus/output current (x0 ) of the boost
hand, at line or load transients, the sluggish system dynamics converter are shown in Fig. 7. This figure shows results for three
can be improved by increasing the value of α. The proposed different values of α = 0.9, 0.5, 0.001. The ripple in input cur-
adaptive surface ensures ripple mitigation and improvement in rent decreases with the decrease in α. For α = 0.9, the peak
transients performance by modulating the parameter α. This is to peak ripple (9 A) in a battery current with respect to its av-
why the profile of α is chosen as plotted in Fig. 4(a). This makes erage value (23 A) is 39%. This reduces to 1.5% (approx) for
the switching function nonlinear and adaptive. α = 0.001. This verifies the theory presented in Section IV.
The schematic of the proposed control scheme is shown in For the comparison of load test results of the proposed con-
Fig. 6. It is to be noted that the inverter is a load. Therefore, the troller, the proportional-integral (PI) controllers for ripple miti-
design of controller for the inverter is not our main objective. gation are designed using the design guidelines of [12]. First, to
This is why an open-loop sinusoidal PWM controller (fixed design PI controllers, the poles and zeros are placed according to
modulation and fixed frequency) is used for the inverter. Table II. Second, the gain of PI controllers is chosen accordingly
GAUTAM et al.: RIPPLE MITIGATION WITH IMPROVED LINE-LOAD TRANSIENTS RESPONSE IN A TWO-STAGE DC–DC–AC CONVERTER 3131

Fig. 7. Simulation results of Test Case-I for α = 0.9, 0.5, and 0.001.

TABLE II
PI CONTROLLER DESIGN FOR 100-HZ RIPPLE COMPENSATION [12]

Parameter Design Requirements

(1) Inner and outer compensator
design criterion
(2) Bandwidth of outer loop
(3) Bandwidth of inner loop
Parameter
Gain of inner compensator
Gain of outer compensator
poles at origin and at half of the
switching frequency ( f s /2), zero at
or below resonance frequency Fig. 9. Simulation results for Test Case-II.
5 Hz
550 Hz
Designed Gain inner loop and open-loop gains without controller (G o ) and
0.13999 with controller (To ) for the outer loop are shown in Fig. 8(b). f oi
5.2899 and f ov are cutoff frequencies of Ti and To , respectively. Clearly,
as suggested in [12], the cutoff frequencies of To and Ti are sep-
arated by more than half a decade from ripple frequency (2ω).
ω is the angular frequency of the output voltage of the inverter.
In Fig. 8(b), the bandwidth of Ti is > 10ω and bandwidth of
To is far below the ripple frequency, i.e., < 2ω 5
. The purpose of
reduction of the voltage loop bandwidth is to increase the output
impedance of the front-end converter, and hence, reduction in
the SHC ripple at input [14], [20]. However, this results to poor
system dynamics.

B. Test Case-II: Load Transient Response Test

Fig. 8. (a) Schematic of dual-loop control. (b) Bode plot.
to obtain the desired bandwidths of inner loop and outer loop.
The designed controller gains are given in Table II. In Fig. 8(a),
the block diagram of the dual-loop control scheme for the boost
converter, is shown. x˜1 , x˜2 , d̃, x˜o , x˜1r , and x˜2r are the variables
in small-signal sense. Ci and Cv are PI controllers. Hi and Hv
are the sensor gains. G vd and G id are the transfer functions
of control-to-output voltage and control-to-inductor current, re-
spectively. Fpwm is PWM gain. The Bode plots of open-loop
gains without controller (G i ) and with controller (Ti ) for the
The simulations results for the PI controller and the proposed
controller are shown in Fig. 9. For load test, load application
transients and load removal transients are captured and dis-
cussed here.
1) System Response at Load Removal: At t = 4 s, the
2-kW-inverter load is removed suddenly. PI controller shows
a bus voltage overshoot of 18.5%. The output voltage settles
down in 700 ms at reference voltage (350 V). The 0.5-kW-
inverter load is kept connected. At no-load condition, the system
shows very large undershoot/overshoot and sluggish response
with the PI controller. On the other hand, complete 2.5-kW
inverter load is removed suddenly for the proposed controller
case. The proposed controller shows an overshoot of 4% only
in bus voltage, and settles down there within < 10 ms.
3132 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 4, APRIL 2018

TABLE III
COMPARISON OF SIMULATION RESULTS

Parameter Dual-Loop PI Controller Nonlinear Compensator [20] Proposed Controller

% Peak to Peak ripple in input current 3.5 % 1.8 % 1.5 % (approx)

Input filter capacitor 220 μF 220 μF 220 μF
Bus filter capacitor 1.9 mF 1.9 mF 1.9 mF
Input voltage 110 V 110 V 110 V
Bus voltage 350 V 350 V 350 V
Inverter load Transients 0.5–2.5 kW 0–2.5 kW 0–2.5 kW
Bus voltage overshoot/undershoot +18.5 %/−17% +4.5 %/−4.5% +4 %/−2 %
Voltage recovery time at load removal 700 ms maintains voltage regulation < 5% maintains voltage regulation < 5%
Voltage recovery time at load application 300 ms 200 ms 20 ms

Fig. 10. Experimental setup.

2) System Response at Load Application: At t = 8 s,

the load is applied. The bus voltage shows undershoot of 17%
for the PI controller and only 2% for the proposed controller, Fig. 11. Experimental results of Test Case-I using the proposed
respectively. The bus voltage tracks reference in 300 ms for PI controller.
and in 20 ms for the proposed controller. For the PI controller,
the peak-to-peak SHC ripple in battery current is 3.5 % that is
more than as in case of the proposed controller (shown at t = 1 s
in Fig. 9). Other plots for both cases are also shown.
Additionally, the comparison is also done with a nonlinear
compensator presented in [20]. The simulation results of the
PI, nonlinear compensator of [20], and proposed controller are
summarized in the Table III. Comparing all together, it can be
concluded that the proposed controller performs better. Second,
the conventional method, e.g., passive compensation requires a Fig. 12. FFT diagram for the compensated system: (a) x1 , (b) x0 , and
(c) Vac .
bulky capacitor (30 mF) at output of the boost converter [20].
However, with the proposed technique, only a 1.9 mF-capacitor
at the output of the boost converter is required. α is designed for Cases: (I) SHC ripple reduction test, (II) Load transients test,
5% bus voltage regulation. This is why there is a steady-state and (III) Line or input voltage variation test. The experimental
error in bus voltage, which is < 5% of x2r . results are shown for battery as input source in Figs. 11–15.
An additional result is also shown using Solar PV (with rated
VII. EXPERIMENTAL RESULTS voltage = 160 V) as input in Fig. 16 for Case-II.
In this section, the proposed controller is validated using a
1-kW-lab prototype of the two-stage dc–dc–ac converter. The A. Test Case-I: SHC Ripple Reduction Test
experimental setup is shown in Fig. 10. In Fig. 10, a boost con- For Test Case-I, the experimental results are shown in Fig. 11
verter, a single-phase PWM inverter, current and voltage sen- (similar as in Fig. 7). Here, also, the value of α is varied, i.e.,
sors, battery bank, and control platform (Real Time Digital Sim- α = 0.9, 0.5, and 0.001. The peak-to-peak SHC ripple in the
ulator) are shown. The experimental parameters are as follows battery/input current reduces with the decrease in α. The ripple
E = 120 V, x2r = 380 V, C = 1 mF, L = 2 mH, Q = 10, and in the input current is negligible (< 1%) for α = 0.001. The
 = 2000. The profile of the α is chosen as shown in Fig. 4(a). experimental result for decrease in the ripple at input with de-
The designed parameters for α are: β = 6 and γ = 10−10 . crease in α validates the theory presented in Section IV. The
Here, the experimental results are shown for three different test input voltage, output voltage, and output current are also shown
GAUTAM et al.: RIPPLE MITIGATION WITH IMPROVED LINE-LOAD TRANSIENTS RESPONSE IN A TWO-STAGE DC–DC–AC CONVERTER
Fig. 13. Experimental results of Test Case-II using the proposed
controller.
Fig. 14. Experimental results of Test Case-II for load variation from 0.6
to 1 kW and vice versa.
Fig. 15. Experimental results of Test Case-III: Variation in input voltage.
Fig. 16. Experimental results for Test Case-II with solar PV as source.
3133
in Fig. 11. In Fig. 12, fast Fourier transform (FFT) diagram for
the compensated system with the proposed controller is shown.
Fig. 12(a) shows that there is negligible component of 100 Hz
in input current x1 . In Fig. 12(b), the output current (x0 ) of the
boost converter contains the 100-Hz ripple component, which is
obvious. Fig. 12(c) shows the FFT diagram of the output voltage
of the inverter.
B. Test Case-II: Load Transients Test
The experimental load transients results for no load to 1-kW-
inverter load and 0.6-kW to 1-kW-inverter load are shown in
Figs. 13 and 14, respectively.
In Fig. 13, the battery current (x1 ) and output voltage (x2 )
of the boost converter, and output current (Iac ) and output
voltage (Vac ) of the inverter are shown. The experimental re-
sults are discussed here for sudden load removal and load
application.
1) Load Application Test: A 1-kW-inverter load is applied
suddenly at the output of the boost converter. The bus voltage
shows an undershoot of 8% (approx). It takes 50 ms to regain
the normal operation within AVVR. The input current of the
battery and the output current and output voltage of the inverter
are also shown. The battery current and output current of the
inverter show overshoots at load application but settle within
80 ms without oscillations. There is a small change in inverter
output voltage.
2) Load Removal Test: At the removal of the complete in-
verter load, the bus voltage shows an overshoot of 3% (approx),
and settles at 375 V in 160 ms without showing any oscillations.
The output voltage of the inverter shows small rise. Nonetheless,
the battery current and inverter output current shows negligible
oscillations at load removal.
In Fig. 14, similar results as in Case-II, are shown for inter-
mediate load variation from 0.6 to 1 kW and vice versa. The
bus voltage shows negligible overshoot at load removal and an
undershoot of < 5% at application of load.
C. Test Case-III: Variation in Input Voltage (E)
The experimental results of Test Case-III are shown in Fig. 15.
The input power supply is switched-OFF suddenly and
switched-ON again. No oscillations in the bus voltage are ob-
served at the switching-OFF the input power. Also, at the reap-
plication of input source, the voltage rises to reference voltage
within 80 ms without any oscillations. The experimental results
(shown in Figs. 11–15) are summarized in Table IV.
Additionally, the experimental results for Test Case-II are
shown for solar PV as input source in Fig. 16. As the input volt-
age is not regulated one, bus voltage shows a larger undershoot
of 16% (approx.) at load application and an overshoot of 3%
(approx.) at load removal in Fig. 16. However, the bus voltage
is recovered in 320 ms (at load application) and 160 ms (at load
removal), respectively. This concludes that the experimental re-
sults validates the effectiveness of the proposed controller in
ripple reduction and system dynamics performance. The pro-
posed controller is robust against the line and load transients.
3134 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 4, APRIL 2018

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GAUTAM et al.: RIPPLE MITIGATION WITH IMPROVED LINE-LOAD TRANSIENTS RESPONSE IN A TWO-STAGE DC–DC–AC CONVERTER 3135

Josep M. Guerrero (S’01–M’04–SM’08–F’15) Deepak Maganlal Fulwani (S’09–M’10) re-

received the B.S. degree in telecommunica- ceived the Ph.D. degree in systems and control
tions engineering, the M.S. degree in electron- from Indian Institute of Technology (IIT) Bombay,
ics engineering, and the Ph.D. degree in power Mumbai, India, in 2009.
electronics from the Technical University of He is currently working as an Assistant Pro-
Catalonia, Barcelona, Spain, in 1997, 2000, and fessor with the Department of Electrical Engi-
2003, respectively. neering, IIT Jodhpur, Jodhpur, India. He also
Since 2011, he has been a Full Profes- worked at IIT Guwahati and IIT Kharagpur. His
sor with the Department of Energy Technology, research interests include control of networked
Aalborg University, Aalborg, Denmark, where he systems and dc microgrid.
is responsible for the Microgrid Research Pro-
gram (www.microgrids.et.aau.dk). Since 2012, he has been a Guest
Professor with the Chinese Academy of Science, Beijing, China and
the Nanjing University of Aeronautics and Astronautics, Nanjing, China;
since 2014, he is a Chair Professor with Shandong University, Jinan,
China; from 2015, he has been a distinguished guest Professor with
Hunan University, Changsha, China; and since 2016, he has been a
Visiting Professor Fellow with Aston University, Birmingham, U.K., and
a Guest Professor with the Nanjing University of Posts and Telecom-
munications. His research interests include different microgrid aspects,
including power electronics, distributed energy-storage systems, hier-
archical and cooperative control, energy management systems, smart
metering and the internet of things for ac/dc microgrid clusters and is-
landed minigrids; recently especially focused on maritime microgrids for
electrical ships, vessels, ferries, and seaports.
Prof. Guerrero is an Associate Editor for the IEEE TRANSACTIONS ON
POWER ELECTRONICS, the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRON-
ICS, and the IEEE INDUSTRIAL ELECTRONICS MAGAZINE, and an Editor
for the IEEE TRANSACTIONS ON SMART GRID and the IEEE TRANSAC-
TIONS ON ENERGY CONVERSION. He has been Guest Editor of the IEEE
TRANSACTIONS ON POWER ELECTRONICS Special Issues: Power Electron-
ics for Wind Energy Conversion and Power Electronics for Microgrids;
the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Special Sections:
Uninterruptible Power Supplies systems, Renewable Energy Systems,
Distributed Generation and Microgrids, and Industrial Applications and
Implementation Issues of the Kalman Filter; the IEEE TRANSACTIONS ON
SMART GRID Special Issues: Smart DC Distribution Systems and Power
Quality in Smart Grids; theIEEE TRANSACTIONS ON ENERGY CONVERSION
Special Issue on Energy Conversion in Next-generation Electric Ships.
He was the Chair of the Renewable Energy Systems Technical Com-
mittee of the IEEE Industrial Electronics Society. He received the best
paper award of the IEEE TRANSACTIONS ON ENERGY CONVERSION for the
period 2014–2015, and the best paper prize of IEEE Power and Energy
Society in 2015. As well, he received the best paper award of the Journal
of Power Electronics in 2016. In 2014, 2015, and 2016, he was awarded
by Thomson Reuters as Highly Cited Researcher, and in 2015, he was
elevated as IEEE Fellow for his contributions on “distributed power sys-
tems and microgrids.”