REVISION FOR COMPUTER SYSTEMS TEST

SERIAL AND PARALLEL BUSES Serial buses

-send a single bit at a time
-higher frequency
-few traces required

Parallel buses
-sends multiple bits at a time
-lower frequency
-more traces required

Parallel bus problems

-clock skew
-signals arrive at different times
-less tolerance at higher frequency’s

-crosstalk
-adjacent signals can interfere with each
other
-density issues

Examples of serial buses

PCI-express
RISC AND CISC RISC: Reduced Instruction Set Computer
CISC: Complex Instruction Set Computer

CISC
dominant architecture in the PC market
belongs to CISC

supports the operations and data structures

used by Higher-Level Languages

complex instructions that do multiple things at

once
harder to decode an implement
instructions can take many cycles
small number of registers
typically 7 clocks per instruction

RISC
Executes all instructions in a single cycle
Hardcoded logic
Many lines of assembly code
Register to register

INSTRUCTION PIPELINING CPU Pipeline is the low-level set of steps which

the CPU carries out in order to execute an
instruction

CPU TIMESHARING AND MULTITASKING
Go over tutorial questions
PRINCIPLE OF LOCALTIY
DIRECT MEMORY ACCESS (BUSES AND
DEVICES)
RISC pipeline comprises:
1. Instruction fetch
2. Instruction decode and register fetch
3. Execute
4. Memory access
5. Register write back
server OS is intended to provide services to
other computers and isn’t for use by users.
A desktop OS is intended to be used by a
human and therefore priorities the user
experience.
kernel is configured. Scheduling on a desktop
system will focus on making the user
experience smooth and fast,
servers focus more on responding to external
requests for web pages or disk resources.
Servers are also intended to be running 24/7,
which is not a typical requirement of a desktop
OS.
Memory accesses are likely to clustered
Instructions tend to be ordered, or in small
loops
Data is also likely to be local
If a page has just been swapped into memory
to satisfy a memory request, subsequent
accesses are likely to be near by
data needs to be transferred from I/O to
memory or even between memory Chips
DMA (Direct Memory Access)  Removes the
responsibility of petty data transfers from the
processor
the processor releases use of the buses to the
DMA Controller (DMAC)
This chip manages requested data transfers
It has a Control Unit and a few registers but no
ability to do calculations
It needs access to the buses so it can its job
Needs ability to HOLD, HOLDA and DREQ and
 send DACK

DERQ1
HOLD
HOLDA
DACK
Takes control of the buses
Begins transfer
Complete transfer = HOLD goes down/
removed
INPUT AND OUTPUT DEVICES I/O Chipset is an interface between the CPU
and input/output devices

use registers to hold data that is being worked

on

The processor considers the I/O chip as

addressable in the same way as memory

The I/O chip then handles communication with

the actual hardware device (like a broker)
Convert signals so the CPU can work with them

-Audio (Microphone, Speaker)

-PCI-E (network card / graphics / SSD)
-Bluetooth (Headsets, Sensors)
SWAPS “Swapping” is the exchange of data to and from
disk

The OS determines the swapping strategy But it

needs support from the processor

it extends memory to the disk Allowing loading

applications bigger than memory

Some early systems swapped whole processes

to and from disk

This gives poor performance due to the large

size of typical processes, and is not widely used
at present

swap location on disk:

 Windows – pagefile.sys
 Linux – dedicated swap partition

If a page has just been swapped into memory

to satisfy a memory request, subsequent
accesses are likely to be near by

Not swappable, fixed priority, scheduled ahead

 others, For critical parts like The Kernel

Swappable, dynamically variable priorities, For

non-critical bits of the OS
VIRTAUL MEMORY Virtual Memory systems are slower than pure
RAM

Generally, most suitable for reasonably large

systems

Processor (Memory management unit) requests

data from RAM

If data was in RAM it will be fetched

If data is not in RAM, its then requested from

the disk

Data will then be moved from disk to RAM

Fetches memory from RAM

ASSESMBLY HALT The HALT instruction causes the program to

terminate.

What would happen if we did not include a

HALT statement at the end of our program?

without HALT the CPU would not know when to

stop!

Without HALT the CPU would continue the

fetch-execute cycle, even if there are no
instructions left to execute. It would then start
treating data stored in DAT directives as
instructions, which would likely be invalid
instructions.

BUFFER OVERFLOW Getting user input requires some space to store

the values

Expect data of a certain length such as

providing a maximum limit

User can provide data longer than this, which

gets stored in memory in places it shouldn’t go!

“overflow” the buffer we were given to store

out text
HARDWARE ATTACK CPUs often execute instructions out of order for
efficiency

Speculative execution -> Do both options of an

branch (if)

MMU doesn’t check for permission to access

memory

When it finds out which path to take, the CPU

hits “undo” on the changes the wrong branch
made

Doesn’t undo changes to cache!

Items in the cache respond faster than memory

Can time the difference to see if data was

cached based on our unauthorised instructions
which were discarded