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FinFET Devices for VLSI
Circuits and Systems
FinFET Devices for VLSI
Circuits and Systems

Samar K. Saha
First edition published 2021
by CRC Press
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ISBN: 9781138586093 (hbk)

ISBN: 9780429504839 (ebk)

Typeset in Times
by Deanta Global Publishing Services, Chennai, India
 In loving memory of my parents
Mahamaya and Phani Bhusan Saha
Contents
Preface...................................................................................................................... xv
Author .....................................................................................................................xix

Chapter 1 Introduction ..........................................................................................1

1.1 Fin Field-Effect Transistors.......................................................1
1.2 Overview of MOSFET Devices for Integrated Circuit
Manufacturing ...........................................................................1
1.2.1 Challenges of MOSFET Scaling at the
Nanometer Node...........................................................4
1.2.1.1 Leakage Current in Short Channel
MOSFETs ..................................................... 4
1.2.1.2 Variability in MOSFETs............................... 6
1.2.2 Physics of MOSFET Scaling Challenges .....................7
1.3 Alternative Device Concepts..................................................... 8
1.3.1 Undoped or Lightly Doped Channel MOSFETs ..........9
1.3.1.1 Deeply Depleted Channel MOSFETs...........9
1.3.1.2 Buried-Halo MOSFETs .............................. 10
1.3.2 Thin-Body Field-Effect Transistors ........................... 11
1.3.2.1 Single-Gate Ultrathin-Body Field-
Effect Transistors........................................ 11
1.3.2.2 Multiple-Gate Field-Effect Transistors....... 12
1.4 FinFET Devices for VLSI Circuits and Systems .................... 13
1.5 A Brief History of FinFET Devices ........................................ 15
1.6 Summary ................................................................................. 18
References .......................................................................................... 19

Chapter 2 Fundamentals of Semiconductor Physics...........................................25

2.1 Introduction .............................................................................25
2.2 Semiconductor Physics ............................................................25
2.2.1 Energy Band Model....................................................26
2.2.2 Carrier Statistics......................................................... 27
2.2.3 Intrinsic Semiconductors............................................ 29
2.2.3.1 Intrinsic Carrier Concentration .................. 29
2.2.3.2 Effective Mass of Electrons and Holes....... 31
2.2.4 Extrinsic Semiconductors........................................... 31
2.2.4.1 Fermi Level in Extrinsic Semiconductor.... 33
2.2.4.2 Fermi Level in Degenerately Doped
Semiconductor ............................................ 35
2.2.4.3 Electrostatic Potential in Semiconductor
and Carrier Concentration............................ 36
2.2.4.4 Quasi-Fermi Level ...................................... 38
vii
viii Contents

2.2.5 Carrier Transport in Semiconductors......................... 39

2.2.5.1 Drift of Carriers: Carrier Motion in
Electric Field............................................... 39
2.2.5.2 Diffusion of Carriers ..................................44
2.2.6 Generation-Recombination of Carrier ....................... 47
2.2.6.1 Injection Level ............................................ 48
2.2.6.2 Recombination Processes ........................... 48
2.2.7 Basic Semiconductor Equations................................. 51
2.2.7.1 Poisson’s Equation ...................................... 51
2.2.7.2 Transport Equations.................................... 53
2.2.7.3 Continuity Equations .................................. 53
2.3 Theory of n-Type and p-Type Semiconductors in Contact...... 55
2.3.1 Basic Features of pn-Junctions................................... 55
2.3.2 Built-Iin Potential....................................................... 57
2.3.3 Step Junctions............................................................. 58
2.3.3.1 Electrostatics............................................... 58
2.3.4 pn-Junctions under External Bias............................... 62
2.3.4.1 One-Sided Step Junction............................. 63
2.3.5 Carrier Transport Across pn-Junctions ...................... 65
2.3.5.1 Relationship between Minority Carrier
Density and Junction Potential ................... 65
2.3.6 pn-Junctions I – V Characteristics.............................. 69
2.3.6.1 Temperature Dependence of
pn-Junction Leakage Current ..................... 71
2.3.6.2 Limitations of pn-Junction Current
Equation...................................................... 72
2.3.6.3 Bulk Resistance .......................................... 74
2.3.6.4 Junction Breakdown Voltage ...................... 75
2.3.7 pn-Junction Dynamic Behavior.................................. 76
2.3.7.1 Junction Capacitance .................................. 77
2.3.7.2 Diffusion Capacitance ................................ 79
2.3.7.3 Small-Signal Conductance .........................80
2.3.8 pn-Junction Equivalent Circuit...................................80
2.4 Summary ................................................................................. 81
References .......................................................................................... 82

Chapter 3 Multiple-Gate Metal-Oxide-Semiconductor (MOS) System ............. 85

3.1 Introduction ............................................................................. 85
3.2 Multigate MOS Capacitors at Equilibrium ............................. 85
3.2.1 Properties of Isolated Metal, Oxide, and
Semiconductor Materials ........................................... 87
3.2.1.1 Workfunction .............................................. 88
3.2.2 Metal, Oxide, and Semiconductor Materials in
Contact Forming MOS Systems.................................90
Contents ix

3.2.2.1 MOS Systems with MG Workfunction

at Silicon Band-Edges.................................90
3.2.2.2 MOS Systems with Silicon-Midgap
MG Workfunction.......................................92
3.2.3 Oxide Charges............................................................94
3.2.3.1 Interface Trapped Charge ........................... 95
3.2.3.2 Fixed Oxide Charge.................................... 95
3.2.3.3 Oxide Trapped Charge................................ 95
3.2.3.4 Mobile Ionic Charge ...................................96
3.2.4 Effect of Oxide Charges on Energy Band
Structure: Flat Band Voltage ......................................96
3.2.5 Surface Potential ........................................................97
3.3 MOS Capacitor Under Applied Bias .......................................99
3.3.1 Accumulation ........................................................... 101
3.3.2 Depletion .................................................................. 102
3.3.3 Inversion ................................................................... 103
3.4 Multigate MOS Capacitor Systems: Mathematical Analysis .... 104
3.4.1 Poisson’s Equation.................................................... 105
3.4.2 Electrostatic Potentials and Charge Distribution ..... 108
3.4.2.1 Induced Charge in Semiconductor ........... 108
3.4.2.2 Formulation of Surface Potential.............. 112
3.4.2.3 Threshold Voltage..................................... 118
3.4.2.4 Surface Potential Function........................ 122
3.4.2.5 Unified Expression for Inversion
Charge Density ......................................... 125
3.5 Quantum Mechanical Effect ................................................. 128
3.6 Summary ............................................................................... 130
References ........................................................................................ 130

Chapter 4 Overview of FinFET Device Technology ........................................ 133

4.1 Introduction ........................................................................... 133
4.2 FinFET Manufacturing Technology...................................... 134
4.3 Bulk-FinFET Fabrication ...................................................... 135
4.3.1 Starting Material ...................................................... 136
4.3.2 Well Formation......................................................... 136
4.3.2.1 p-Well Formation ...................................... 136
4.3.2.2 n-Well Formation...................................... 136
4.3.3 Fin Patterning: Spacer Etch Technique.................... 136
4.3.3.1 Mandrel Patterning ................................... 137
4.3.3.2 Oxide Spacer Formation........................... 138
4.3.3.3 Silicon Fin Formation ............................... 138
4.3.4 Alternative Well Formation Process ........................ 139
4.3.5 Gate Definition: Polysilicon Dummy Gate
Formation ................................................................. 139
x Contents

4.3.6 Source-Drain Extensions Processing ....................... 140

4.3.6.1 nFinFET Source-Drain Extension
Formation.................................................. 140
4.3.6.2 pFinFET Source-Drain Extension
Formation.................................................. 140
4.3.7 Raised Source-Drain Processing ............................. 141
4.3.7.1 SiGe pFinFET Raised Source-Drain
Formation.................................................. 141
4.3.7.2 SiC nFinFET Raised Source-Drain
Formation.................................................. 142
4.3.7.3 Raised Source-Drain Silicidation ............. 142
4.3.8 Replacement Metal Gate Formation ........................ 143
4.3.8.1 Polysilicon Dummy Gate Removal .......... 143
4.3.8.2 High-k Gate Dielectric Deposition ........... 144
4.3.8.3 Metal Gate Formation............................... 144
4.3.9 Self-Aligned Contact Formation .............................. 144
4.3.9.1 Metallization............................................. 145
4.4 SOI-FinFET Process Flow .................................................... 146
4.4.1 Starting Material ...................................................... 146
4.4.2 Fin Patterning: Spacer Etch Technique.................... 146
4.4.2.1 Mandrel Patterning ................................... 146
4.4.2.2 Oxide Spacer Formation........................... 146
4.4.2.3 Silicon Fin Formation ............................... 147
4.4.3 Comparison of Bulk-Silicon FinFET and
SOI-FinFET Fabrication Technology....................... 147
4.5 Summary ............................................................................... 148
References ........................................................................................ 148

Chapter 5 Large Geometry FinFET Device Operation .................................... 151

5.1 Introduction ........................................................................... 151
5.2 Basic Features of FinFET Devices........................................ 152
5.3 FinFET Device Operation ..................................................... 155
5.4 Drain Current Formulation.................................................... 156
5.4.1 Derivation of Electrostatic Potential ........................ 161
5.4.2 Continuous Drain Current Equation for
Symmetric DG-FinFETs .......................................... 168
5.4.3 Regional Drain Current Formulation for
Symmetric DG-FinFETs .......................................... 172
5.4.3.1 Threshold Voltage Formulation ................ 172
5.4.3.2 Linear Region Ids Equation ....................... 173
5.4.3.3 Saturation Region Ids Equation ................. 175
5.4.3.4 Subthreshold Conduction.......................... 176
5.5 Summary ............................................................................... 180
References ........................................................................................ 180
Contents xi

Chapter 6 Small Geometry FinFETs: Physical Effects on Device

Performance ..................................................................................... 183
6.1 Introduction ........................................................................... 183
6.2 Short-Channel Effects on Threshold Voltage........................ 183
6.2.1 Formulation of Natural Length ................................ 184
6.2.2 Channel Potential ..................................................... 190
6.2.3 Threshold Voltage Roll-Off...................................... 192
6.2.4 DIBL Effect on Threshold Voltage .......................... 192
6.3 Quantum Mechanical Effects................................................ 192
6.3.1 Volume Inversion...................................................... 193
6.3.2 QM Effect on Mobility............................................. 195
6.3.3 QM Effect on Threshold Voltage ............................. 195
6.3.4 QM Effect on Drain Current .................................... 198
6.4 Surface Mobility.................................................................... 199
6.5 High Field Effects..................................................................204
6.5.1 Velocity Saturation ...................................................204
6.5.2 Channel Length Modulation ....................................207
6.6 Output Resistance..................................................................209
6.7 Summary ............................................................................... 211
References ........................................................................................ 211

Chapter 7 Leakage Currents in FinFETs .......................................................... 215

7.1 Introduction ........................................................................... 215
7.2 Subthreshold Leakage Currents ............................................ 215
7.3 Gate-Induced Drain and Source Leakage Currents .............. 217
7.3.1 Formulation of Gate-Induced Drain Leakage
Current ..................................................................... 218
7.3.2 Formulation of Gate-Induced Source Leakage
Current ..................................................................... 221
7.4 Impact Ionization Current ..................................................... 221
7.5 Source-Drain pn-Junction Leakage Current ......................... 226
7.6 Gate Oxide Tunneling Leakage Currents.............................. 226
7.7 Summary ............................................................................... 227
References ........................................................................................ 228

Chapter 8 Parasitic Elements in FinFETs ......................................................... 231

8.1 Introduction ........................................................................... 231
8.2 Source-Drain Parasitic Resistance ........................................ 232
8.2.1 Raised Source-Drain FinFET Structure .................. 232
8.2.2 Components of Source-Drain Series Resistance...... 234
8.2.2.1 Contact Resistance.................................... 235
8.2.2.2 Spreading Resistance................................ 237
8.2.2.3 Source-Drain Extension Resistance .........240
xii Contents

8.3 Gate Resistance .....................................................................246

8.4 Parasitic Capacitance Elements.............................................248
8.4.1 Gate Overlap Capacitance........................................248
8.4.2 Fringe Capacitance................................................... 249
8.4.2.1 Fin-to-Gate Fringe Capacitance ............... 250
8.4.2.2 Gate-to-Contact Fringe Capacitance ........ 250
8.5 Source-Drain pn-Junction Capacitance................................. 251
8.5.1 Reverse-Bias Capacitance ........................................ 252
8.5.2 Forward Bias Capacitance........................................ 254
8.6 Summary ............................................................................... 255
References ........................................................................................ 255

Chapter 9 Challenges to FinFET Process and Device Technology ................. 257

9.1 Introduction ........................................................................... 257
9.2 Process Technology Challenges ............................................ 257
9.2.1 Lithography Challenges ........................................... 257
9.2.1.1 ArF Lithography with Multi-Patterning...... 258
9.2.1.2 Extreme Ultraviolet Lithography.............. 258
9.2.2 Process Integration Challenges ................................ 259
9.2.2.1 Precise and Uniform Fin Patterning......... 259
9.2.2.2 Gate and Spacer Patterning ...................... 259
9.2.2.3 Uniform Junction Formation in Fin..........260
9.2.2.4 Stress Engineering ....................................260
9.2.2.5 High-k Dielectric and Metal Gate ............ 261
9.2.2.6 Variability Control.................................... 262
9.2.2.7 Spatial Challenges .................................... 262
9.2.3 Dopant Implantation Challenges.............................. 263
9.2.3.1 Conformal Doping.................................... 263
9.2.3.2 Damage Control........................................ 263
9.2.4 The Etching Challenges ...........................................264
9.2.4.1 Depth Loading Control of Fin Etching.....264
9.2.4.2 Gate Etch Control .....................................264
9.2.4.3 STI Process for Gate.................................264
9.2.4.4 Gate Process .............................................264
9.3 Device Technology Challenges ............................................. 265
9.3.1 Multiple Threshold Voltage Devices........................ 265
9.3.2 Width Quantization .................................................. 267
9.3.3 Crystal Orientation................................................... 268
9.3.4 Source-Drain Series Resistance ............................... 270
9.4 Challenges in FinFET Circuit Design ................................... 271
9.5 Summary ............................................................................... 271
References ........................................................................................ 272
Contents xiii

Chapter 10 FinFET Compact Models for Circuit Simulation............................. 277

10.1 Introduction ........................................................................... 277
10.2 Compact Device Model ......................................................... 277
10.3 Common Multiple-Gate Compact FinFET Model ................ 279
10.3.1 Core Model............................................................... 279
10.3.1.1 Electrostatics............................................. 279
10.3.1.2 Drain Current Model ................................ 286
10.3.2 Modeling Real Device Effects ................................. 288
10.3.2.1 Short-Channel Effects .............................. 288
10.3.2.2 Quantum Mechanical Effects ................... 291
10.3.2.3 Mobility Degradation ............................... 294
10.3.2.4 Velocity Saturation ................................... 295
10.3.2.5 Source-Drain Series Resistance ............... 295
10.4 Dynamic Model..................................................................... 296
10.4.1 Common Multigate C – V Model ............................. 296
10.5 Threshold Voltage Variability ............................................... 298
10.6 Summary ...............................................................................306
References ........................................................................................306

Index......................................................................................................................309
Preface
Silicon integrated circuits (ICs) have enormously impacted modern society, serving
as the foundation of the Internet, social media, and interconnected network of net­
works or Internet of Things (IoT). The emerging Internet technologies offer people­
to-people, people-to-machine, and machine-to-machine communications enabling
appliances and services to provide notifications, security, energy-saving, automation,
telecommunications, healthcare, computers, entertainment, and so on. The network
of networks is integrated into a single ecosystem to create smart environments with
a shared user interface. This ongoing progress of smart environments and integrated
ecosystems is made possible due to the continuous miniaturization of metal-oxide­
semiconductor (MOS) field effect-transistor (FET) or MOSFET devices, thus, pro­
viding low-cost, high-density, fast, and low-power ICs. However, the performance of
MOSFETs in the design and manufacturing of “smart” electronic products neces­
sary to create smart networks or “smart things” to enable smart environments and
integrated ecosystems has approached its limits due to the fundamental physical
limitations such as the short-channel effects (SCEs). Shrinking MOSFET device
length in the decananometer regime degrades device performance including degra­
dation in the subthreshold swing and decrease in device turn-on voltage. As a result,
the scaled MOSFETs cannot be turned off easily by lowering the gate voltage lead­
ing to excessive leakage current. And, because of SCEs, the device characteristics
become increasingly sensitive to process variation that imposes a serious challenge
to continued scaling of planar-MOSFETs to the nanometer nodes. Furthermore, at
gate length below 22 nm, the sub-surface leakage paths are weakly controlled by the
gate irrespective of gate oxide thickness and their potential barriers can be easily
lowered by drain bias through the enhanced electric field coupling to the drain. Thus,
to surmount the challenges of continuous scaling of MOSFETs, the fin field-effect
transistor or FinFET has emerged as the real alternative to continue scaling and
manufacture ICs to create smart things and enable smart environments and inte­
grated ecosystems. This book presents the basic features and operating principles of
FinFET devices required for the understanding of design and manufacturing of very
large scale integrated (VLSI) circuits and systems.
A large volume of research articles along with a handful of books are available
on device technology and modeling of FinFETs. Most of the research articles are
meant for experts in the field. On the other hand, the available books on FinFETs are
either dedicated to device modeling for IC design or a collection of research articles
on research and development. Thus, the available literature does not provide the
fundamental principles of FinFET device operation and adequate background for the
understanding of the newly adopted mainstream device technology for beginners as
well as practicing engineers and experts transitioning to FinFET device technology.
After working for over 30 years in the field of semiconductor process and device
architecture and device modeling in industry, and over 20 years of teaching device
and process physics and device modeling courses in academia, I felt the need for a
comprehensive book that presents the fundamentals of FinFET device electronics for

xv
xvi Preface

the understanding of the design and manufacturing of FinFET ICs at the nanometer
nodes. This book provides readers the basic architecture and theory of FinFETs to
continue shrinking devices to the fundamental scaling limits for VLSI manufactur­
ing technology. Starting from the basic semiconductor electronics, this book pres­
ents the principles of operation and modeling of FinFETs. Thus, this book is useful
for beginners as well as experts in the field of microelectronics device and design
engineering to understand the theory and operation of FinFET devices.
This book is intended for the researchers and practitioners working in the area of
electron devices as well as senior undergraduate and graduate students in electrical
and electronics engineering programs. However, the presentation of the materials
is such that even an undergraduate student not well-acquainted with semiconductor
physics can understand the basic concepts of FinFETs.
Chapter 1 presents an introduction to FinFET devices as the alternative to the
mainstream MOSFETs and planar-CMOS technology for VLSI circuits and sys­
tems at the nanometer node. The chapter overviews the scaling constraints of the
mainstream MOSFETs beyond the 22-nm node due to SCEs; discusses the scalable
alternative planar-MOSFETs and non-planar-FinFET devices for VLSI circuits and
systems beyond the 22-nm node; and presents the advantages of the multiple-gate
ultrathin-body FinFET devices in surmounting the SCEs for VLSI circuit manu­
facturing in the sub-22-nm regime. Furthermore, a comprehensive history of the
emergence and development of FinFETs for non-planar-CMOS technology is pre­
sented. Chapter 2 presents a brief overview of the basic semiconductor electronics
and pn-junction operation as background materials for the understanding of FinFET
devices.
Chapter 3 presents the basic structure and operation of multiple-gate MOS
capacitor systems as the foundation for the development of FinFET device theory.
Analytical expressions for multiple-gate MOS capacitor systems are derived to dis­
cuss the accumulation, depletion, and inversion mode operations of multiple-gate
MOS capacitor systems. A unified surface potential function is developed to analyze
the characteristics of multiple-gate MOS capacitors applicable to FinFET devices.
Also, a unified inversion charge expression is derived to account for the substrate
doping effect in multiple-gate MOS capacitors that can be used for FinFET current
calculation.
Chapter 4 provides an overview of FinFET device architecture, process technol­
ogy, and typical fabrication processes for the manufacturing of FinFETs in non­
planar-CMOS technology. Fabrication process flow for FinFETs on bulk-silicon
substrate and on SOI substrate is overviewed and the complexities and benefits of
each technology are highlighted.
Chapter 5 presents the basic theory of FinFETs, formulation of surface potentials,
and presents the electrostatic behavior of long-channel devices. A set of simplifying
assumptions are used to derive a continuous drain current expression for long-chan­
nel devices applicable to all regions of device operation. In addition, the regional
drain current expressions for linear, saturation, and subthreshold operations are
derived from the continuous drain current expression for intuitive analysis of device
performance. Chapter 6 presents the small geometry effects in FinFETs for accu­
rate characterization of real device effects. The mathematical formulation for SCEs,
Preface xvii

including Vth roll-off, DIBL, quantum mechanical effects, low-field mobility, veloc­
ity saturation, and channel length modulation and output resistance is presented.
Chapter 7 discusses the physical mechanisms and mathematical formulation of
the different components of leakage currents in FinFET devices during operation in
VLSI circuits and systems. These leakage currents include the subthreshold leakage
currents due to the close proximity of the drain to the source, the gate-induced drain
and source leakage currents due to band-to-band tunneling, source-drain pn-junction
leakage currents, and gate tunneling currents.
Chapter 8 overviews the parasitic resistance and capacitance elements of FinFETs.
The parasitic resistances include the contact resistance, spreading resistance, and
source-drain extension resistance components of the raised source-drain series resis­
tance as well as the gate resistance. The parasitic capacitances discussed are overlap,
fringe, and the source-drain pn-junction capacitances. Chapter 9 presents an over­
view of the major challenges of the FinFET process, device, and circuit design.
Chapter 10 presents an overview of the present state-of-the-art compact models
for common multiple-gate FinFET devices. Device model includes a core model for
large geometry devices and models for short-channel devices to accurately analyze
the physical and geometrical effects on real devices. The model includes current-
voltage and capacitance-voltage formulations for FinFET devices. Furthermore, a
process variability model is formulated to estimate the effect of dopant fluctuations
in FinFET devices.
An extensive set of references is provided at the end of each chapter to help the
readers identify the evolution and development of FinFETs and FinFET manufactur­
ing technology for ICs at nanometer nodes

Samar K. Saha
January 2020
Author
Samar K. Saha received a PhD in Physics from Gauhati University, India, and
MS in Engineering Management from Stanford University, CA. Currently, he is an
Adjunct Professor in the Electrical Engineering Department at Santa Clara University,
CA, and Chief Research Scientist at Prospicient Devices, CA. Since 1984, he has
worked in various technical and management positions for National Semiconductor,
LSI Logic, Texas Instruments, Philips Semiconductors, Silicon Storage Technology,
Synopsys, DSM Solutions, Silterra USA, and SuVolta. He has also worked as a
faculty member in the Electrical Engineering Departments at Southern Illinois
University at Carbondale, IL; Auburn University, AL; the University of Nevada at
Las Vegas, NV; and the University of Colorado at Colorado Springs, CO. He has
authored more than 100 research papers. He has also authored one book, Compact
Models for Integrated Circuit Design: Conventional Transistors and Beyond (CRC
Press, 2015); one book chapter on Technology Computer-Aided Design (TCAD),
“Introduction to Technology Computer-Aided Design,” in Technology Computer
Aided Design: Simulation for VLSI MOSFET (C.K. Sarkar, ed., CRC Press, 2013);
and holds 12 US patents. His research interests include nanoscale device and process
architecture, TCAD, compact modeling, devices for renewable energy, and TCAD
and R&D management.
Dr. Saha served as the 2016–2017 President of the Institute of Electrical and
Electronics Engineers (IEEE) Electron Devices Society (EDS) and is currently serv­
ing as the Senior Past President of EDS, J.J. Ebers Award Committee Chair, and
EDS Fellow Evaluation Committee Chair. He is a Fellow of IEEE and a Fellow
of the Institution of Engineering and Technology (IET, UK), and a Distinguished
Lecturer of IEEE EDS. Previously, he has served as the Junior Past President of EDS;
EDS Awards Chair; EDS Fellow Evaluation Committee Member; EDS President-
Elect; Vice President of EDS Publications; an elected member of the EDS Board
of Governors; Editor-In-Chief of IEEE QuestEDS; Chair of EDS George Smith
and Paul Rappaport Awards; Editor of Region 5&6 EDS Newsletter; Chair of EDS
Compact Modeling Technical Committee; Chair of EDS North America West
Subcommittee for Regions/Chapters; a member of the IEEE Conference Publications
Committee; a member of the IEEE TAB Periodicals Committee; and the Treasurer,
Vice Chair, and Chair of the Santa Clara Valley-San Francisco EDS chapter.
Dr. Saha served as the head guest editor for the IEEE Transactions on
Electron Devices (T-ED) Special Issues (SIs) on Advanced Compact Models and
45-nm Modeling Challenges and Compact Interconnect Models for Giga Scale
Integration; and as a guest editor for the T-ED SI on Advanced Modeling of Power
Devices and their Applications and the IEEE Journal of Electron Devices
Society (J-EDS) SI on Flexible Electronics from the Selected Extended Papers at
2018 IFETC. He has also served as a member of the editorial board of the World
Journal of Condensed Matter Physics (WJCMP), published by the Scientific
Research Publishing (SCIRP).

xix
 1 Introduction

1.1 Fin FIELD-EFFECT TRANSISTORS

A FinFET or a “fin” field-effect transistor (FET) is a metal-oxide-semiconductor
(MOS) device where the gate is placed on two sides of a thin vertical semiconductor
body standing on a substrate. This novel device was invented by Yutaka Hayashi at
the Electrotechnical Laboratory, Tsukaba, Japan in 1980 [1] and the manufactur­
ing device technology was developed in the late 1990s by the research group led
by Chenming Hu at the University of California Microfabrication Lab, Berkeley,
CA [2]. The “Fin” in the acronym FinFET describes an ultrathin-body “fin” of a
semiconductor material such as silicon as the channel of an FET device. In FinFET
device architecture, the gate may be placed on two, three, four sides, or all around
the ultrathin-body fin for improved device performance, and the devices could be
fabricated on silicon or silicon-on-insulator (SOI) substrates [3,4]. The FinFETs
offer significantly superior device performance including faster switching speed and
higher current drive compared to the mainstream metal-oxide-semiconductor field-
effect transistors (MOSFETs) [3–7]. Thus, considering the advantages of FinFETs
over the conventional MOSFETs, Intel was the first to introduce triple-gate FinFET
technology into mass production at the 22 nm node in the year 2011 [8]. This chapter
presents a brief introduction and the history of the development of FinFET device
technology.
Prior to the introduction of the FinFET structure, a brief overview of the main­
stream MOSFET devices used for integrated circuit (IC) manufacturing technology,
their limitations and scaling challenges, and the need for alternative devices such as
FinFETs for IC manufacturing technology at the nanometer nodes is presented in
Section 1.2.

1.2 OVERVIEW OF MOSFET DEVICES FOR

INTEGRATED CIRCUIT MANUFACTURING
Over the past five decades, silicon-based microelectronic devices have revolution­
ized human society and continue to have an unprecedented impact on every aspect
of modern society [7,9–11]. The basic building blocks of ICs are conductor, semi­
conductor, and insulator materials creating target electrical properties to design very
large scale integrated (VLSI) circuits that are core elements of all modern electronic
devices and systems. These electronic devices and systems enable communica­
tions, military, security, healthcare, energy saving, industrial automation, transport,
autonomous vehicles, entertainment, infotainment, and digital society [10–12]. This
microelectronics revolution started after the invention of bipolar junction transistors
(BJTs) by W. Shockley, J. Bardeen, and W. Brattain at Bell Laboratories in 1947
[13,14], followed by the invention of first working ICs in September 1958 by J. Kilby

1
2 FinFETs for VLSI Circuits and Systems

of Texas Instruments [15,16]. Subsequently, in April 1959, Robert Noyce at Fairchild

patented the practical monolithic IC technology for high volume manufacturing [17].
The inventions of BJTs and ICs paved the way for the realization of complete ICs
with both active and passive elements on monolithic silicon substrates by the late
1950s. And, through the 1960s, the IC or microelectronics industry was dominated
by BJT manufacturing technology.
In the late 1950s, semiconductor companies started the development of manufac­
turing technology for MOSFET device that was invented by J.E. Lilienfeld in 1926
[18]. In 1960, D. Kahng and M. M. Atalla fabricated working MOS transistors and
demonstrated the first MOSFET amplifier enabling cost-effective integration of a
large number of MOSFETs with interconnections on a single silicon chip [19,20].
In 1963, F. Wanlass invented the complementary MOS (CMOS) device configura­
tion to build two-input acting on one output inverter circuit using both n-type and
p-type MOSFET devices [21]. In 1965, Gordon Moore at Fairchild estimated that the
number of transistors per chip would double about every two years which later trans­
formed itself into a law known as “Moore’s law” [22]. The underlying idea behind
Moore’s law was that the smaller devices improve almost every aspect of IC opera­
tion including a reduction in the cost and switching power consumption per transistor
along with enhancement in memory capacity and speed.
The successful development of MOSFET device technology and the cost-effec­
tive integration of a large number of these devices in IC-chips started the progress
of MOSFET technology from the early 1970s. And subsequently, the 1970s saw
MOSFET technology begin to overtake BJT technology in terms of the functional
complexity and level of integration. Moore’s law became the guiding principle to
scale down MOSFET device dimensions to manufacture lower cost, lower power,
and higher computing speed IC-chips from each new generation of technology. To
aid Moore’s law for accurate estimation of device scaling, R. Dennard et al. at IBM
quantified the scaling rules for IC process design in 1974 [23]. These scaling rules
accelerated the global race to shrink physical dimensions of devices and manufacture
more complex VLSI circuits enabling continuous increase in the integration density
proposed by Moore’s law to achieve higher speed and reduced power consumption
of a digital MOS circuit at reduced cost. The high speed and low power consumption
became the driving force for the microelectronics industry to achieve higher integra­
tion density of MOSFETs in every following generation of IC technology [24]. Thus,
CMOS technology with its cost-effective technology solution became the pervasive
technology for ICs from the 1980s [9].
Figure 1.1 shows an ideal conventional MOSFET device structure used in CMOS
technology for manufacturing VLSI circuits. As shown in Figure 1.1, a MOSFET
device is characterized by a channel length Lg, a channel width W, a gate oxide with
thickness Tox, substrate doping Nb, and source-drain with junction depth Xj. In VLSI
circuits, NMOS (p-type body with n+ source-drain) and PMOS (n-type body with
p+ source-drain) FET devices are integrated together and called CMOS transistors.
In the context of device operation, a MOSFET is a four-terminal device with gate,
source, drain, and substrate or body and the corresponding terminal voltages are
Vg, Vs, Vd, and Vb, respectively, as shown in Figure 1.1 [9]. The device is symmetrical
and cannot be distinguished without the applied bias. An applied gate bias Vg above
Introduction 3

FIGURE 1.1 An ideal three-dimensional structure of an advanced four-terminal bulk-MOS­

FET device: here Vg, Vs, Vd, and V b are the applied bias at the gate, source, drain, and body
terminals, respectively; W and Lg are the channel width and channel length of the device,
respectively; and Xj is the source-drain junction depth.

a certain threshold voltage (Vth) induces a conducting channel between the source
and drain at the silicon/silicon dioxide (SiO2) interface of the substrate and a drain
bias Vd is used to generate current-voltage characteristics of the devices. The body
terminal allows the modulation of the inversion layer from the gate as well as body to
offer more flexibility of device performance in circuit operation. The basic operation
of a MOSFET device is available in most books on semiconductor devices [9,25,26].
According to the MOSFET scaling rule [23], as Lg is scaled down, Tox is scaled
proportionately to maintain a strong capacitive coupling between the inversion chan­
nel and the gate terminal with respect to the other transistor terminals. This enables
controlling of the short-channel effects (SCEs) including threshold voltage (Vth) roll-
off, subthreshold swing (S) degradation, and drain-induced barrier lowering (DIBL)
that act together to increase the off-state transistor leakage current (Ioff ) [9,27]. Also,
scaling down Lg is accompanied by a corresponding increase in the body doping Nb
and a decrease in source-drain junction depth Xj to reduce the sub-surface leakage
paths below the channel inversion layer. Thus, the worldwide effort continued for the
miniaturization of MOSFETs and CMOS technology to provide increasingly higher
computing power, lower power consumption, and cheaper cost IC-chips at each new
technology node [24,28].
With aggressive scaling of MOSFETs, the transistor dimensions soon reached
the point at which the first-order assumptions about the physical effects and dopant
distributions began to break down. For MOSFETs, the intrinsic device problem such
as output conductance, velocity saturation, and subthreshold behavior all received
substantial research interest and effort [9,29]. In order to continue device minia­
turization following Moore’s law, the US semiconductor industry association (SIA)
formed the National Technology Roadmap for Semiconductors (NTRS) in 1994 and
4 FinFETs for VLSI Circuits and Systems

transition to the International Technology Roadmap for Semiconductors (ITRS) to

include the global semiconductor companies in 2000 [30,31]. The ITRS defined the
comprehensive guidelines for the future generations of technology by following
Moore’s law and Dennard’s scaling rule. This scaling methodology has worked very
well for several generations of VLSI technology. However, for 32 nm planar-CMOS
technology and beyond, the conventional MOSFET scaling rules could no longer
provide positive improvements in the device performance set by Moore’s law due to
unsurmountable challenges [32–34] as described in Section 1.2.1.

1.2.1 Challenges of MosfeT sCaling aT The nanoMeTer node

The continuous miniaturization of conventional MOSFET devices and planar-
CMOS technology to achieve performance improvement, reduced power consump­
tion, and higher-density integration has become more challenging at the same rate
of Moore’s law due to several constraints imposed by the fundamental principles
of device physics such as SCEs [32–37]. The major constraints to MOSFET device
scaling in the sub-32 nm regime include degradation of leakage current and process
variability-induced device parameter variation [9,26,27].

1.2.1.1 Leakage Current in Short Channel MOSFETs

As MOSFET devices are scaled down in the nanometer regime, the device per­
formance becomes increasingly dependent on gate length, Lg [9,26,27]. As Lg
decreases, the body doping concentration Nb is increased according to the scaling
rule to suppress source-drain punchthrough and sub-surface leakage current (due
to DIBL) [38]. This increase in Nb leads to a reduction in the carrier mobility due
to the enhanced vertical electric field resulting in degradation in the current drive
of the scaled devices [9]. The high vertical electric field at the source-drain junc­
tion due to high Nb, also increases the band-to-band tunneling and thereby off-state
leakage current, Ioff. Thus, scaling MOSFET gate length Lg in the decananometer
regime degrades device characteristics and subthreshold swing as well as decreases
Vth, causing Vth roll-off as shown in Figure 1.2 [9,35].
The subthreshold swing S degradation and Vth roll-off with decreasing Lg due
to SCEs poses a severe challenge to control leakage current in devices beyond the
32 nm node [9,35]. This implies that the scaled MOSFETs cannot be turned off
easily by lowering the gate voltage Vg due to SCEs even with reducing the gate-
dielectric thickness in proportion to Lg following the scaling rule [9,27]. Thus, a
major constraint for the continuous scaling of conventional bulk-MOSFETs is con­
trolling the leakage current in the scaled devices [9,27,38] as shown in Figure 1.3.
The leakage paths that are several nanometers below the silicon/gate-dielectric inter­
face are primarily responsible for the observed leakage current in the scaled devices
at the nanometer nodes [27]. This challenge to scaling Lg led to the enormous efforts
on channel-profile engineering, shallow source-drain extensions (SDEs), and halo
implants around SDEs [4,39–44] to continue scaling MOSFETs at the nanometer
node. However, for the conventional MOSFETs below the 20 nm regime, the sub­
surface leakage cannot be controlled by reducing the gate-dielectric thickness in the
lowest possible value, even with zero thickness [27].
Introduction 5

FIGURE 1.2 The threshold voltage Vth roll-off as a function of the effective channel length
L eff of nMOSFET and pMOSFET devices of a typical 40 nm CMOS technology with effective
oxide thickness, Tox(effective) = 1.5 nm. (Vth is defined as the gate bias, Vgs that is required
to induce a conducting channel between the source and drain of MOSFETs enabling current
flows in devices).

FIGURE 1.3 The drain current Ids versus Vgs characteristics of the conventional nMOSFET
devices of a typical 65 nm CMOS technology as a function of gate length; here the numerical
simulation data are shown to illustrate the continuous increase in the off-state leakage current
for the gate lengths below 60 nm.
6 FinFETs for VLSI Circuits and Systems

1.2.1.2 Variability in MOSFETs

With the continued miniaturization of MOSFET devices [23,31,42–44], the perfor­
mance variability of MOSFETs induced by process variability has become a critical
issue in the design of VLSI circuits using scaled CMOS technologies [45,46]. Process
variability in scaled CMOS technologies severely impacts the delay and power vari­
ability in VLSI devices, circuits, and systems, and this impact keeps increasing as
MOSFET devices and CMOS technologies continue to scale down [45–51]. Because
of SCEs, the device characteristics become increasingly sensitive to Lg variations,
and therefore, the process-induced variability imposes a serious challenge for con­
tinuous scaling of conventional MOSFETs [45–47]. As Lg decreases, Nb is increased
in keeping with the scaling rule to suppress source-drain punchthrough and sub-sur­
face leakage current. The presence of heavy body doping Nb exacerbates the random
device-to-device variability in the form of random discrete doping (RDD) [46–48].
And, in scaled MOSFETs, the RDD is the major contributor to overall variability in
device performance due to Vth variation as shown in Figure 1.4 [9].
The effect of Vth variation causes variation in the performance of devices of the
conventional CMOS technology at the nanometer node as shown in Figure 1.5.
Figure 1.5 shows the distribution of ON-currents, IONN and IONP for the conven­
tional 20 nm nMOSFETs and pMOSFETs, respectively. Here, IONN and IONP are
extracted at the supply bias of magnitude 1 V. The IONN versus IONP distribution
in Figure 1.5, clearly shows the impact of overall process variability on nanometer
scale device performance.
In order to overcome the major scaling challenges of the conventional planar
MOSFETs in the nanometer nodes as described in Section 1.2.1, it is important to
understand the physics of SCEs causing leakage current and the variability in device

FIGURE 1.4 Threshold voltage variation of MOSFET devices for a typical 20 nm bulk-
CMOS technology as a function of device channel length for a channel width of 20 and
200 nm; here, σVth is the variance in threshold voltage due to RDD; all data are taken from
the reference [9].
Introduction 7

FIGURE 1.5 The distribution of ON-currents of pMOSFETs (IONP) and nMOSFETs

(IONN) for a typical 20 nm CMOS technology showing the impact of process variation on
device performance. The nominal values of IONP and IONN are also shown on the plot.
All data are obtained by the industry standard circuit simulation tool using statistical device
model for L eff = 20 nm; Weff = 1000 nm devices; and Tox(effective) = 1.1 nm at gate bias,
Vgs = 1 V = Vds (drain bias).

performance as Lg decreases and discuss the alternative device structures to sup­

press SCEs and enable continuous scaling of devices to improve device performance
according to Moore’s law. In Section 1.2.2, the underlying physical principles of
the above described scaling challenges for the conventional MOSFETs are briefly
discussed.

1.2.2 PhysiCs of MosfeT sCaling Challenges

As shown in Figure 1.3, the Ids–Vgs characteristics of the conventional MOSFETs of
a planar-CMOS technology degrade in two major ways with scaling down Lg. First
of all, S degrades and Vth decreases with decreasing Lg – that is, the device cannot be
turned off easily by lowering Vgs. Secondly, S and Vth become increasingly sensitive
to Lg variations – that is, the variation in device performance becomes more problem­
atic as shown in Figures 1.4 and 1.5. These problems are referred to as the SCEs and
the cause of SCEs in the conventional MOSFETs can be understood from Figure 1.6.
Typically, a transistor is turned ON and OFF when Vg lowers and raises the potential
of the channel, respectively; and thus, modulates the potential barrier between the
channel and the source through the gate-to-channel capacitance, Cg (~Cox, gate oxide
capacitance). In an ideal transistor, the channel potential is controlled only by Vg and
Cg. However, in real MOSFET devices, the channel potential is, also, subjected to the
influence of Vd through the channel-to-drain coupling capacitance Cdsc as shown in
Figure 1.6. For a device with large Lg, Cdsc is significantly smaller than Cg. Therefore,
the influence of Vds is insignificant in modulating the channel and Vgs solely controls
8 FinFETs for VLSI Circuits and Systems

FIGURE 1.6 A conventional MOSFET device showing gate capacitance Cox, bulk capaci­
tance Cd, and the source-drain to channel coupling capacitances Cdsc; with scaling Lg, Cd
increases due to the increase in Cdsc and controls the channel potential in the nanometer node
devices; here, A represents the capacitance voltage divider node between Cox and the effective
capacitance of Cd and Cdsc.

the channel potential. As Lg decreases, the effective value of Cd increases [9,52,53]

and Vgs loses its absolute control of the channel. In extreme cases, Vgs has less con­
trol than Vds and the transistor can be turned on by Vds only as shown in Figure 1.3
for a 30 nm MOSFET device. Before the extreme case (Lg = 30 nm) is reached, we
observe the gradually deteriorating subthreshold device performance in Figure 1.3
with decreasing Lg from 250 nm and below.
The ideal MOSFET scaling rule to increase the gate control of the channel is to
increase Cg by reducing the value of Tox in proportion to Lg [23]. However, the con­
ventional scaling rule is limited to improve Vgs control of the MOSFET channel and
leakage current beyond the 20 nm regime even with the lowest possible Tox due to
fundamental physical constraint as shown in two-dimensional (2D) cross-section of
an ideal planar MOSFET in Figure 1.7 [27]. It is seen from Figure 1.7 that the leak­
age paths far from the gate are worse than the surface leakage path since they are
only weakly controlled by Vgs. As a result, the potential barriers along these weakly
controlled paths can be easily lowered by Vds through the large Cdsc in a small Lg
device as shown in Figure 1.8 [9,27,38].
There are two possible options to overcome the above described scaling constraints
in conventional MOSFETs at the nanometer node planar-CMOS technology. The first
option is the introduction of new technologies and new materials into the conventional
planar bulk-MOSFETs to allow further scaling and boost the performance of scaled
transistors [54,55]. The second option being alternative transistor architectures such
as ultrathin-body FETs and multiple-gate FETs which inherently have superior elec­
trostatic control over the inversion channel [9,27] as discussed in Section 1.3.

1.3 ALTERNATIVE DEVICE CONCEPTS

In order to overcome the increasing challenges in continuous scaling of the conven­
tional planar MOSFET devices, the major research and development efforts for the
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39 Sept
9970 Robinson H
K 28
111 Sept
7607 Robinson A
I 2
95 July
3880 Robinson H C
I 21
115 Aug
6419 Robinson Jno
A 22
 27 Robins L, Cor 154 Mar
K 8
173 Sept
7663 Roberts A
C 3
14 Sept
7585 Rockwell N C A
D 2
85 July
8318 Rockfeller R E
D 23
15 Oct
11342 Rockfeller H Art
M 23
July
3959 Rock F “ 6F
25
July
4350 Rogers A “ 7 I
31
125 Aug
6059 Rogers A
H 18
85 Aug
5791 Rogers G, Mus
F 15
132 July
3011 Rogers Jas
H 7
85 July
4287 Rogers H C
C 30
Sept
8369 Rogers H J Art 2E
10
43 Aug
4912 Rogers M
D 6
85 Aug
7208 Rogers O S, S’t
C 29
12 Aug
6824 Rogers Thos
F 25
Nov
11772 Romer F 9A
3
8468 Rook G Art 6E Sept
 11
152 Sept
9663 Rooney Jno
G 28
132 Sept
9102 Rooney M
F 18
Sept
8922 Rooney P Art 2C
16
85 Aug
5669 Root A N
C 14
120 July
2998 Roots W T
H 7
24 June
1735 Root Legrand Bat
- 8
16 Oct
10278 Rose A
L 2
125 Sept
9550 Rosecrans J E
H 23
23 Sept
8171 Ross C Cav
A 8
111 July
3874 Ross E F
I 24
27 Aug
5591 Ross David
D 14
76 Aug
6741 Ross G
K 24
Sept
9751 Ross A Cav 1M
25
121 Nov
11963 Ross J H
G 11
Aug
5929 Rosenbarger Jno 4D
17
84 July
3616 Rosser Lewis
A 20
2924 Rosenburg J 30 July
A 5
24 Sept
8737 Rosson Chas Cav
E 14
93 Dec
12259 Roswell J
K 10
151 Apr
727 Ross Jacob
A 25
120 June
1940 Row W J
B 14
39 Aug
5097 Roth Louis
D 9
20 Sept
8504 Rothwell M, Cor Cav
M 12
12 July
3720 Rouge Wm, Bug C
F 21
11 Sept
7709 Rowbotham R C
L 3
70 Aug
5857 Rowell J E
G 16
99 July
3492 Rowell L N
H 17
Mar
59 Roberts A B, S’t Cav 8B
18
120 June
2609 Ruddin C
H 28
120 May
867 Rudler Wm
M 3
Mar
40 Rue Newton, S’t Cav 5A
13
69 Sept
8667 Runey F
H 13
12635 Russ Jno 2K Feb 65
 10
Sept
8856 Russell J, Cor Art 7A 64
15
106 Aug
5094 Ryan D
D 8
95 Sept
8599 Ryan J
E 12
22 Sept
8741 Ryan J Cav
E 14
12 Aug
7258 Ryan Owen
A 30
66 Aug
4762 Ryonch Jno
I 5
Aug
6413 Ryson Jno Art 7L
22
39 Aug
6206 Ryne J M
E 9
111 Apr
684 Rush Jno
E 23
85 Aug
7234 Sackett R S
G 29
77 June
1920 Sadley M
H 14
24 June
1880 Safford B J Bat
- 12
Nov
11870 Salsbury H Art 1M
6
16 Oct
10652 Salisbury E
D 11
13 Oct
10923 Samlett —— Cav
I 14
15 Oct
10880 Samet W
H 13
3769 Sampson J 106 July
K 22
Sanders Chas, Apr
346 Mil 9A
Cor 2
99 July
3618 Sanders J
C 23
12 Sept
9857 Sanders J Cav
A 27
July
4423 Sandford P O Art 7L
31
12 June
2341 Saughin J Cav
F 23
Sept
7740 Sawyer J “ 2L
3
22 Oct
11232 Sayles A “
E 21
85 July
3612 Seaman A, Cor
H 19
2 Oct
10856 Seaman A Art
- 13
May
1372 Sears F Cav 2H
25
Aug
6120 Seagher J 8M
19
11 July
4325 See Henry
K 30
140 Sept
8824 Seeley A J
A 15
15 Oct
11374 Seeley C B
H 24
100 July
4256 Seeley Thos
F 29
10027 Segam Ed Cav 5K Sept
 29
10 July
4204 Seigler Geo
- 29
120 Sept
7458 Seigle John R
K 1
59 Nov
11886 Selson H
C 6
40 July
3457 Serrier R
C 17
June
1746 Serine C Cav 4M
8
99 Apr
629 Settle Henry
H 19
Sept
9828 Seyman F Cav 1A
27
77 Aug
5951 Seard Louis
E 17
21 Aug
6888 Schayler J W Cav
M 26
160 Oct
10794 Schadt Theo
A 12
July
3557 Scheck B Cav 2G
18
120 July
3190 Schemerhorn H
G 12
Nov
11965 Schempp M Art 7F
11
170 July
2795 Schermashie B
A 2
Schlotesser J, 91 May
1325
S’t H 24
Oct
11515 Schlotesser J 1L
26
9578 Schmaker Jno 30 Sept
B 23
Oct
10291 Schmaley J 1G
16
39 Oct
10550 Schmeager A
A 9
39 Aug
5311 Schneider Chas
A 11
24 Sept
8595 Shockney T T Bat
- 12
Sept
8796 Schofield J 7H
15
54 June
2441 Scholl Jno
D 25
59 Oct
11422 Schriber H
I 24
Sept
7814 Schroeder G Art 7E
4
14 Sept
8550 Schrum J “
K 12
20 May
1070 Schrimer Wm
B 13
12 July
4280 Schware F Cav
K 20
66 Aug
6613 Schwick A
G 23
85 Aug
4849 Scott J C, S’t
K 6
14 Aug
6857 Scott P C Cav
G 26
Sept
8622 Scott W W “ 2F
13
8290 Sibble W 148 Sept
 G 9
July
4362 Sick R E - -
31
Aug
4557 Sickler E Art 7E
2
120 July
3210 Sickles A
D 12
40 Nov
11950 Siddell G
- 10
Dec
12284 Simmons A Art 8H
13
Simmons C G, 85 Aug
6364
S’t B 21
116 Sept
8316 Simon H
B 10
85 Aug
6284 Simons H L, S’
E 20
155 Mar
142 Simondinger B
I 24
99 Mar
242 Simpson D
H 30
22 Aug
6345 Sisson P V, S’t Art
M 21
50 Sept
10067 Shaab J 64
A 30
61 Mar
201 Shea Pat, Drum’r
M 28
7 Aug
4801 Shaffer M Art
- 5
66 Aug
4584 Shaffer J
E 2
103 Apr
782 Shafer H
F 28