Information Technology University

Laboratory Manual
for
CS233: Digital Logic and Design
Course Instructor : Ma’m Hafsa Batool
Semester Fall 2023 : 1
Teaching Assistant : Muhammad Ahmad
Teaching Assistant : Moeed Ahmad
Teaching Assistant : Rimsha Ashfaq

Student Name :
Student Roll No. :

Department of Computer Science ITU, Lahore, Pakistan

LAB-15

Design an SR latch for your ease first.(not a task, just a

hint).
 Task-01:
Design a D-flip flop from SR latch.

Working: (truth table, Characteristic table, Expression,

circuit)

Task-02:
Design a T-flip flop from SR latch.

Working: (truth table, Characteristic table, Expression,

circuit)

Truth Table:
T Q Q’
0 0 0
1 0 1
0 1 0
1 1 0
Characteristic Table:
T Qn Qn + 1 S R
 0 0 0 0 x
0 1 1 x 0
1 0 1 1 0
1 1 0 0 1

Expression:
T ⊕Qn

Circuit:

Task-03:
Design a synchronous counter (use D-flip flop).
Working: (State tables, expressions, circuit)

Task-04:
Design a Asynchronous counter (use EITHER a T-flip
flop OR D-flip flop).

Working: (State tables, expressions, circuit)

Task-05:
Design a Shift Register (make EITHER a SIPO OR
PISO).

Working: ( all required working must be shown)