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Advanced FPGA Architectures for Efficient Implementation of Computation

Intensive Algorithms: A State-of-the-Art Review

Article · September 2009

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MASAUM Journal of Computing, Volume 1 Issue 2, September 2009
Advanced FPGA Architectures for Efficient
Implementation of Computation Intensive
Algorithms: A State-of-the-Art Review
Syed M. Qasim, Shuja A. Abbasi, Senior Member, IEEE, and Bandar A. Almashary, Member, IEEE
Abstract—Algorithms used in signal processing, image
processing and high performance computing applications are
computationally intensive. For efficient implementation of such
algorithms with efficient utilization of available resources, an in-
depth knowledge of the targeted field programmable gate array
(FPGA) technology is required. This paper presents a state-of-
the-art review of the architectures and technologies used in
modern FPGAs. A case study of most popular and widely used
state-of-the-art commercial FPGA technologies from Xilinx and
Altera is also presented in this paper. Upcoming three-
Dimensional (3D)-FPGA architecture is also discussed.
Index Terms—Architecture, Field Programmable Gate Array
(FPGA), Hardware, Review, Technology.
I. INTRODUCTION
C OMPUTATION
and image
intensive algorithms used in digital signal
processing, multimedia, wireless
communications, cryptography and networking applications
were first realized using software running on digital signal
processors (DSPs) or general purpose processors (GPPs).
However, with advancement in very large scale integration
(VLSI) technology, hardware implementation has become an
attractive alternative. Significant speedup in computation time
can be achieved by assigning computation intensive tasks to
hardware and by exploiting the parallelism in algorithms [1].
Recently, field programmable gate arrays (FPGAs) have
emerged as a platform of choice for efficient hardware
implementation of computation intensive algorithms [1]-[2].
Especially, when the design at hand requires very high
performance, designers can benefit from high density and high
performance FPGAs instead of costly multicore digital
signal processing (DSP) systems. FPGAs enable a high degree
This work was supported in part by a Research Grant from the Research
Center of College of Engineering at King Saud University.
Syed Manzoor Qasim is with the Electronics Group, Electrical
Engineering Department, College of Engineering, King Saud University,
Riyadh, Saudi Arabia 11421 (fax: +966-1-4676757; e-mail: smanzoor@
ksu.edu.sa).
Shuja Ahmad Abbasi is with the Electronics Group, Electrical Engineering
Department, College of Engineering, King Saud University, Riyadh, Saudi
Arabia 11421 (e-mail: abbasi@ksu.edu.sa).
Bandar Almashary is with the Electronics Group, Electrical Engineering
Department, College of Engineering, King Saud University, Riyadh, Saudi
Arabia 11421 (e-mail: bmashary@ksu.edu.sa).
252
of parallelism and can achieve orders of magnitude speedup
over GPPs. This is as a result of the increasing embedded
resources available on FPGA. FPGAs have the benefit of the
hardware speed and the flexibility of software. FPGAs offer
cheap and fast programmable silicon on some of the most
advanced fabrication processes. Many different architectures
and programming technologies have evolved to provide better
designs that make FPGAs economically viable and an
attractive alternative to application specific integrated circuits
(ASICs).
The three main factors that play an important role in FPGA-
based designs are the targeted FPGA architecture, electronic
design automation (EDA) tools and design techniques
employed at the algorithmic level using hardware description
languages. The objective of this paper is to examine and
present a state-of-the-art review of advanced FPGA
architectures and technologies used for efficient hardware
implementation of computation intensive algorithms. A case
study of state-of-the-art Xilinx and Altera FPGAs is also
presented in this paper.
The remainder of the paper is structured as follows. Section
II presents a brief overview of FPGA technology. In section
III, classification of FPGAs based on the arrangement of the
logic and interconnect resources is provided. Section IV and V
presents a case study of state-of-the-art Xilinx and Altera
FPGAs respectively. Three-Dimensional (3D)-FPGA
architecture is also studied and briefly presented in section VI.
Finally, conclusion is presented in section VII.
II. FPGA TECHNOLOGY
FPGAs are programmable digital integrated circuits which
consist of configurable logic blocks (CLBs) and input/output
blocks (IOBs) located around the periphery of the chip. By
using the appropriate configuration, FPGAs can implement
any complex digital circuit as long as their available resources
are adequate. Modern FPGAs have superior logic density, low
chip cost and performance specifications comparable to low-
end microprocessor. With multimillion programmable gates
per chip, FPGAs are now capable of implementing digital
systems operating at frequencies beyond 550 MHz.
Commercial FPGAs are broadly classified into two major
categories depending on the way in which they are configured
MASAUM Journal of Computing, Volume 1 Issue 2, September 2009
[1], [3]-[5].
A. One-time configurable FPGAs
This type of FPGA can be programmed once in its entire
life time. FPGAs manufactured by Actel are programmed with
anti-fuses and belong to this category. Such FPGAs are very
economical because antifuses occupy very little silicon real
estate and are able to hold their state without the support of
any backup external storage devices.
B. Reconfigurable FPGAs
This is a more common type of FPGAs and widely utilized
for reconfigurable digital system designs because
reconfigurable FPGA can be programmed over and over again
to implement new designs. These are generally static random
access memory (SRAM) or erasable programmable read only
memory (EPROM) based programmable circuits where
devices can be programmed with electronic signals. They are
called reconfigurable because their programming is not
permanent and can be loaded with new configuration bits to
perform a new task. Xilinx and Altera manufacture FPGAs of
this type. Reconfigurable FPGAs are further categorized into
the following subgroups.
1) Statically reconfigurable FPGAs: These types of FPGA
are programmed with an external device by loading
configuration bitstream in programming mode. The
configuration data is stored in SRAM or EPROM within
the FPGA and can be erased or reprogrammed very easily.
However, it is not possible to program the device or
change the design when it is being used.
2) Dynamically reconfigurable FPGAs: These types of
FPGA are used for run-time reconfiguration (RTR). Since
modern FPGAs can accommodate more than ten million
gates on chip, hence it is not reasonable to configure the
huge on-chip resource completely. Therefore, modern
FPGAs also support partial reconfiguration which can be
programmed at run-time to change the underlying
hardware. In some applications, on-the-fly partial
reconfiguration is a very useful feature to adopt the
change of behavior dynamically to meet the needs of
certain applications and perform tasks more efficiently.
Such applications may be a specialized task like
algorithms for adaptive digital filter, data compression,
image processing or to create an evolvable hardware
design.
III. FPGA INTERCONNECT ARCHITECTURE
Based on the arrangement of the logic and interconnect
resources, FPGAs are broadly categorized into four main
types.
A. Island Style FPGAs
It consists of an array of programmable logic blocks
connected via vertical and horizontal programmable routing
channels [6]. A logic block input or output can connect to the
routing channels with the connection box that consists of
253
multiple user programmable switches such as pass transistors
or bidirectional buffers. The horizontal and vertical routing
channels are connected at every intersection with user
programmable switch box. Switch boxes are also made of
programmable switches, which allow user to program the
routing channels.
B. Row based FPGAs
It consists of logic blocks which are arranged in parallel
rows with horizontal routing channels running between
successive rows. The routing tracks within the channel are
divided into one or more segments. The segments can be
connected at the ends using programmable switches to increase
their length. Series of vertical wires are overlaid on the logic
blocks, and users can program the interconnects from the
inputs and outputs of the logic blocks to the wires in the
horizontal channels. The Actel ACT-3 FPGA family belongs
to this group [7].
C. Sea-of-Gate FPGAs
It consists of fine grain logic blocks covering the entire floor
of the device [8]. Connectivity is realized using dedicated
neighbor-to-neighbor routes that are usually faster than general
routing resources. Usually the architecture also uses some
general routing resources to realize longer connections. The
Actel ProASIC FPGA family is an implementation of the sea-
of-gate approach [8].
D. Hierarchical FPGAs
These FPGAs are made in a hierarchical fashion with a
network of interconnects which can be programmed by the
users [9]. Most logic designs exhibit locality of connections,
which imply a hierarchy in the placement and routing of the
connections between the logic blocks. The hierarchical FPGAs
try to exploit this feature to provide smaller routing delays and
a more predictable timing behavior. This architecture is
created by connecting logic blocks into clusters. These clusters
are recursively connected to form a hierarchical structure. The
speed of the network is determined by the number of routing
switches it has to pass through. The hierarchical structure
reduces the number of switches in series for long connections
and can hence potentially run at a higher speed. The Altera
Flex, Cyclone II, Stratix II families have two hierarchical
levels.
IV. CASE STUDY OF XILINX FPGA ARCHITECTURES
Due to the parallel nature, high frequency, and high density
of modern FPGAs they make an ideal platform for the
implementation of computationally intensive and massively
parallel architecture. FPGA can accommodate multiple
processors and control units that work in parallel. This section
presents a case study of state-of-the-art FPGAs from Xilinx.
These include Spartan-3, Virtex-4 and Virtex-5 FPGAs.
A. Spartan-3 FPGAs
The Spartan-3 FPGA belongs to the fifth generation Xilinx
MASAUM Journal of Computing, Volume 1 Issue 2, September 2009
family. It is specifically designed to meet the needs of high
volume, low unit cost electronic systems. The family consists
of eight member offering densities ranging from 50,000 to five
million system gates [10]. The Spartan-3 FPGA consists of
five fundamental programmable functional elements: CLBs,
IOBs, Block RAMs, dedicated multipliers (18×18) and digital
clock managers (DCMs). Spartan-3 family includes Spartan-
3L, Spartan-3E, Spartan-3A, Spartan-3A DSP, Spartan-3AN
and the extended Spartan-3A FPGAs.
Spartan-3L FPGAs consume less static current than the
corresponding members of the standard Spartan-3 family. Its
capability to operate in hibernate mode lowers device power
consumption to the lowest possible levels. The Spartan-3E
family builds on the success of the earlier Spartan-3 family by
increasing the amount of logic per I/O, significantly reducing
the cost per logic cell. The Spartan-3A family builds on the
success of the earlier Spartan-3E and Spartan-3 FPGA families
by increasing the amount of I/O per logic, significantly
reducing the cost per I/O.
The Spartan-3A DSP FPGA is built by extending the
Spartan-3A FPGA family by increasing the amount of memory
per logic and adding XtremeDSP DSP48A slices. The
XtremeDSP DSP48A slices replace the 18x18 multipliers
found in the Spartan-3A devices. The Spartan-3AN FPGA
family combines all the features of the Spartan-3A FPGA
family plus leading technology in-system flash memory for
configuration and nonvolatile data storage. It is excellent for
applications such as blade servers, medical devices,
automotive infotainment, GPS and other small consumer
products. Extended Spartan-3A FPGA includes non-volatile
Spartan-3AN devices, which combine leading edge FPGA and
flash technologies to provide a new evolution in security,
protection and functionality, ideal for space-critical or secure
applications.
B. Virtex-4 FPGAs
Virtex-4 FPGAs are produced on a state-of-the-art 90 nm
copper process, using 300 mm wafer technology [11]. It
consists of three platform families i.e., LX, SX and FX.
Virtex-4 hard-IP core blocks include the IBM PowerPC (PPC)
405 32-bit reduced instruction set computer (RISC)
processors, tri-mode Ethernet media access controls (MACs),
622 Mbps to 6.5 Gbps serial transceivers, dedicated DSP
slices and high-speed clock management circuitry. Virtex-4
devices consume approximately 50% the power of respective
Virtex-II Pro devices due to static and dynamic power
reduction enabled by triple-oxide technology and reduced core
voltage and capacitance respectively. The Virtex-4 FPGA
family comprises of CLBs, Block RAMs, XtremeDSP Slices
and DCMs.
Block RAM stores relatively large amounts of data more
efficiently than the distributed RAM. The Virtex-4 Block
RAM resources are 18 Kb true dual-port RAM blocks,
programmable from 16K×1 to 512×36, in various depth and
width configurations. Each port is totally synchronous and
independent. Block RAM is cascadable to implement large
254
embedded storage blocks.
XtremeDSP slices contain a dedicated 18×18-bit 2’s
complement signed multiplier, adder, and a 48-bit
accumulator. Each multiplier or accumulator can be used
independently and can be used to implement extremely
efficient and high speed DSP and image processing algorithms
[11].
C. Virtex-5 FPGAs
The Virtex-5 devices built on a 65 nm state-of-the-art
copper process technology are a programmable alternative to
custom ASIC technology [12].The Virtex-5 LX platform also
contains many hard-IP system-level blocks, including Block
RAM/first in first out (FIFO), second generation 25×18 DSP
slices, SelectIO technology with built-in digitally-controlled
impedance, ChipSync source-synchronous interface blocks,
enhanced clock management tiles with integrated DCM and
phase locked loop (PLL) clock generators, and advanced
configuration options.
In addition to the regular programmable functional
elements, Virtex-5 family provides power-optimized high
speed serial transceiver blocks for enhanced serial
connectivity, tri-mode Ethernet MACs and high-performance
PPC 440 microprocessor embedded blocks. Virtex-5 devices
also use triple-oxide technology for reducing the static power
consumption. Their 1.0 V core voltage and 65 nm
implementation process leads also to dynamic power
consumption reduction as compared to Virtex-4 devices.
The Virtex-5 family is the first FPGA platform to offer a
real 6-input look-up table (LUT) with fully independent inputs
as shown in Fig. 1. This leads to increased logic fabric
performance due to the reduced critical path delay through the
LUTs.
Fig. 1. Virtex-5 6-input LUT architecture (Courtesy of Xilinx Inc.)
It implements significantly more logic than a LUT with four
inputs. Power consumption is also reduced because the larger
LUT reduces the amount of required interconnects [12].
Virtex-5 family uses a new diagonally symmetric interconnects
to minimize the number of interconnects required from CLB to
CLB in order to realize major performance improvements
[12].
Advanced DSP48E slices are available in Virtex-5 FPGAs
that helps in accelerating computation intensive DSP and
MASAUM Journal of Computing, Volume 1 Issue 2, September 2009
image processing algorithms. These slices can operate at a
maximum frequency of 550 MHz, drawing only 1.38 mW/100
MHz.
V. CASE STUDY OF ALTERA FPGA ARCHITECTURES
This section presents a case study of state-of-the-art FPGAs
from Altera. These include Cyclone/Cyclone II, Stratix/Stratix
GX and Stratix-II/Stratix-II GX devices.
A. Cyclone/Cyclone II FPGAs
Cyclone FPGAs use a two-dimensional row and column-
based architecture to implement custom logic. It is based on a
1.5 V, 0.13 µm, all layer copper SRAM process [13]. Cyclone
II FPGAs is based on TSMC 90 nm low-k dielectric process in
order to extend the functionality of Cyclone FPGAs [14].
The smallest unit of logic in the Altera FPGA family is the
logic element (LE). Each LE contains a four-input LUT. A
collection of ten LEs constitute a logic array block (LAB)
which is a fundamental programmable functional element in
Altera FPGAs.
A significant addition to the Cyclone/Cyclone II FPGA
features is the addition of embedded multiplier blocks for the
efficient implementation of multiplier intensive DSP functions
[14]. In addition to these, cyclone FPGA also includes
embedded memory blocks and PLLs for clock management.
B. Stratix/Stratix GX FPGAs
Stratix and Stratix GX families are also based on a 1.5 V,
0.13 µm, all layer copper SRAM process, with higher
densities. Stratix devices offer up to 22 embedded DSP blocks
for applications that enable efficient implementation of high-
performance filters and multipliers. Stratix devices support
various I/O standards and also offer a complete clock
management solution with its hierarchical clock structure with
up to 420 MHz performance and up to 12 PLLs [15].
Stratix GX family of devices is Altera’s second FPGA
family to combine high-speed serial transceivers with a
scalable, high-performance logic array. Stratix GX devices
include 4 to 20 high-speed transceiver channels, each
incorporating clock data recovery (CDR) technology and
embedded SERialiser/DESerialiser (SERDES) capability at
data rates of up to 3.1875 Gbps. The Stratix GX FPGA
technology is built upon the Stratix architecture. This scalable,
high-performance architecture makes Stratix GX devices ideal
for high-speed backplane interface, chip-to-chip, and
communications protocol-bridging applications [16].
Stratix/Stratix GX FPGAs use advanced TriMatrix memory
which consists of three types of RAM blocks: M512, M4K and
MRAM blocks. In the Stratix family connections between LEs,
TriMatrix memory, DSP blocks, and device I/O pins are
provided by the MultiTrack interconnect structure with
DirectDrive technology. The MultiTrack interconnect consists
of continuous, performance-optimized routing lines of
different lengths and speeds used for inter- and intra-design
block connectivity. DirectDrive technology is a deterministic
255
routing technology that ensures identical routing resource
usage for any function regardless of placement within the
device.
C. Stratix II/Stratix II GX FPGAs
Stratix II and Stratix II GX FPGA families are based on a
1.2 V, 90 nm, all layer copper SRAM process and offer up to 9
MB of on-chip, TriMatrix memory for demanding, memory
intensive applications and have up to 96 DSP blocks with up
to 384 multipliers for efficient implementation of high
performance DSP functions [17]. Stratix II devices support
various I/O standards along with support for one Gbps source
synchronous signaling with dynamic phase alignment (DPA)
circuitry.
Stratix II devices offer a complete clock management
solution with internal clock frequency of up to 550 MHz and
up to 12 PLLs. Stratix II devices have the ability to decrypt a
configuration bitstream using the advanced encryption
standard (AES) algorithm to protect designs. Stratix II GX
devices have somewhat fewer logic resources than the
respective Stratix II devices due to the space occupied by the
embedded transceivers [18].
Adaptive logic module (ALM) is the basic building block
used in Stratix II architecture. The ALM packs more
combinational logic into less area, providing a higher logic
density than a standard 4-input LUT architecture and more
logic per register as shown in Fig. 2.
It contains a variety of LUT based resources that can be
divided between two adaptive LUTs (ALUTs). In addition to
the ALUT-based resources, each ALM contains two
programmable registers, two dedicated full adders, a carry
chain, a shared arithmetic chain, and a register chain. Through
these dedicated resources, the ALM can efficiently implement
high performance arithmetic functions and shift registers. Each
LAB of Stratix II FPGA family consists of eight ALMs [17]-
[18].
Fig. 2. Block Diagram of Stratix-II ALM (Courtesy of Altera Inc.)
VI. 3D-FPGA ARCHITECTURE
Although the two-dimensional (2D)-FPGA architecture
discussed so far has several advantages such as high degree of
flexibility and inherent parallelism, it suffers from a major
problem of long interconnect delays. As discussed in [19]-
[20], almost 80% of the total power is dissipated in
MASAUM Journal of Computing, Volume 1 Issue 2, September 2009
interconnects and clock networks. To reduce the interconnect
delay, 3D-FPGA was proposed in [21]-[22].
3D-FPGA model is based on the 2D-FPGA architecture that
are vertically stacked and interconnects are provided between
vertically adjacent 3D-switch blocks. The vertical stacking
results in reduction of total interconnect length which
eventually results in achieving reduced interconnect delay,
improved performance and speed.
However, the advantages associated with 3D-FPGA can be
fully exploited only when supported by an efficient placement
and routing algorithm which is currently a hot research topic.
Several research groups from academia and industry are
currently working to achieve this objective. This topic is of
great importance and will be further explored in detail as
future work.
VII. CONCLUSION
For efficient hardware implementation of computation
intensive algorithms with efficient and proper utilization of
available resources, it is important to study the targeted FPGA
architecture and technology in detail. The objective of this
paper has been to present a state-of-the-art review of advanced
FPGA architectures and technologies that can be utilized by
the designers and researchers working in this area to achieve
high performance and efficient FPGA-based circuits and
systems. We have also presented a case study of most widely
used state-of-the-art Xilinx and Altera FPGAs respectively.
We also briefly presented the advantages and current research
going on in the area of 3D FPGAs.
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Syed M. Qasim received the B.Tech and M.Tech Degrees in Electronics
Engineering from Z. H. College of Engineering and Technology, Aligarh
Muslim University, India in 2000 and 2002 respectively. Currently, he is
working as a Researcher in the Electronics Group, Department of Electrical
Engineering, King Saud University, Saudi Arabia. He is the author or
coauthor of more than 30 papers in international journals and refereed
conferences.
He is a member of the Institution of Electronics and Telecommunication
Engineers, India and International Association of Engineers, Hong Kong. His
current research interests include Digital VLSI System Design and High
Performance Reconfigurable Computing using FPGAs.
Shuja A. Abbasi was born in Amroha, India in 1950. He obtained the B.Sc
and M.Sc Degrees in Electrical Engineering from Z. H. College of
Engineering and Technology, Aligarh Muslim University, India in 1970 and
1972 respectively. He received the Ph.D Degree in Microelectronics from
University of Southampton, England in 1980. He joined as Lecturer at
Aligarh Muslim University in 1971, was promoted to the positions of Reader
and Professor in 1982 and 1986 respectively. He served as the Chairman,
Department of Electronics Engineering, Z. H. College of Engineering and
Technology, Aligarh Muslim University from 1996 to 1999. He joined as a
Professor of Electronics Engineering at College of Engineering, Department
of Electrical Engineering, King Saud University, Riyadh in1999 and is
continuing since then.
He has fairly large number of research publications to his credit so far and
has completed many client funded projects from various organizations. He is
a senior member of IEEE and Fellow of Institution of Electronics and
Telecommunication Engineers, India.
Bandar A. Almashary is an Associate Professor in the Department of
Electrical Engineering, King Saud University, Saudi Arabia. He received the
BS and MS Degrees in Electrical Engineering from King Saud University,
Saudi Arabia. He received the Ph.D Degree in Optoelectronics from
University of Pittsburgh, USA in 1996. He has fairly large number of research
publications to his credit. He is a member of IEEE.