Professional Documents
Culture Documents
PDF Microlithography Science and Technology 3Rd Edition Bruce W Smith Editor Ebook Full Chapter
PDF Microlithography Science and Technology 3Rd Edition Bruce W Smith Editor Ebook Full Chapter
PDF Microlithography Science and Technology 3Rd Edition Bruce W Smith Editor Ebook Full Chapter
https://textbookfull.com/product/microlithography-science-and-
technology-third-edition-smith/
https://textbookfull.com/product/psychology-the-science-of-mind-
and-behaviour-3rd-edition-michael-w-passer/
https://textbookfull.com/product/computational-science-and-
technology-5th-iccst-2018-kota-kinabalu-
malaysia-29-30-august-2018-rayner-alfred/
https://textbookfull.com/product/computational-science-and-
technology-6th-iccst-2019-kota-kinabalu-
malaysia-29-30-august-2019-rayner-alfred/
Computational Science and Technology 7th ICCST 2020
Pattaya Thailand 29 30 August 2020 Rayner Alfred
(Editor)
https://textbookfull.com/product/computational-science-and-
technology-7th-iccst-2020-pattaya-
thailand-29-30-august-2020-rayner-alfred-editor/
https://textbookfull.com/product/handbook-of-essential-oils-3rd-
ed-science-technology-and-applications-3rd-edition-kemal-husnu-
can-baser/
https://textbookfull.com/product/computational-science-and-
technology-4th-iccst-2017-kuala-lumpur-
malaysia-29-30-november-2017-1st-edition-rayner-alfred/
https://textbookfull.com/product/windows-powershell-in-
action-3rd-edition-bruce-payette/
https://textbookfull.com/product/smith-tanaghos-general-urology-
jack-w-mcaninch/
Microlithography
Microlithography
Science and Technology
Third Edition
Edited by
Bruce W. Smith and Kazuaki Suzuki
Third edition published 2020
by CRC Press
6000 Broken Sound Parkway NW, Suite 300, Boca Raton, FL 33487-2742
Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume respon-
sibility for the validity of all materials or the consequences of their use. The authors and publishers have attempted to trace the
copyright holders of all material reproduced in this publication and apologize to copyright holders if permission to publish in this
form has not been obtained. If any copyright material has not been acknowledged please write and let us know so we may rectify
in any future reprint.
Except as permitted under U.S. Copyright Law, no part of this book may be reprinted, reproduced, transmitted, or utilized in any
form by any electronic, mechanical, or other means, now known or hereafter invented, including photocopying, microflming, and
recording, or in any information storage or retrieval system, without written permission from the publishers.
For permission to photocopy or use material electronically from this work, access www.copyright.com or contact the Copyright
Clearance Center, Inc. (CCC), 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400. For works that are not available on CCC
please contact mpkbookspermissions@tandf.co.uk
Trademark notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identifcation
and explanation without intent to infringe.
Typeset in Times
by Deanta Global Publishing Services, Chennai, India
Contents
Preface to Third Edition ..................................................................................................................vii
Editors...............................................................................................................................................ix
Contributors ......................................................................................................................................xi
Chapter 6 Design for Manufacturing and Design Process Technology Co-Optimization ....... 293
John Sturtevant and Luigi Capodieci
v
vi Contents
Index.............................................................................................................................................. 825
Preface to Third Edition
Semiconductor micro- and nanolithography continues to provide the necessary support to drive
Moore’s Law with future nanometer-scale device generations. With technological innovation in
imaging systems, materials, processing, modeling, and optimization, what had once been envi-
sioned as technical barriers to advancement are continually surpassed to allow increasingly more
capable devices. The drumbeat of smaller, faster, cheaper, and lower power continues as the world
moves into new technology applications demanding tremendously increased processing and storage
capacity. Combined with new forefronts in electronics and photonics, the applications for nano-
electronic devices have grown well beyond the needs of microlithography covered in the frst and
second editions of Microlithography: Science and Technology.
To address the new technology that has evolved over the last several years, this Third Edition
of Microlithography: Science and Technology has been completely revised. While providing a
balanced treatment of theoretical and operational considerations, from fundamental principles to
advanced topics of nanoscale lithography, this edition details the technology necessary for current
and future device generations. It provides the necessary reference for students and engineers to
learn the fundamental as well as understand the future requirements of the challenging technology
behind lithography at the nano scale. It also provides the basis for more experienced engineers to
understand the interdisciplinary nature of microlithography, which involves aspects of many areas
of science and engineering.
The book is divided into 13 chapters, starting with an overview of the lithography requirements
of semiconductor processing (Lithography, Etch, and Silicon Process Technology, Chapter 1) and
exploring the details of all the technologies involved. Chapters include Optical Nanolithography
(Chapter 2), Multiple Patterning Lithography (Chapter 3), EUV Lithography (Chapter 4), Alignment
and Overlay (Chapter 5), Design for Manufacturing and Design Process Technology Co-optimization
(Chapter 6), Chemistry of Photoresist Materials (Chapter 7), Photoresist and Materials Processing
(Chapter 8), Optical Lithography Modeling (Chapter 9), Maskless Lithography (Chapter 10),
Imprint Lithography (Chapter 11), Metrology for Nanolithography (Chapter 12), and Directed
Self-Assembly of Block Copolymers (Chapter 13). The Third Edition has involved contributions
from 29 renowned experts from the world’s leading academic and industrial organizations to pro-
vide in-depth coverage of these technologies. As a result, we are certain that the Third Edition of
Microlithography: Science and Technology will remain a highly valuable resource for students,
engineers, and researchers well into the future.
Bruce W. Smith
Kazuaki Suzuki
vii
Editors
Bruce W. Smith is a Distinguished Professor of engineering at the Rochester Institute of Technology.
He has been involved in teaching and research in microelectronic and microsystems engineering
for over 35 years. His areas of research include semiconductor processing, deep ultraviolet (DUV),
vacuum ultraviolet (VUV), immersion, and extreme ultraviolet (EUV) lithography, thin flms,
optics, and microelectronic materials. He has authored over 250 technical publications, given over
100 technical talks, and received over 25 patents, licensing his technology both nationally and
internationally. He has worked extensively with individuals and organizations in the semiconductor
industry, including industrial partners in the Semiconductor Research Corporation, SEMATECH,
and the IMEC. He is the recipient of numerous teaching and research awards, including the Institute
of Electrical and Electronics Engineers (IEEE) Technical Excellence Award, the American Vacuum
Society (AVS) Excellence in Leadership Award, the Society for Photo-optical Instrumentation
Engineers (SPIE) Research Mentoring Award, and the Rochester Institute of Technology Trustees
Scholarship Award. He has also been inducted into the Rochester Institute of Technology Innovator
Hall of Fame. Professor Smith is a Fellow of the Institute of Electrical and Electronics Engineers,
the Optical Society of America, and the Society for Photo-optical Instrumentation Engineers.
Kazuaki Suzuki majored in plasma physics and X-ray astronomy in the University of Tokyo, Japan.
He has been a project manager for developing new concept exposure tools at Nikon Corporation,
such as the early-generation KrF excimer laser stepper, the frst-generation KrF excimer laser scan-
ner, the electron beam projection exposure system, and the full-feld extreme ultraviolet scanner. He
received his Ph. D. in Precision Engineering from the University of Tokyo about the system design
of exposure tools for microlithography. He has authored and coauthored many papers in the feld of
exposure tool and related technologies, including advanced equipment control by using metrology
data. He also holds numerous patents in the same feld. In the frst decade of this century, he was
a member of the program committee of the Society for Photo-optical Instrumentation Engineers
(SPIE) Microlithography and other international conferences such as Micro & Nano Engineering
in Europe and the International Microprocesses and Nanotechnology Conference in Japan. He was
one of the associate editors of Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3) from
2002 to 2009. He moved to Tokyo Tech Academy for Convergence of Materials and Informatics at
Tokyo Institute of Technology (Tokyo Tech) in March 2019.
ix
Contributors
Robert D. Allen Stephan Müllender
IBM Research Almaden Carl Zeiss SMT GmbH
xi
1 Lithography, Etch, and
Silicon Process Technology
Matthew Colburn, Derren N. Dunn, and Michael A. Guillorn
CONTENTS
1.1 Introduction ..............................................................................................................................1
1.2 Lithography Fundamentals .......................................................................................................5
1.2.1 Image Formation and Modeling ...................................................................................6
1.2.2 Diffraction-limited Imaging: Abbe Imaging Theory ...................................................7
1.2.3 Numerical Aperture ......................................................................................................9
1.2.4 Kohler Illumination ......................................................................................................9
1.2.5 Partially Coherent Imaging ........................................................................................ 10
1.2.6 Hopkins Diffraction Theory of Imaging and Transmission Cross Coeffcients ........ 11
1.2.7 Impact of Illuminator.................................................................................................. 13
1.2.8 Sub-resolution Assist Features (SRAFs) ..................................................................... 14
1.2.9 Optical Proximity Correction ..................................................................................... 16
1.2.10 Etch Modeling ............................................................................................................ 18
1.3 Lithography Process and Tolerance Assessment .................................................................... 19
1.3.1 Transitions in Lithography.......................................................................................... 22
1.3.2 Immersion Lithography .............................................................................................. 23
1.3.3 Negative Tone Imaging ............................................................................................... 23
1.4 Multiple Patterning and Overlay Optimization ......................................................................24
1.4.1 Self-Aligned Integrated Solutions ..............................................................................28
1.5 Reactive Ion Etch and Deposition Processes .......................................................................... 30
1.5.1 Reactive Ion Etch ........................................................................................................ 31
1.6 Extreme Ultraviolet (EUV) Lithography................................................................................ 32
1.7 Summary ................................................................................................................................34
References ........................................................................................................................................ 35
1.1 INTRODUCTION
Since Gordon Moore made his prophetic observation [1] that transistor density is doubling every
2 years (commonly referred to as “Moore’s law”), the semiconductor industry has been steadily
pushing the limits of lithography, etch, and Si process technology to deliver denser integrated cir-
cuits. For over 50 years, feature scaling in integrated circuits has enabled a reduction in circuit area.
It stands to reason that with this reduction in area, a commensurate reduction in parasitic resistance
and capacitance would follow, resulting in an improvement in device and circuit performance. The
theory that describes the relationship between feature scaling and device performance was estab-
lished by Dennard and coworkers in 1974 [2]. Simply stated, by scaling all dimensions by a given
factor, κ, as shown in Figure 1.1, while simultaneously increasing doping by κ and decreasing oper-
ating voltage by κ to maintain constant feld, power can be reduced by κ2 or operating speed can be
increased commensurately. While there are limits to this scaling approach [3], this theory provided
1
2 Microlithography
FIGURE 1.1 Schematic of scaled device in which key device dimensions are scaled by a factor of κ to
reduce power or improve performance. (Adapted from Dennard, R.H. et al., IEEE J. Solid-State Circuits, 9,
256, 1974.)
the governing principles of technology development, ensuring that the value proposition behind
Moore’s law remains true. It is important to note that scaling can be leveraged to emphasize per-
formance improvement or power reduction. This duality has enabled a singular base semiconductor
process technology to be tailored for high-performance computational applications as well as for
low-power mobile applications [4].
In spite of the practical framework that scaling theory provides, it is misleading to think of
Moore’s law as being driven solely by shrinking dimensions. Moore himself noted in a 1975 speech
[1] that a “contribution of device and circuit cleverness’’ was required to account for the unabated
progress in the performance of semiconductor products. As we enter the sixth decade of Moore’s
law scaling, the contribution of device and circuit cleverness coupled with continued advancements
in lithography and patterning solutions have become equally important in maximizing the return on
investment for developing new generations of semiconductor technologies.
Examples of “cleverness’’ in device architecture and process technology are found in abun-
dance throughout the history of the semiconductor industry. The need to improve power dissipa-
tion drove the industry to transition from bipolar to complementary metal–oxide–semiconductor
(CMOS) technology [5] in the 1980s. The pursuit of reduced parasitic junction capacitance led to
the development of silicon-on-Insulator (SOI) device technology in the 1990s. The industry learned
to manipulate channel mobility through stress engineering [6], and channel material engineering [4,
7] in the late 1990s and early 2000s, producing large gains in device performance through enhanced
drive current. Degraded control of the felds in the channel region at scaled gate lengths, referred to
as short channel effects, led to the pursuit of a reduction in effective gate oxide thickness (EOT) by
pushing Si-based gate dielectrics beyond the point once thought physically possible [8]. This trend
continued in the late 2000s with the implementation of high-permittivity, high-κ gate dielectrics and
metal gate electrodes, producing further scaling of EOT [9] and reduced power due to a reduction
in gate oxide leakage. In parallel with this revolution in gate processing, numerous advancements
Lithography, Etch, and Silicon Process Technology 3
in junction engineering and silicide formation enabled signifcant improvements in junction depth
control and contact resistance reduction [10].
Practical schemes featuring “double gate” fully depleted devices for improving short channel
effect control have been studied since the early 1990s [11] and are illustrated in Figure 1.2. This
work illustrated a path forward toward deeply scaled devices. Further conceptual work on such
devices was carried out in the late 1990s [12], and experimental work was published in the early
2000s [13]. However, manufacturing concerns prevented widespread acceptance of this approach.
In the late 1990s, work on transistors with three-dimensional (3-D) channel geometries featuring
improved electrostatics began to transition from university labs [14] to industrial research facilities
[15]. The operating principle of these devices was simple: raise the channel out of plane, allowing
the gate electrode to wrap around the channel, and reduce the body thickness to form a “fn”-like
structure, resulting in a superior geometry from an electrostatic point of view. This device, now
referred to as the FinFET, continued to gain traction in the industry in the mid-2000s [16]. By the
early 2010s, the FinFET became the standard device for all leading-edge CMOS technologies [17].
Innovation has not been limited to the front end of line (FEOL), that is, transistor device struc-
ture prior to contact formation. As feature density increased and critical dimensions dipped well
below 250 nm, control of wafer topography became a formidable challenge. Planarization technol-
ogy prior to interconnect metallization had been explored early in the semiconductor industry, rely-
ing on refow of doped glass dielectric. However, reliability concerns and performance degradation
proved to be shortcomings of these processes. In contrast, the use of chemical mechanical polishing
(CMP) for planarization of high-quality dielectrics in the back end of line (BEOL) became a foun-
dation on which all high-performance CMOS interconnect technologies were built. For a review,
the author refers the reader to Krishnan et al. [18]. Improvements in BEOL topography through
CMP enabled one of the most important materials innovations in the history of the semiconductor
industry: the transition from Al interconnects to Cu interconnects.
The adoption of Cu interconnect metallurgy using the damascene [19] process provided a
materials solution for signifcantly reducing interconnect resistance (R) with the added beneft of
reduced reliability failures from electromigration [20], an example of which is shown in Figure 1.3.
Additional performance gains were achieved by the introduction of several materials and struc-
tural innovations, a comparison of which can be seen by comparing the left and right sides of
Figure 1.3. First, the adoption of reduced-permittivity, low-κ dielectrics led to reduced interconnect
capacitance (C). Building off advances in low-κ dielectric materials, further reductions in permit-
tivity were achieved through the introduction of airgap technology, achieving the lowest capacitance
possible [22–24].
An important second innovation in BEOL architecture was the introduction of new ultrathin
liner technology [20], which further reduced interconnect resistance at deeply scaled dimensions
FIGURE 1.2 Comparison of depletion regions for Planar Bulk, Planar FDSOI, and FinFET. Note SOI
Structures generally have thicker SOI Si thicknesses relative to FinFET Si thicknesses. (Adapted from Frank,
D. J. et al., Proceedings of the IEEE, 89, 259, 2001.)
4 Microlithography
FIGURE 1.3 Representative schematic of a BEOL structure. (From Colburn, M., SPIE Advanced Etch
Conference Plenary, 2015.)
by maximizing the cross-sectional area of the Cu portion of the interconnect while maintaining
aggressive reliability specifcations. Further innovations in microstructural engineering [25] dem-
onstrated a path to maintain BEOL performance while continuing to achieve further dimensional
scaling.
It is undeniable that there are physical limits to scaling within transistors as dimensions approach
near-atomic dimensions. In the FEOL, short channel effects, quantum effects, and stochastic varia-
tion such as line-edge roughness, feature placement variation, and random dopant fuctuation [26]
will ultimately limit device performance. Variants of planar silicon on insulator (SOI) devices to
enhance low power performance have been proposed for the mobile/hand-held space [27]. More
advanced 3-D channel architectures including gate all around (GAA) devices have been proposed
to continue scaling in the high-performance space. In addition, a resurgent interest in vertical tran-
sistors [28], as well as higher-mobility transistor materials including III–V [29] materials, has also
been proposed to extend device scaling improvements for both high-performance and low-power
applications.
In the BEOL, challenges to continued device scaling are equally great. Nonlinear increases in
resistivity at small dimensions [30] and dielectric breakdown due to increased electric feld strength
are reaching fundamental materials limits [31]. There are a limited number of variables that can be
used to tune performance and address challenges in interconnect architecture: interconnect pitch,
line width, aspect ratio, interconnect resistivity (metallization), interlayer dielectric constant, and
dielectric thickness. Within these constraints, copper interconnect resistance increases exponen-
tially as line width reduces below 100 nm primarily due to grain boundary scattering. The dielec-
tric constant of a vacuum bounds the remaining improvements achievable by reducing dielectric
constant. Within the confnes of these increasing technologic challenges, fabrication of statistically
yieldable and reliable device architectures have been enabled by advances in patterning technology.
In the face of these daunting obstacles, circuit area reduction through cell-level area scal-
ing has become a subject of intense interest [32]. The area that a logic or memory cell occupies
directly impacts density at the product level [33]. This relationship has encouraged the develop-
ment of process technologies optimized for delivering smaller logic cells. To frst order, logic
cell area is dictated by the minimum gate pitch, the number of gates, the minimum wiring pitch
transverse to the gates, and the number of wiring “tracks” required to complete the connec-
tions within the cell. By aggressively scaling these parameters, smaller logic cells can be syn-
thesized, resulting in more compact circuit blocks, which occupy a smaller area and therefore
have lower parasitic resistance and capacitance. However, a careful co-optimization of logic cell
design, lithographic patterning techniques, and device process technology—referred to as design
Lithography, Etch, and Silicon Process Technology 5
technology co-optimization (DTCO)—is required to achieve products that deliver the desired
power, performance, and area scaling without compromising yield. DTCO has become a staple of
the semiconductor industry since the 22 nm node [34]. Taking a holistic approach to patterning
process development in view of device process technology and circuit design has become a new
frontier in enabling device scaling [35].
Understanding the fundamental contributions of patterning process optimization to advanced
device architectures is vital for anyone undertaking work in advanced CMOS technology develop-
ment. This chapter reviews fundamental aspects of patterning process optimization by exploring
essential elements of lithography, optical proximity correction (OPC), and reactive ion etch (RIE)
technology. A discussion of modern patterning techniques used to push feature resolution beyond
the limitations of optical systems is also provided. Finally, an overview of the current state of
extreme ultraviolet (EUV) lithography is presented. This material is presented in the context of
advanced integrated circuit manufacturing to provide a frame of reference for engineers and scien-
tists looking for an introduction to this feld.
FIGURE 1.4 Historic trend of scale resolution power (λ/NA) including EUV. (From Colburn, M., Lithography
Solutions for the 22nm Node, VLSI, Honolulu, HI, 2009. With permission.)
6 Microlithography
micromirror array, designed to optimize overall image fdelity through computational wave front
engineering techniques [40]. Photomask images are reduced by a factor of four (4×) and projected
onto the wafer. Modern lithography tools do not project the full image of the mask on the wafer at
one time; rather, they move or scan the photomask four times (commensurate with the scale factor)
faster than the wafer stage motion or scan. This scanning motion of the mask and wafer gives rise
to the use of the term scanner for modern production lithography systems.
FIGURE 1.5 Schematic diagram of a modern stepper showing the path of light through an optical system
using Kohler illumination from source to wafer.
Lithography, Etch, and Silicon Process Technology 7
FIGURE 1.6 Schematic representation of a lithographic system as viewed from a Fourier optics perspective.
Additionally, it is also commonly assumed that geometric optics can be used to model the lens and
apertures contained within the optical system; thus, the fnite extent of the entrance and exit pupils
is found by geometrically projecting the smallest aperture contained within the optical system to
the object and image planes. Waves entering and exiting the optical system are then limited by the
effective angular extent of the entrance aperture of the optical system and equivalently impacted by
the effective angular extent of the exit aperture of the optical system.
In general, optical systems used in modern lithographic scanners are diffraction-limited sys-
tems. Diverging spherical waves from point source elements entering the optical system are trans-
ferred through the system and exit as converging spherical waves emanating from the exit pupil.
Diffraction limits of the entrance aperture and the exit aperture of the optical system limit the
spatial frequencies transferred by the system equivalently, because the entrance and exit pupils of
the optical system are geometric projections of each other. Also, the effective diffraction limit of the
optical system is dictated by the smallest aperture in the optical system projected onto the entrance
or exit pupils.
In the following sections, essential elements of modern optical systems will be described in
terms of a set of optical transfer functions, which in aggregate, allow computational lithographers
to rapidly and accurately calculate the impact of lenses, aberrations, and diffraction limitations on
the formation of images in the wafer plan from lithography mask images in the object plane shown
in Figure 1.5.
FIGURE 1.7 Optical system representing essential elements of a system following Abbe imaging theory.
objective lens, which, in a far-feld approximation, propagates to form an image in the image plane
shown in Figure 1.7. We can represent the amplitude distribution at the image plane, Ui(xi,yi), from
this imaging system as a superposition integral of wave amplitudes, Uo(xo,yo), scattered by the object
as follows [41, 42]:
¥ ¥
Ui ( xi , yi ) =
ò ò O( x , y ; x , y )U ( x , y ) dx dy
-¥ -¥
i i o o o o o o o (1.1)
In this integral, a point in the image plane (xi,yi) is mapped from a point in the object plane
(xo,yo), by a linear transformation that directly accounts for the magnifcation of the optical
system, M, which can be either positive or negative depending upon whether or not the image is
inverted [41].
This integral can be understood as the convolution of the Fraunhofer diffraction pattern of the exit
pupil of the system represented by the function O, with the idealized image of the object calculated
from geometric optics, Uo. O can then be written as follows:
¥ ¥
é 2p ù
O ( xi , yi ; xo , yo ) = Co
ò ò P( x, y)exp ëê-i ld ((x - Mx )x + (y - My )y )úû dx dy
-¥ -¥
i
i o i o (1.3)
In this equation [41], P(x,y) is a discrete function, referred to as the pupil function, that has a non-
zero value for (x,y) points in the exit aperture of the optical system and is zero for all other points,
di represents a spatial frequency in the object being imaged, and Co is a normalization constant.
Conventionally, this representation is rewritten in optical coordinates:
x y
x¢ = , y¢ = , x¢o = Mxo , y¢o = Myo
l di l di
¥
1 æ x¢o y¢o ö
Ui ( xi , yi ) = 2
M ò O ( x - x¢ , y - y¢ )U çè M , M ÷ø dx¢ dy¢
-¥
i o i o o o o (1.4)
Lithography, Etch, and Silicon Process Technology 9
In general, this integral is thought of as the convolution of the object image predicted by geometric
optics with the exit pupil function of the optical system [41]. This formulation allows computational
lithographers to use methods developed for the analysis of linear systems to establish accurate, but
computationally effcient, approaches to calculating aerial images for simulation OPC.
1.22l
di = (1.5)
2n sin q
The denominator in this equation, 2nsinθ, is used as a defning characteristic of the resolving power
of the optical systems that follow Abbe imaging [43]. The term nsinθ is defned to be the NA of the
optical system and describes the acceptance half-angle of the objective lens.
FIGURE 1.8 Enlarged section of the object shown in Figure 1.7. Two object points, separated by di and
diffracting waves through the maximum acceptance angle of the lens, are used to defne the numerical aper-
ture of an optical system. (From Jenkins, F. A. and White, H. E., Fundamentals of Optics, McGraw-Hill,
New York, 1957. With permission.)
10 Microlithography
FIGURE 1.9 Diagram depicting the essential elements of Kohler illumination. Partially coherent source
waves are defocused through a series of source and condenser optical elements to produce parallel illumina-
tion of a mask.
coherent points on the source were focused in the sample plane. To overcome these limitations,
August Köhler developed a method of illuminating an object using a system of auxiliary and con-
denser lenses to illuminate the object with nearly parallel waves from the source.
In an idealized system, waves illuminating the mask will be spherical with radius of curvature
selected to offset the impact of tilted illumination on mask features located at positions off the
optical axis [44]. Also, this arrangement of source and condenser lenses has the added beneft that
inhomogeneities in source intensity do not cause irregularities in the illumination feld [42]. An
important additional result is that condenser lens aberrations will have negligible impact on the
degree to which waves from source points remain parallel [42].
Figure 1.9 shows a schematic diagram containing the essential optical elements of Köhler illu-
mination. Köhler illumination provides uniform parallel illumination of the mask from partially
coherent point sources and minimizes positional shifts in the image plane for features far away from
the optical axis. Apertures in the system are used to optimize wave fronts from different source
types and ensure optimal parallel illumination of the mask.
U * (r1 ) U (r2 )
I (ri ) = I r1 (ri ) + I r2 (ri ) + 2 I r1 (ri ) I r2 (ri ) (1.6)
2 I r1 (ri ) I r2 (ri )
Lithography, Etch, and Silicon Process Technology 11
In this equation, U*(r1) and U(r2) are phasors emanating from points r1 and r2 and the term
U * (r1 ) U (r2 ) is the cross-correlation of light emanating from points r1 and r2 normalized by the
intensity of light from each point if it were an independent point source [42, 45]. In addition, the
U * (r1 ) U (r2 )
term is called the complex degree of coherence and represents the intensity of
2 I r1 (ri ) I r2 (ri )
light due to interference between waves from r1 and r2 at point ri in the image plane.
There are two primary limiting cases for this equation. In the frst, the distance between r1 and
r2 approaches zero; then, light from source points 1 and 2 is completely correlated, and the inten-
sity distribution in the image plane is the same as that for two coherent waves. In the second, the
distance between points 1 and 2 approaches infnity, and light from points 1 and 2 is completely
uncorrelated; therefore, the intensity distribution in the image plane at ri is equivalent to a com-
pletely incoherent image [45]. Understanding partially coherent imaging concepts in lithography is
particularly important, because illumination sources consisting of multiple points of light are rou-
tinely used. In addition, complex off-axis illumination sources are required to increase resolution
and enable lithographic scaling.
¥ ¥ ¥ ¥
I ( x, y ) =
ò ò ò ò TCC( f ¢, g¢ : f ², g²)F( f ¢, g¢)F ( f ², g²)
*
-¥ -¥ -¥ -¥ (1.7)
expp é -2p i
ë (( f ¢ - f ²) x + ( g¢ - g²) y )ùû df ¢dg¢df ²dg²
In this equation, the term TCC( f ¢, g¢ : f ², g²) is referred to as the transmission cross coeffcient
(TCC) of the optical system, F ( f ¢, g¢) is the Fourier transform of the mask, and F * ( f ², g²) is the
complex conjugate of the Fourier transform of the mask. This equation represents the partially
coherent imaging of the mask denoted by F illuminated by two sets of partially coherent plane
waves, ( f ¢, g¢) and ( f ², g²). In addition, the TCC term in Equation 1.7 represents the propagation of
source waves through the aberrated pupil function presented previously.
¥ ¥
é -2p i ù
TCC ( f ¢, g¢ : f ², g² ) =
ò ò P ( f + f ¢, g + g¢) exp ëê
-¥ -¥
l
f ( f + f ¢, g + g¢ ) ú
û
(1.8)
é 2p i ù
exp ê f ( f + f ², g + g² ) ú df dg
ë l û
In both the Hopkins intensity integrals and the TCC integrals, the integrals are taken over infnite
domains, but these integrals become fnite due to diffraction-limited optics. Also, in the case of
the TCC, the intensity over the entrance aperture of the optical system is assumed to be constant,
so the TCC integrals reduce to a constant multiplying the integral over a spatial frequency range,
f2 + g2 < r 2 , where r represents the pupil extent of the entrance aperture of the optical system.
12 Microlithography
FIGURE 1.10 Illustration of the effective domain of integration for one pole of a dipole illuminator. The
cross-hatched region illustrates the region over which TCC integration would be taken for source points cen-
tered at (- f ¢, g¢) and ( f ², g²). (From Toh, K. K., Tech. Rep. No. UCB/ERL M88/30, University of California at
Berkeley, Berkeley, CA, 1988. With permission.)
Figure 1.10 shows an example of the integration region used to calculate the TCC for the right-
hand pole of a dipole source [47]. In this example, there are two source circles centered at (- f ¢, g¢)
and ( f ², g²), each of radius NA/M ls , where NA is taken at the entrance aperture of the objective sys-
tem, M is the Gaussian magnifcation in the wafer plane, and λs is the mean wavelength of the source
laser (Figure 1.11). These two source points are transmitted through the optical system of effective
aperture of radius r that is capable of generating partially coherent images at the wafer plane. In a full
TCC calculation for a dipole source like that shown in Figure 1.12, there would be a similar pole with
source points similar to those at ( f ¢, g¢) and (- f ², g²) that would generate the left-hand pole.
FIGURE 1.11 Comparison of diffracted orders captured for conventional and off-axis illumination [38]. Off-
axis illumination captures higher frequencies that result in denser printable pattern (at a fxed λ/NA). (From
Brunner, T. A. et al., J. Micro. Nanolithogr. MEMS MOEMS, 5, 5, 2006. With permission.)
Lithography, Etch, and Silicon Process Technology 13
FIGURE 1.12 Comparison of aerial images for off-axis illumination. (a) Dipole Illumination 0.7/0.9;
(b) quadrupole (0.75/0.97) Illumination; (c) annular (0.75/0.97) Illumination. One can see the horizontal and
vertical contrast difference visually from the aerial images for three k1 values: 0.45 (left column), 0.35 (middle
column), and 0.28 (right column). (From Brunner, T. A. et al., J. Micro. Nanolithogr. MEMS MOEMS, 5, 5,
2006. With permission.)
l
CDmin = k1 (1.9)
2NA
In Equation 1.9, the constant of proportionality, k1, captures lithographic process components that
contribute to the achievable critical dimension for a given lithographic process. This constant of
proportionality is a measure of lithographic process performance that ranges from slightly larger
than 0.25 to values of approximately 1. A k1 value of 0.25 represents the ultimate resolution of an
optical system and should be thought of as an asymptotic lower limit for a lithographic process.
Larger k1 values represent processes that are not delivering the maximum resolution for the scanner
defned by λ and NA.
In its simplest form, with off-axis illumination (OAI), one can defne classic annular, quadrupole,
and dipole illuminators as shown in Figure 1.12. OAI leverages two-beam interference of zeroth
and frst order to provide contrast at high resolution at the expense of through-pitch performance.
Annular illumination is defned by the inner and outer radius of a ring of intensity in the illumi-
nator used to expose the mask. Historically, annular illumination is appropriate for designs that
require a continuous range of supported feature sizes and pitches in orthogonal orientations requir-
ing k1 < 0.5. As k1 is reduced toward a value of 0.25, annular illumination begins to yield smaller
process windows, which require a change in illumination to overcome.
Quasar illumination is defned by four off-axis poles with a well-defned radial extent and fxed
angular extent for each pole. Experience has demonstrated the beneft of this strategy for bidirec-
tional design spaces at tighter pitches (k1 > 0.35), but it suffers at very low k1 (k1 ® 0.25) due to
lack of captured diffraction orders. A quadrupole with poles on axis, sometimes called a c-quad
confguration, offers better resolution in both directions and can enhance tip-to-tip image formation
but generally suffers at intermediate pitches.
14 Microlithography
FIGURE 1.13 Comparison of NILS for an optimized illuminator and an annular illuminator. Through the
entire clip range consisting of one-dimensional and two-dimensional patterns, the SMO illuminator provides
superior NILS, which typically translates into larger process window.
Dipole illumination is defned by two on-axis poles with a well-defned radial extent and fxed angu-
lar extent for each pole. Dipoles are applied to design spaces with preferred or unidirectional features
requiring tight across-chip critical dimension control and k1 approaching 0.25, but they have degraded
image formation for features aligned in the nonpreferred orientation. One drawback of dipole illumina-
tion is that forbidden pitch ranges develop as the radial extent or sigma range of each pole increases.
As we have shown in the previous examples, the use of OAI allows lithography engineers to tai-
lor illumination to a particular design space. These examples represent an approach to illuminator
design that focuses on simple optical elements customized to enable continued device scaling over
a broad range of design styles.
Recent advancements in hardware and software have resulted in more sophisticated illumina-
tions. Source mask optimization (SMO) technology leverages pixelated illumination and co-opti-
mized masks to improve design space coverage and patterning process window on wafer. Utilizing
sophisticated algorithms [49], fexible programmable illuminators [50, 51], and improvements in
mask fabrication, it is now possible to increase design space coverage and process window simul-
taneously. An example of an SMO solution compared with a conventional illumination solution is
shown in Figure 1.13.
Figure 1.13 shows an illuminator determined by SMO compared with a more traditional annular
illuminator. In this plot, the SMO illuminator has yielded signifcantly higher normalized image
log slope (NILS) response than the annular illuminator. Higher NILS translates into more robust
imaging and process window for applicable resist systems. It is clear from Figure 1.13 that both
illuminators are challenged for clips 1 to 5 and 10 to 20. These clips should be examined carefully
by lithography engineers to ensure that there is suffcient process window for these constructs to
enable targeted patterning yield specifcations; otherwise, these constructs may need to be addressed
through ground-rule constraints, retargeting, or new patterning process approaches.
contrast of diffracted light in isolated spaces, approximately 2× the minimum pitch and larger, can
be improved by adding additional spatial frequencies into the formation of an image. An example of
the image with and without a sub-resolution feature is shown in Figure 1.14.
In the case of a 2× minimum pitch structure, a sub-resolution feature (too small to print) can
add a higher spatial frequency of diffracted light into the capture angle of the lens. When combined
with lower (greater than 2× minimum printable pitch) resolution, one can see improved contrast of
the image. This improves the depth of focus and process window for the isolated structures. One
consequence of SRAF usage is unintended printing of the higher-order pattern. It is necessary to
balance the relative size of the SRAF (ease of mask fabrication) with the unintended (side-lobe)
printing of the SRAF.
A natural question to ask at this point is how the introduction of SRAFs improves process win-
dow for isolated features. Shown in Figure 1.15 is a comparison of process window for an isolated
trench feature with and without SRAFs using a typical annular illuminator. In Figure 1.15a and b,
mask features from a baseline isolated trench and an isolated trench with two SRAFs per edge are
shown. In these fgures, the cross-hatched features are transmitting, and the white background does
not transmit light.
The size of SRAFs in Figure 1.15b and their spacing from the main feature are chosen based
on two criteria. First, the dimension of SRAFs features is chosen to boost the intensity of the main
feature to a maximum value, such that the SRAF features do not print. Second, to frst order, the
spacing between the main feature and the SRAF features is chosen to approximate a fully nested
grating. It is clear from Figure 1.15 that the introduction of SRAFs has resulted in a signifcant
increase in depth of focus, from 195% to 272%, which is an increase of approximately 77%. The
increase in dose latitude is more modest but still improved from 4.9% to 6.8%. The features shown
in Figure 1.15 are an idealized case, but they do demonstrate the benefts of using SRAFs.
Aside from SRAF printing, there are some other challenges that computational pattering engi-
neers face when using SRAFs, such as mask manufacturing rule constraints (MRCs), inability of
mask processes to produce SRAFs of the prescribed size to produce maximum process window
FIGURE 1.14 Schematic representation of the intensity for a 2× minimum pitch L/S without SRAF, 1×
minimum pitch (higher frequency), and (bottom) a small trench at 2× minimum pitch with two different
SRAFs. (Black) Mid-sized SRAF and (gray) large SRAF. One can see the improved sharpness of the SRAF
isolated pitch pattern and that increasing the SRAF size too close to the anchor leads can lead to inadvertent
printing. Note that the large SRAF image drops below the threshold for the resist in this thought experiment.
16 Microlithography
FIGURE 1.15 Comparison of isolated trench printing with and without SRAFs. (a) Schematic of horizontal
trench feature without SRAFs. In this diagram, the cross-hatched feature transmits light and the white back-
ground does not. (b) Schematic diagram of a horizontal trench feature with two SRAFs per edge. (c) Ellipsoidal
process window of isolated trench feature showing baseline dose-latitude and depth of focus. (d) Ellipsoidal
process window with two SRAFs per edge showing a signifcant increase in depth of focus and a modest
increase in dose latitude.
beneft, and challenges in ensuring that SRAF geometry and size distributions do not overwhelm
shot count constraints introduced by mask writers.
I
t makes one feel very sick to cry for a long time. Peggy cried till
she was so tired that she had to stop because it hurt her to go on.
Her face was swollen up, and her eyes were red, and she looked
quite ugly. But at last she got so tired that she fell sound asleep,
and only wakened up to have dinner. It was a horrid dinner—cold
mutton, rice pudding without raisins in it, and with no sugar sprinkled
over it; that was all. However, Peggy was wonderfully hungry, and
she ate it up. Then came a very long hour. She sat up in bed, and
looked out at the ships; she made hills and valleys with the sheets,
piling them up, and smoothing them out; she counted the roses on
the wall-paper; she plaited the fringe of the counterpane into dozens
of little plaits, and yet the clock in the hall had only struck three.
There was the whole long day to get through!
Then she heard the door-bell ring, and some one was shown into
the drawing-room. She wondered who it could be.
After ten minutes or so, she heard the drawing-room door open
again, and Aunt Euphemia’s voice in the hall, saying,—
“No; Peggy is in bed to-day!”
“In bed? I hope the little woman isn’t ill!” some one said—Dr.
Seaton, Peggy thought, with a throb of delight. Perhaps he would
help her.
“No, not ill. I am sorry to say she was a very naughty child. I am
keeping her in bed as a punishment.”
Peggy heard the speakers pause near her door. Dr. Seaton had
evidently stood still as he was going out.
“Not all day, I hope, Miss Roberts,” he said. “It’s not good for the
child in this hot weather. You don’t want to have her ill on your
hands?”
Aunt Euphemia then began to give him the whole history of the
night before; and Dr. Seaton seemed to listen, as if it were all new to
him.
“Well, she told you honestly about it, Miss Roberts. Don’t you
think half a day in bed will be enough punishment, this time?” he
said.
“I wish to be firm!” said Aunt Euphemia; but there was a sound of
wavering in her voice that made Peggy wriggle in bed with delight,
for she thought her hour of release was coming.
“Suppose you let the child get up now,” Dr. Seaton urged.
“Oh, she will just get into some fresh mischief the moment she is
out of bed. I never saw a child like her,” said Aunt Euphemia; “Martin
is quite worn out with looking after her.”
“I saw that pleasant-looking cook of yours gathering currants in
the kitchen-garden as I came past. Why don’t you let Peggy help
her? She couldn’t get any harm there, I fancy,” said Dr. Seaton. “But
I must go now. Good-bye, Miss Roberts.”
And Peggy heard him run down the steps. Would she be allowed
to get up? She held her breath. Aunt Euphemia came in.
“Peggy, if you are a very good girl you may get up now, and go
out into the kitchen-garden and gather black currants with Janet,”
she said.
The words were scarcely uttered before Peggy was out of bed
and struggling into her clothes. She was in such a hurry that she put
on her stockings on the wrong side, and fastened her frock all wrong;
but she managed to get dressed somehow, though she would have
been much quicker if she had not been in such a hurry—which
sounds absurd, but is quite true. Then out into the sunny garden she
ran as fast as her feet could carry her. It was deliciously warm, and
such a nice, hot, fruity smell was all over the place. Janet wore a big
straw bonnet, and carried a basket already half full of black currants.
She gave Peggy a very warm welcome, for, unlike Martin, she
was one of those people who love children.
“Dearie me, Miss Peggy! This is fine. Come away and see which
of us will gather quickest,” she said. “Here’s a wee basket for you,
and a wee one for me; and you take the one side of the bush, and I’ll
have the other, and see who’ll be first!”
She laid down her large basket between them, and got out the
two tiny baskets instead. It is much nicer to gather fruit in small
baskets that are soon filled, for one seems to be getting on so much
quicker. Peggy worked at a great pace, and actually got her basket
full before Janet, to her great delight. Then it was poured into the
large basket, and she began again. Thus the work went on for an
hour at least. Peggy was just beginning to think she was getting a
tiny bit tired, when Janet laid down her basket suddenly.
“Come in-bye, Miss Peggy,” she said. “I hear the baker’s man at
the back door; maybe he’ll have something for you.”
Peggy followed her to the kitchen, where the baker’s man had
just laid down some loaves on the table. They were still warm, and
the crust had the nicest smell you can imagine.
“I’m thinking you’d like a piece,” said Janet, taking up one of the
new loaves, and looking at Peggy. “It wasn’t much o’ a dinner Martin
took upstairs for ye.”
“That was because I was naughty,” Peggy admitted with a blush.
“Ye’re no naughty now!” said Janet.
She took a knife, and cut a slice of the
nice new bread. Then from the cupboard
she took out a round pat of beautiful fresh
butter, stamped with a swan, and spread it
thickly on the bread. Last of all, she
sprinkled a lot of sparkling, brown Jamaica
sugar from the sugar-jar over it, and
handed the bread to Peggy.
“Oh, how nice! May I sit on the
doorstep and eat it?” Peggy cried.
I don’t suppose, though she lived to be a hundred years old, she
would ever forget the taste of that bread and sugar, it was so
delicious.
Janet was getting out a huge brass pan from the scullery, and
Peggy wanted to know what it was meant for.
“It’s to make jam in, Miss Peggy; but that’s too hot a job for you.
Maybe if you go and play for an hour and come back, I’ll let you stir
the pan for a minute then,” said Janet. And then, anxious that Peggy
should get into no further mischief that night, she suggested the
washing-green as a safe place to spend the hour in. There were
shamrocks growing there, and clover; and if Peggy could find a four-
leaved clover, she would be lucky all the rest of her life, she assured
her.
The washing-green was very cool and pleasant, and Peggy lay
on her face on the grass and searched for that four-leaved clover for
a whole hour without being dull for a minute. Then she heard Janet
calling her, and went running to the kitchen. There the great brass
pan was full of boiling fruit, deep crimson, and with the most
delicious smell. Janet gave her a saucer, and told her that with a
large spoon she might skim the white froth from the edge of the pan.
This was great fun to do; and then she was allowed to taste it, and it
was very good. Then Janet took the huge pan off the fire, and with a
cup began to fill up rows and rows of jars with the jam. Peggy sat on
the table and counted the jars, and was allowed, when they were full,
to take a damp cloth and wipe off all the drops of jam from the
edges, so that the jars were all clean and neat. When all this was
done it was quite late, and Janet said Peggy must go and have her
frock changed for the evening now.
“I’ve been so happy, Janet, I want to stay with you,” said Peggy,
flinging her arms round Janet’s neck as she said good-night.
CHAPTER VII.
THE ADVENTURE IN THE LANE.