INTRODUCTION TO

FLIP FLOPS

SYNCHRONOUS SEQUENTIAL CIRCUIT

Dwumfour Abdullai Aziz Slide 1

 LATCHES

q Latches and Flip Flops are the basic elements used to

store information in digital circuit.
q Both Latches and flip flops are circuit elements where the
output depends on the current inputs, previous input and
outputs.
q The peculiar feature about latches is that their outputs are
constantly affected by their inputs if the enable signal is
asserted, thus when the latches are enabled, their
content changes immediately when their inputs change.
q This behavior of the latch is referred to as asynchronous
q Latches are also level sensitive; thus, only triggered when
enable is high or low Slide 2
Dwumfour Abdullai Aziz
 FLIP FLOP

q Flip-flops, on the other hand, have their content change only

either at the rising or falling edge of the enable signal.
q This enable signal is usually the controlling clock signal.
q We can obtain Flip Flop from a gated latch by simply replacing
the enable control with a clock signal.
q The circuit only changes state when there is a rise or fall in the
edge of the clock signal.
q A Flip-Flop continuously checks its inputs and correspondingly
changes its output only at times determined by clocking signal.
It works based on clock pulses. This behavior is referred to as
synchronous
q Flip flops are however edge sensitive; thus, they are triggered by
the
Dwumfour rising
Abdullai Aziz or falling edge of the clock Slide 3
 CLOCK
q In digital circuit a clock is a signal that oscillates between high
and low state in a specific time interval
q This oscillation is useful in controlling the activities of digital
circuits.
q The clock is used to control the state of synchronous
sequential circuit.
q It is a global time signal which determines when circuit
elements change state or retain state.
q A clock generator is used to generate a clock, which is an
oscillator that provides a square wave output.
q The output of the clock is used to trigger or activate circuit
elements. The components of clock is presented below
Dwumfour Abdullai Aziz Slide 4
 +v Edge
-v Edge

+v Level -v Level

CLOCK DUTY CYCLE

Duty cycle(DC) is the proportion of time during which the clock
is high. It is usually 50%
Mathematically:
DC=ratio of number of times clock is high/total time

Dwumfour Abdullai Aziz Slide 5

 CLOCK TRIGGERING

Triggering is the process of making the circuit active.

Different triggering mechanisms exist to make circuit active.
Clock can trigger circuits in two ways:
q Level triggering
q Edge triggering

Level Triggering: In level triggering the circuit will become active

when the gating or clock pulse is on a particular level (high or low).
This level is decided by the designer.
We can have a negative level triggering in which the circuit is active
when the clock signal is low or a positive level triggering in which
the circuit is active when the clock signal is high.
Dwumfour Abdullai Aziz Slide 6
 CLOCK TRIGGERING

Edge triggering
q In edge triggering the circuit becomes active only at the
edge of the clock.
q Edge triggering may be negative or positive.
q If a circuit is positive edge triggered, the circuit will take
input at exactly the time in which the clock signal goes
from low to high(0 to 1)
q Similarly, negative edge triggering allows input to be
taken at exactly the time in which the clock signal goes
from high to low (1 to 0)

Dwumfour Abdullai Aziz Slide 7

 SYNCHRONOUS AND ASYNCHRONOUS CIRCUIT

q Sequential circuits can be synchronous or

asynchronous.
q Synchronous circuits change state only with the clock
signal whiles asynchronous circuit change state
whenever the input changes when enable is on.
q Latches are asynchronous whiles flip flops are
synchronous

Dwumfour Abdullai Aziz Slide 8

 TYPES OF FLIP-FLOPS

qS-R Flip Flop

qD Flip Flop
q J-K Flip-Flop
qT Flip-Flop
qMaster/slave S-R Flip-Flop
qMaster/slave J-K Flip-Flop

Dwumfour Abdullai Aziz Slide 9

 TYPES OF FLIP-FLOPS

S-R Flip Flop

This can be obtained from the gated S-R latch by
clocking the circuit with clock impulse

clk

BLOCK DIAGRAM OF SR FLIP FLOP

Dwumfour Abdullai Aziz Slide 10
NOR SR FLIP-FLOPS

BLOCK DIAGRAM OF SR FLIP FLOP

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NAND SR FLIP-FLOPS

BLOCK DIAGRAM OF SR FLIP FLOP

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SR FLIP-FLOPS TRUTH TABLE

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SR FLIP-FLOPS CHARACTERISTIC TABLE

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SR FLIP-FLOPS EXCITATION TABLE

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TIMING DIAGRAM FOR SR FLIP FLIP

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D-FLIP FLOP

BLOCK DIAGRAM
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D-FLIP FLOP

CIRCUIT DIAGRAM
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D-FLIP FLOP

Dwumfour Abdullai Aziz Slide 19

 D-FLIP FLOP

CHARACTERISTIC TABLE & CHARACTERISTIC EQUATION

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D-FLIP FLOP

EXCITATION TABLE
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TIMING DIAGRAM FOR D-FLIP FLOP

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J K FLIP FLOP

BLOCK DIAGRAM
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NAND J K FLIP FLOP

CIRCUIT DIAGRAM
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 J K FLIP FLOP

JK FLIP FLOP TRUTH TABLE

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J K FLIP FLOP CHARACTERISTIC TABLE

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TIMING DIAGRAM FOR J K FLIP FLOP

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SUMMARY OF FLIP FLIPS

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T - FLIP FLOP

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T - FLIP FLOP

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T - FLIP FLOP: CHARACTERISTIC TABLE

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T - FLIP FLOP: TIMING DIAGRAM

Dwumfour Abdullai Aziz Slide 34

 MASTER-SLAVE FLIP-FLOPS

² Master- Slave flip flop are the cascaded combination of two flip-
flops among which the first is designated as master flip-flop
while the next is called slave flip-flop
² The master flip-flop is triggered by the external clock pulse while
the slave is activated at its inversion
² If the master is positive edge-triggered, then the slave is
negative-edge triggered and vice-versa.
² Hence a master-slave flip-flop completes its operation only after
the appearance of one full clock pulse for which they are also
known as pulse-triggered flip-flops.
² Master-Slave Flip Flop is an attempt to handle the Racing around
condition in the JK Flip Flop.
² The Master –Slave Flip Flop is used to create the toggle situation
Dwumfour Abdullai Aziz Slide 35
MASTER-SLAVE FLIP-FLOPS

CIRCUIT DIAGRAM
Dwumfour Abdullai Aziz Slide 36
RECALL TRUTH TABLE FOR POSITIVE EDGE FLIP FLOP

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MASTER-SLAVE FLIP-FLOPS

BLOCK DIAGRAM
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J K MASTER-SLAVE FLIP FLOP

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 J K MASTER-SLAVE FLIP FLOP TIMING DIAGRAM

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INTRODUCTION TO FLIP
FLOP CONVERSION

Dwumfour Abdullai Aziz Slide 41

 FLIP FLOP CONVERSION

Conversion of flip-flops causes one type of flip-flop to behave like another

type of flip-flop.
In order to make one flip-flop mimic the behavior of another certain
additional circuitry and/or connections become necessary.

² SR Flip – flop to JK Flip – flop

² SR Flip – flop to D Flip – flop
² SR Flip – flop to T Flip – flop
² JK Flip – flop to SR Flip – flop
² JK Flip – flop to D Flip – flop
² JK Flip – flop to T Flip – flop
² D Flip – flop to SR Flip – flop
² D Flip – flop to JK Flip – flop

Dwumfour Abdullai Aziz Slide 42

 STEPS TO FLIP FLOP CONVERSION

We shall consider the following steps:

1. Identify the available and required flip flops
2. Make characteristic table of the required flip flop
3. Make excitation table of the available flip flop
4. Derive Boolean expression for available flip flop
5. Draw circuit diagram

Dwumfour Abdullai Aziz Slide 43

 SR FLIP FLOP TO JK FLIP FLOP CONVERSION

Available flip flop: SR

Required flip flop: JK
Characteristic table for JK flip flop
Excitation table for SR flip flop

Dwumfour Abdullai Aziz Slide 44

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SR TO JK FLIP FLOP

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 SR TO D FLIP FLOP

Available flip flop: SR

Desired flip flop: D
Characteristic table for D flip flop
Excitation table for SR flip flop

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Dwumfour Abdullai Aziz Slide 48
JK TO D FLIP FLOP

Dwumfour Abdullai Aziz Slide 49

JK TO D FLIP FLOP

Dwumfour Abdullai Aziz Slide 50

THEORY OF COMPUTATION/
AUTOMATA THEORY

Dwumfour Abdullai Aziz Slide 51