Lab 7 - 10 Manual

FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard University
Experiment # 7-A
OBJECTIVE:
To implement and perform verification of decoder and encoder, using ICs 7442 & 74147.
BACKGROUND THEORY:
a. DECODER:
A decoder is a multiple input; multiple output logic circuit, which converts coded input into
coded output where input and output codes are different. The input code generally has fewer
bits than the output code. Each input code word produces a different output code word i.e.
there is one to one mapping can be expressed in truth table. In the block diagram of decoder
circuit the encoded information is present as n input producing 2𝑛 possible outputs. 2𝑛 Output
values are from 0 through output 2𝑛 -1.
The 7442 decoder consists of eight inverters and ten four−input NAND gates. The inverters
are connected in pairs to make BCD input data available for decoding by the NAND gates.
Full decoding of valid input logic ensures that all outputs remain off for all invalid input
conditions.
Pinout: 7442
Hamdard Institute of Engineering & Technology, Hamdard University

Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
Hamdard University

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HARDWARE REQUIRED:
 Power supply with cables

 Breadboard
 IC 7442 (BCD to DEC Decoder)
 LEDs
 Logic Probe (optional)
PROCEDURE:
1. Make supply connections to the IC.

2. Now apply the BCD inputs to the decoder and check the corresponding decimal
outputs.
3. Complete the following Truth Table as per observations:
A0 A1 A2 A3 0 1 2 3 4 5 6 7 8 9
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
b. PRIORITY ENCODER:
An encoder performs a function that is the opposite of decoder. It receives one or more
signals in an encoded format and output a code that can be processed by another logic circuit.
One of the advantages of encoding data, or more often data addresses in computers, is that it
reduces the number of required bits to represent data or addresses. For example, if a memory
has 16 different locations, in order to access these 16 different locations, 16 lines (bits) are

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required if the addressing signals are in 1 out of n format. However, if we code the 16
different addresses into a binary format, then only 4 lines (bits) are required. Such a reduction
improves the speed of information processing in digital systems.
CIRCUIT DIAGRAM:
Decimal Inputs Outputs

1 2 3 4 5 6 7 8 9 D C B A
0 H H H H H H H H H H H H H
1 L H H H H H H H H H H H L
2 x L H H H H H H H H H L H
3 x x L H H H H H H H H L L
4 x x x L H H H H H H L H H
5 x x x x L H H H H H L H L
6 x x x x x L H H H H L L H
7 x x x x x x L H H H L L L
8 x x x x x x x L H L H H H
9 x x x x x x x x L L H H L
Truth Table for Encoder

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HARDWARE REQUIRED:
 Power supply with cables

 Breadboard
 IC 74147 (10-to-4 line Priority Encoder)
 LEDs
 Logic Probe (optional)
PROCEDURE:
1. Make supply connections to the IC.

2. Now apply the inputs to the encoder and check the corresponding outputs.
3. Complete the following Truth Table as per observations:
Inputs Outputs
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 A B C D
0 1 1 1 1 1 1 1 1 1
1 0 1 1 1 1 1 1 1 1
1 1 0 1 1 1 1 1 1 1
0 1 1 0 1 1 0 1 1 1
1 1 1 1 0 1 1 1 1 1
1 1 1 1 1 0 1 1 1 1
1 1 1 0 1 1 0 1 1 1
1 1 1 1 1 1 1 0 1 1
1 1 1 1 1 1 1 1 0 0
0 1 1 1 1 1 1 1 1 0
REVIEW QUESTIONS:
Q.1. Does the theoretical calculations confirmed by Experimental findings?
Q.2. Which digital system translates coded characters into a more useful form?
Q.3. Give an application of decoder:

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Q.4. What are code converters?
Q.5. What did you learn in this experiment?
LEARNING OUTCOMES:
Upon successful completion of the lab, students will be able to:
LO1: To learn about working principle of decoder and encoder.
LO2: To learn and understand the working of IC 7442 and IC 74147.
To be filled by Demonstrator/Lab Instructor
Date of Conduct
Last Date of Submission

Signature

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Experiment # 7-B
OBJECTIVES:
 To familiarize with the concept of sequential circuits.

 To study the SR Latch, Gated SR Flip Flop and D-type Flip Flop.
HARDWARE REQUIRED:
 Power Supply with cables
 Breadboard
 Logic gate ICs: 1) NOT Gate 2) AND Gate 3) NOR Gate
 LEDs
 Logic Probes (optional)
BACKGROUND:
Unlike Combinational Logic circuits that change state depending upon the actual signals being
applied to their inputs at that time, Sequential Logic circuits have some form of inherent
“Memory” built in to them as they are able to take into account their previous input state as well
as those actually present, a sort of “before” and “after” effect is involved with sequential logic
circuits. In other words, the output state of a “sequential logic circuit” is a function of the
following three states, the “present input”, the “past input” and/or the “past output”. Sequential
Logic circuits remember these conditions and stay fixed in their current state until the next clock
signal changes one of the states, giving sequential logic circuits “Memory”. Sequential logic
circuits are generally termed as two state or Bi-sable devices which can have their output or
outputs set in one of two basic states, a logic level “1” or a logic level “0” and will remain
“latched” (hence the name latch) indefinitely in this current state or condition until some other
input trigger pulse or signal is applied which will cause the bi-stable to change its state once
again.
Following is the Block Diagram of a Sequential logic. Note that a sequential logic is mainly a
combinational logic with memory element added to it:

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Fig 1: Basic Block Diagram of a Synchronous Sequential system
SR LATCH
The SR Latch, also known as SR flip-flop, can be considered as one of the most basic sequential
logic circuit possible. This simple flip-flop is basically a one-bit memory bi-stable device that
has two inputs, one which will “SET” the device (meaning the output = “1”), and is labeled ‘S’
and another which will “RESET” the device (meaning the output = “0”), labeled ‘R’. Then the
SR description stands for “Set-Reset”. The reset input resets the flip-flop back to its original state
with an output Q that will be either at a logic level “1” or logic “0” depending upon this set/reset
condition. The basic circuit symbol of an SR Latch is shown below:
Fig 2: Symbol of an SR Latch

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The basic SR Latch can be implemented by using either NAND Gates (NAND Latch) or NOR gates
(NOR Latch), both of them are shown as under:
NAND LATCH
To make single bit SR NAND Latch, connect together a pair of cross-coupled 2-input NAND
gates as shown, to form a Set-Reset Bi-stable also known as an active LOW SR NAND Gate
Latch, so that there is feedback from each output to one of the other NAND gate inputs. This
device consists of two inputs, one called the Set, ‘S’ and the other called the Reset, ‘R’ with two
corresponding outputs ‘Q’ and its inverse or complement Q’ as shown below.
Fig 3: NAND SR Latch
NOR LATCH
Similar as with NAND gates, it is also possible to construct simple one-bit SR Flip-flops using two
cross-coupled NOR gates connected in the same configuration. The circuit will work in a similar
way to the NAND gate circuit above, except that the inputs are active HIGH and the invalid
condition exists when both its inputs are at logic level “1”, and this is shown below

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Fig 4: NOR SR Latch
S R Q 𝑄 S R Q 𝑄
No
0 0 X X Invalid 0 0 X X
change
0 1 0 1 0 1 1 0
1 0 1 0 1 0 0 1
No
1 1 1 1 1 1 0 0 Invalid
change
GATED SR FLIP FLOP
It is sometimes desirable in sequential logic circuits to have a bi-stable SR flip-flop that only
changes state when certain conditions are met regardless of the condition of either the Set or
the Reset inputs. By connecting a 2-input AND gate in series with each input terminal of the SR
Flip-flop a Gated SR Flip-flop can be created. This extra conditional input is called an “Enable”
input and is given the prefix of “EN“. The addition of this input means that the output at Q only
changes state when it is HIGH and can therefore be used as a clock (CLK) input making it level-
sensitive. The circuit symbol with internal circuitry is shown below:

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Fig 5: Gated or Clocked SR Latch circuit symbol and gate level Circuit
When the Enable input “EN” is at logic level “0”, the outputs of the two AND gates are also at
logic level “0”, (AND Gate principles) regardless of the condition of the two inputs S and R,
latching the two outputs Q and Q’ into their last known state. When the enable input “EN”
changes to logic level “1”, the circuit responds as a normal SR bi-stable flip-flop with the two
AND gates becoming transparent to the Set and Reset signals. This additional enable input can
also be connected to a clock timing signal (CLK) adding clock synchronization to the flip-flop
creating what is sometimes called a “Clocked SR Flip-flop“. So a Gated Bi-stable SR Flip-flop
operates as a standard bi-stable latch but the outputs are only activated when logic “1” is
applied to its EN input and deactivated by a logic “0”.The Truth Table for Gated SR Flip Flop is as
follows:
S R Gate Q 𝑄`
Table 1: Truth Table for Gated SR NOR Flip Flop
 With ‘EN’ high (enable true), the signals can pass through the input gates to the
Encapsulated latch; all signal combinations except invalid condition then immediately
reproduce on the (Q’ ) output, i.e. the latch is transparent.
 With ‘EN’ low (enable false) the latch remains in the state it was left the last time ‘EN’
was high, i.e. the latch is closed (opaque).

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Major Drawback in an SR Flip Flop:
Both S & R inputs cannot be ‘0’ (NAND Latch) or‘1’ (NOR Latch) at the same time as it may cause
the latch to produce undesirable results at output.
D-TYPE FLIP FLOP

One way to eliminate the undesirable condition of the indeterminate state in SR Latch is to
ensure that the inputs ‘S’ & ‘R’ are never equal to ‘1’ at the same time. This is done in the D-
Latch (or D-type Flip Flop). This latch has only two inputs: ‘D (Data)’ and ‘C (Control)’. The ‘D’
input goes directly to the ‘S’ input and its complement is applied to the ‘R’ input. The resulting
Gate level circuit with circuit symbol is shown below:
Fig 7: Gated D-Type Flip Flop gate level Circuit and circuit symbol
The Truth Table for Gated SR Flip Flop is as follows:
D EN Q 𝑄
X 0 X X
1 1 1 0
0 1 0 1
Table 2: Truth Table for Gated D-Type Flip Flop

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Procedure:
1. Connect the circuit of SR Flip Flop as shown in figure 4 and verify the Truth Table.
2. Now connect the inverter between S and R inputs (D-type Flip Flop configuration) and verify
the truth table for D-type Flip Flop.
3. Based on your knowledge of D-Flip Flop, how can we develop a Toggle Flip Flop (T-Flip Flop)
from D-Flip Flop?
Lab Exercise:
1. If the S and R waveforms in Figure 1 are applied to the inputs of the latch in Figure b,
determine the waveform that will be observed on the Q output. Assume that Q is initially
LOW.
Fig 8
2. Develop the fout waveform for the circuit in Figure 2 when an 8 kHz square wave input is
applied to the clock input of ﬂip-ﬂop A.
Fig 9

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Conclusion:
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
_______________
Date of Conduct

Signature

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Experiment # 08
To Build A JK Master Slave Flip Flop and Verify its

Truth Table
Objectives:
To study the working of JK Type Flip Flop.
To study the error safe configuration of JK Flip Flop (Master-Slave configuration).
Apparatus:
 Power Supply with cable

 Breadboard
 7473 Dual JK Flip Flops LEDs
 Logic Probes (optional)
Background:
This simple JK flip Flop is the most widely used of all the flip-flop designs and is considered
to be a universal flip-flop circuit. The JK flip flop is basically a gated SR Flip-flop with the
addition of a clock input circuitry that prevents the illegal or invalid output condition that can
occur when both inputs S and R are equal to logic level “1”. Due to this additional clocked
input, a JK flip-flop has four possible input combinations:
i. Logic 1
ii. Logic 0
iii. No change
iv. Toggle
The circuit symbol, gate level circuit and Truth Table for JK Flip Flop is shown below:

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Fig 1: Circuit symbol and Gate Level circuit of JK Flip Flop
J K Q 𝑄
0 0 No
0 0
0 1 Change
Reset:
0 1 0 1
Q=0
Set:
1 0 1 0
Q=1
0 1
1 1 Toggle
1 0
Table 1: Truth table of JK Flip Flop
Although above circuit is an improvement on the clocked SR flip-flop it still suffers from timing
problems called “race” if the output ‘Q’ changes state before the timing pulse of the clock input
has time to go “OFF”. To avoid this the timing pulse period ( T ) must be kept as short as

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possible (high frequency). As this is sometimes not possible with modern TTL IC’s the much
improved Master-Slave JK Flip-flop was developed.
THE MASTER-SLAVE JK FLIP-FLOP
The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series
configuration with the slave having an inverted clock pulse. The outputs from Q and Q from the
“Slave” flip-flop are fed back to the inputs of the “Master” with the outputs of the “Master” flip
flop being connected to the two inputs of the “Slave” flip flop. This feedback configuration from
the slave’s output to the master’s input gives the characteristic toggle of the JK flip flop as
shown below:
Fig 2: Gate Level circuit of a Master Slave JK Flip Flop
The input signals J and K are connected to the gated “master” SR flip flop which “locks” the
input condition while the clock (CLK) input is “HIGH” at logic level “1”. As the clock input of
the “slave” flip flop is the inverse (complement) of the “master” clock input, the “slave” SR flip
flop does not toggle. The outputs from the “master” flip flop are only “seen” by the gated “slave”
flip flop when the clock input goes “LOW” to logic level “0”. Following is the working
mechanism:
 When the clock is “LOW”, the outputs from the “master” flip flop are latched and any
additional changes to its inputs are ignored. The gated “slave” flip flop now responds to
the state of its inputs passed over by the “master” section.
 Then on the “Low-to-High” transition of the clock pulse the inputs of the “master” flip
flop are fed through to the gated inputs of the “slave” flip flop and on the “High-to-Low”
transition the same inputs are reflected on the output of the “slave” making this type of
flip flop edge or pulse-triggered.
 Then, the circuit accepts input data when the clock signal is “HIGH”, and passes the data
to the output on the falling-edge of the clock signal. In other words, the Master-Slave JK
Flip flop is a “Synchronous” device as it only passes data with the timing of the clock
signal.

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PROCEDURE
1. The connection diagram of 7473 Dual JK Flip Flop is shown below:
Fig 3: Connection Diagram for 7473
2. 1J, 2J, 1K, and 2K: Pins for J and K inputs for flip flops 1 & 2 respectively.
3. 1CLK and 1CLK: Clearing Inputs for Flip Flops 1 & 2 respectively. Activated by
grounding pins where required.
4. 1CK, 2CK: Clock inputs for Flip Flops 1 & 2 respectively.
5. Q1, Q2, 1, and 2: Output pins for Flip Flops 1 & 2 respectively.
6. Connect the circuit as shown in figure 2 for Master Slave JK Flip Flop.
7. Now apply the inputs to the Flip Flop on specified pins (J1, J2, K1 & K2). Apply Clock
input on 1CLR and inverted clock on 2 CLR. Observe the output on Pins Q1 & 2.
8. Note the observations in the following Truth Table compare it with Table 1.
J K Q 𝑄
0 0
0 1
1 0
1 1
Table 2: Truth Table for a experimental findings

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Conclusion:
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
_________________
Date of Conduct
Signature

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Experiment # 09
Multiplexer & De-Multiplexer
OBJECTIVE:
 To study and observe the proper operation of a multiplexer.

 To study and observe the proper operation of 1-of-4 decoder (demultiplexer).
Equipment & Components required:
1. Power Supply
2. 74153 4-input multiplexer and 74139 1-of-4 decoder.
3. Bread Board
4. Probes
5. Connecting wires
THEORY
MULTIPLEXER
A multiplexer is an MSI (Medium-Scale Integration) circuit capable of selecting a single input

from a number of inputs and routing the selected input to a single output. The selected input is
determined by the appropriate input address lines. For instance, a multiplexer having 2 input
address is capable of selecting 1 of 4 possible inputs. The '153 is a dual 4-input multiplexer.
74153

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DEMULTIPLEXER
A logic decoder is a multiple-input MSI device with the capacity to select a single
output based on the input levels.1-of-4 decoder means 1 of 4 outputs may be
selected at a time.
74139
Preliminary work
1- With the help of datasheet write down the maximum supply current Icc
required for '153.
_________ mA.
2- With the help of datasheet write down the maximum supply current Icc
required for '139.
_________ mA.
PROCEDURE:
Part (A)
Step 1
The chip 74153 contains two 4-input multiplexers designated multiplexer 1 and
__
multiplexer 2. Working with multiplexer 1connect +Vcc=+5v dc to 1G and measure the
voltage levels at the output 1Y.

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1Y= ______.
Check to see that 1Y remains low if any input is connected to ground, +Vcc or
__
left unconnected, provided that 1G is connected to +Vcc.
__
The result should verify that holding 1G at +Vcc does indeed disable the chip.
Step 2
__
Connect 1G to ground and complete the following table.
Address __ Inputs Output
A B 1G
1C0 1C1 1C2 1C3 1Y
L L L L X X X
L L L H X X X
H L L X L X X
H L L X H X X
L H L X X L X
L H L X X H X
H H L X X X L
H H L X X X H
Where H = 1 = Vcc = +5V

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L = 0 = Gnd = 0V
X = either H or L or open
Step3
__
Connect 1G to Gnd and leave the 4 inputs 1C0, 1C1, 1C2 and 1C3 unconnected.
Complete the table given below.
Address __ Inputs Output
A B 1G
1Y
L L
Open
H L
L H
H H
Part (B)
Step1
The chip 74139 contains two 1-of-4 decoders designated decoder 1 and
decoder2.
__
Connect 1G to +Vcc and complete the table given

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Input output
B A 1Y0 1Y1 1Y2 1Y3
0 0
0 1
1 0
1 1
__
The result should verify that +Vcc applied to 1G does indeed disable the chip.
Step2
__
Now connect 1G to ground and complete the table given.
Input output
B A 1Y0 1Y1 1Y2 1Y3
0 0
0 1
1 0
1 1
The result should verify the truth table given on the 74139 data sheet.

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Step3
Complete the table given below.
Input output
B A 1Y0 1Y1 1Y2 1Y3
open 0
open 1
1 open
1 open
Date of Conduct
Signature

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Experiment # 10
555 Timer
OBJECTIVE:
 To study the A-stable mode of 555 Timer.

 To study the Mono-stable Mode of 555 Timer.
..
HARDWARE REQUIRED
1. Power Supply
2. LM555
3. Resistors.
4. Capacitor (1µF).
5. Bread board.
6. Jumper wires
BACKGROUND THEORY
Basically, the 555 timer is a highly stable integrated circuit capable of functioning as an accurate
time-delay generator and as a free running multi-vibrator. When used as an oscillator the
frequency and duty cycle are accurately controlled by only two external resistors and a capacitor.
• Pin 1. − Ground, The ground pin connects the 555 timer to the negative (0v) supply rail.
• Pin 2. − Trigger, The negative input to comparator No 1. A negative pulse on this pin "sets"
the internal Flip-flop when the voltage drops below 1/3Vcc causing the output to switch from a
"LOW" to "HIGH" state.
• Pin 3. − Output, The output pin can drive any TTL circuit and is capable of sourcing or sinking

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up to 200mA of current at an output voltage equal to approximately Vcc - 1.5V so small

speakers, LEDs or motors can be connected directly to the output.
• Pin 4. − Reset, This pin is used to "reset" the internal Flip-flop controlling the state of the
output, pin 3. This is an active-low input and is generally connected to a logic "1" level when not
used to prevent any unwanted resetting of the output.
• Pin 5. − Control Voltage, This pin controls the timing of the by overriding the 2/3Vcc level of
the voltage divider network. By applying a voltage to this pin the width of the output signal can
be varied independently of the RC timing network. When not used it is connected to ground. Via
10nF capacitor to eliminate any noise.
• Pin 6. − Threshold, The positive input to comparator No 2. This pin is used to reset the Flip-
flop when the voltage applied to it exceeds 2/3Vcc causing the output to switch from "HIGH" to
"LOW" state. This pin connects directly to the RC timing circuit.
• Pin 7. − Discharge, The discharge pin is connected directly to the Collector of an internal NPN
transistor which is used to "discharge" the timing capacitor to ground when the output at pin3
switches at "LOW"
• Pin 8. − Supply +Vcc, This is the power supply pin and for general purpose TTL 555 timers is
between 4.5V and 15V.
PRELIMINARY WORK
Standard 555 IC creates a significant 'glitch' on the supply when its output state
changes. A smoothing capacitor (e.g. 100µF) should be connected across the +Vs and
0V supply.

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ASTABLE MODE
An Astable circuit produces a 'square wave’ if R1<<R2 this is a digital waveform with
sharp transitions between low (0V) and high (+Vs). Note that the durations of the low and
high states may be different (if the relation R1<<R2 is false). The circuit is called an
Astable because it is not stable in any state: the output is continually changing between
'low' and 'high'.
For square wave if R1<<<R2 therefore R1 is negligible formula for frequency becomes
F= 1.44/ (2R2) * C = 0.72/ (R2*C)

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OBSERVATION
Astable Mode
C1 R2= 10kΩ R2= 27kΩ R2= 47kΩ

R1= 1kΩ R1= 10kΩ R1= 27kΩ
FMEAS= FMEAS= FMEAS=
1 uF
FCALC= FCALC= FCALC=
Monostable Mode
A Monostable circuit produces a single output pulse when triggered. It is called a monostable because it
is stable in just one state: 'output low'. The 'output high' state is temporary.
The duration of the pulse is called the time period (T) and this is determined by resistor R1 and capacitor
C1.
555 monostable output, a single pulse

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OBSERVATIONS
Monostable Mode
S.N C1 R1 Time Delay
TMEAS=
1.
TCALC=

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Q-1- Find the duty cycle of output (Astable mode) if R1=R2.
Date of Conduct
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FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY

Hamdard Institute of Engineering & Technology, Hamdard University

Hamdard Institute of Engineering & Technology, Hamdard University

 Power supply with cables

1. Make supply connections to the IC.

Hamdard Institute of Engineering & Technology, Hamdard University

Decimal Inputs Outputs

Truth Table for Encoder

Hamdard Institute of Engineering & Technology, Hamdard University

 Power supply with cables

1. Make supply connections to the IC.

Q.1. Does the theoretical calculations confirmed by Experimental findings?

Q.3. Give an application of decoder:

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Q.4. What are code converters?

Q.5. What did you learn in this experiment?

Upon successful completion of the lab, students will be able to:

LO1: To learn about working principle of decoder and encoder.

LO2: To learn and understand the working of IC 7442 and IC 74147.

To be filled by Demonstrator/Lab Instructor

Last Date of Submission

Hamdard Institute of Engineering & Technology, Hamdard University

 To familiarize with the concept of sequential circuits.

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Fig 1: Basic Block Diagram of a Synchronous Sequential system

Fig 2: Symbol of an SR Latch

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Fig 3: NAND SR Latch

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Fig 4: NOR SR Latch

GATED SR FLIP FLOP

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Table 1: Truth Table for Gated SR NOR Flip Flop

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Major Drawback in an SR Flip Flop:

D-TYPE FLIP FLOP

The Truth Table for Gated SR Flip Flop is as follows:

Table 2: Truth Table for Gated D-Type Flip Flop

Hamdard Institute of Engineering & Technology, Hamdard University

Hamdard Institute of Engineering & Technology, Hamdard University

To be filled by Demonstrator/Lab Instructor

Last Date of Submission

Hamdard Institute of Engineering & Technology, Hamdard University

To Build A JK Master Slave Flip Flop and Verify its

To study the working of JK Type Flip Flop.

To study the error safe configuration of JK Flip Flop (Master-Slave configuration).

 Power Supply with cable

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Fig 1: Circuit symbol and Gate Level circuit of JK Flip Flop

Table 1: Truth table of JK Flip Flop

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THE MASTER-SLAVE JK FLIP-FLOP

Fig 2: Gate Level circuit of a Master Slave JK Flip Flop

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1. The connection diagram of 7473 Dual JK Flip Flop is shown below:

Fig 3: Connection Diagram for 7473

Table 2: Truth Table for a experimental findings

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To be filled by Demonstrator/Lab Instructor

Last Date of Submission

Hamdard Institute of Engineering & Technology, Hamdard University

 To study and observe the proper operation of a multiplexer.

Equipment & Components required:

A multiplexer is an MSI (Medium-Scale Integration) circuit capable of selecting a single input