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Smart Computing and Informatics Proceedings of The First International Conference On SCI 2016 Volume 2 1st Edition Suresh Chandra Satapathy
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Smart Innovation, Systems and Technologies 78
Smart Computing
and Informatics
Proceedings of the First International
Conference on SCI 2016, Volume 2
123
Smart Innovation, Systems and Technologies
Volume 78
Series editors
Robert James Howlett, Bournemouth University and KES International,
Shoreham-by-sea, UK
e-mail: rjhowlett@kesinternational.org
The Smart Innovation, Systems and Technologies book series encompasses the
topics of knowledge, intelligence, innovation and sustainability. The aim of the
series is to make available a platform for the publication of books on all aspects of
single and multi-disciplinary research on these themes in order to make the latest
results available in a readily-accessible form. Volumes on interdisciplinary research
combining two or more of these areas is particularly sought.
The series covers systems and paradigms that employ knowledge and
intelligence in a broad sense. Its scope is systems having embedded knowledge
and intelligence, which may be applied to the solution of world problems in
industry, the environment and the community. It also focusses on the
knowledge-transfer methodologies and innovation strategies employed to make
this happen effectively. The combination of intelligent systems tools and a broad
range of applications introduces a need for a synergy of disciplines from science,
technology, business and the humanities. The series will include conference
proceedings, edited collections, monographs, handbooks, reference books, and
other relevant types of book in areas of science and technology where smart
systems and technologies can offer innovative solutions.
High quality content is an essential feature for all book proposals accepted for the
series. It is expected that editors of all accepted volumes will ensure that
contributions are subjected to an appropriate level of reviewing process and adhere
to KES quality principles.
Editors
Smart Computing
and Informatics
Proceedings of the First International
Conference on SCI 2016, Volume 2
123
Editors
Suresh Chandra Satapathy Swagatam Das
Department of Computer Science Electronics and Communication Sciences
Engineering Unit
PVP Siddhartha Institute of Technology Indian Statistical Institute
Vijayawada, Andhra Pradesh Kolkata, West Bengal
India India
Vikrant Bhateja
Department of Electronics and
Communication Engineering
Shri Ramswaroop Memorial Group
of Professional Colleges
Lucknow, Uttar Pradesh
India
The 1st International Conference on Smart Computing and Informatics (SCI) was
organized successfully with the excellent support of Department of CSE, ANITS,
Visakhapatnam, during March 3–4, 2017. The aim of this international conference
was to present a unified platform for advanced and multidisciplinary research
towards design of smart computing and information systems. The theme was on a
broader front focused on various innovation paradigms in system knowledge,
intelligence, and sustainability that is applied to provide realistic solution to varied
problems in society, environment, and industries. The scope was also extended
towards deployment of emerging computational and knowledge transfer approaches,
optimizing solutions in varied disciplines of science, technology, and healthcare.
The conference received many high-quality submissions in direct track and special
session tracks. After stringent quality check and review process only good papers
were accepted with an acceptance ratio of 0.38. Several eminent researchers and
academicians delivered talks addressing the participants in their respective field of
proficiency. Professor Ganapati Panda, IIT Bhubaneswar; Dr. R. Logeswaran,
Malaysia; Dr. C. Krishna Mohan, IIT Hyderabad; Dr. P.S. Grover, KIIT, Group of
Colleges, Gurgaon; Dr. A.K. Nayak, Hon. Secretary, Computer Society of India,
Director, Indian Institute of Business Management, Patna; Dr. Arunkumar
Thangavelu, VIT Vellore; Dr. Ramchandra V. Pujeri, Director, MIT College of
Engineering Pune; Dr. Nilanjan Dey, TICT Kolkota; and Dr. Prashant Kumar
Pattnaik, KIIT Bhubaneswar were the eminent speakers and guests on the
occasion.
We would like to express our appreciation to the members of the Program
Committee for their support and cooperation in this publication. We are also
thankful to the team from Springer for providing a meticulous service for the timely
production of this volume. Our heartfelt thanks to Chairman, ANITS, for the
support provided. Special thanks to all guests who have honored us with their
presence in the inaugural day of the conference. Our thanks are due to all special
session chairs, track managers and reviewers for their excellent support. Profound
thanks to Organizing Chair Prof. Pritee Parweker, ANITS, Visakhapatnam for
marvelous support. Sincere thanks to Honorary Chair, Dr. Lakhmi Jain, Australia,
v
vi Preface
for his valuable inputs and support during the conference. Last, but certainly not
least, our special thanks go to all the authors who submitted papers and all the
attendees for their contributions and fruitful discussions that made this conference a
great success.
vii
viii Organizing Committee
S. Pattanaik, India
Gerardo Beni, USA
K. Parsopoulos, Greece
Lingfeng Wang, China
Athanasios V. Vasilakos, Athens
Pei-Chann Chang, Taiwan
Chilukuri K. Mohan, USA
Saeid Nahavandi, Australia
Abbas Khosravi, Australia
Almoataz Youssef Abdelaziz, Egypt
K.T. Chaturvedi, India
M.K. Tiwari, India
Yuhui Shi, China
Dipankar Dasgupta, USA
Lakhmi Jain, Australia
X.Z. Gao, Finland
Juan Luis Fernandez Martinez, Spain
Oscar Castillo, Mexico
Heitor Silverio Lopes, Brazil
S.K. Udgata, India
Namrata Khemka, USA
G.K. Venayagamoorty, USA
Zong Woo Geem, USA
Ying Tan, China
S.G. Ponnambalam, Malaysia
Halina Kwasnicka, Poland
M.A. Abido, Saudi Arabia
Richa Singh, India
Manjaree Pandit, India
Hai Bin Duan, China
Delin Luo, China
V. Ravi, India
S. Basker, India
M. Rammohan, South Korea
Munesh Chandra Trivedi, ABES Engineering College, Ghaziabad, India
Alok Aggarwal, Professor and Director, JP Institute of Engineering and
Technology, Meerut, India
Dilip Kumar Sharma, Institute of Engineering and Technology, GLA University,
Mathura, India
K. Srujan Raju, CMR Technical Campus, Hyderabad, India
B.N. Biswal, BEC, Bhubaneswar, India
Sanjay Sengupta, CSIR, New Delhi, India
Naeem Hanoon, Malaysia
Cirag Arora, India
Steven Fernades, India
x Organizing Committee
xi
xii Contents
Big Data Analytics and Security: A Big Choice and Challenge for the
Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Gebremichael Girmay and D. Lalitha Bhaskari
A Prototype for Image Tamper Detection with Self-generated
Verification Code Using Gödelization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
P. Raja Mani and D. Lalitha Bhaskari
Suspicious URLs Filtering Using Optimal RT-PFL: A Novel Feature
Selection Based Web URL Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Kotoju Rajitha and Doddapaneni Vijayalakshmi
A Decision Tree Approach to Identify the Factors Affecting Reliability
for Component-Based System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Rajni Sehgal, Deepti Mehrotra and Manju Bala
A Novel Differential Evolution Test Case Optimisation (DETCO)
Technique for Branch Coverage Fault Detection . . . . . . . . . . . . . . . . . . . 245
Vibhor Gupta, Avneet Singh, Kapil Sharma and Himanshu Mittal
Comparative Analysis of Authentication and Access Control Protocols
Against Malicious Attacks in Wireless Sensor Networks . . . . . . . . . . . . . 255
Vikas Mittal, Sunil Gupta and Tanupriya Choudhury
Blockchain—Technology to Drive the Future . . . . . . . . . . . . . . . . . . . . . . 263
Shweta Bhardwaj and Manish Kaushik
Unified Payment Interface—A Way Ahead for Demonetization
in India . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Shweta Bhardwaj and Manish Kaushik
Evolutionary Algorithm Based Faults Optimization of Multi-modular
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Rana Majumdar, P.K. Kapur, Sunil K. Khatri and A.K. Shrivastava
Chip-Based Key Distribution Technique . . . . . . . . . . . . . . . . . . . . . . . . . . 293
K. Naveen Kumar and Manisha J. Nene
An Efficient Way to Find Frequent Patterns Using Graph Mining and
Network Analysis Techniques on United States Airports Network . . . . . 301
Anant Joshi, Abhay Bansal, A. Sai Sabitha and Tanupriya Choudhury
Terrorist Attacks Analysis Using Clustering Algorithm . . . . . . . . . . . . . . 317
Pranjal Gupta, A. Sai Sabitha, Tanupriya Choudhury and Abhay Bansal
A Review on VANET Routing Protocols and Wireless Standards . . . . . 329
Gagan Deep Singh, Ravi Tomar, Hanumat G. Sastry and Manish Prateek
Mechanical CAD Parts Recognition for Industrial Automation . . . . . . . 341
Jain Tushar, Meenu and H.K. Sardana
xiv Contents
xvii
xviii About the Editors
Abstract Present-day technology has reached a goal where an entire system can be
implemented on a single chip which is nothing but called system on chip (SOC). It
involves microcontrollers and various peripheral devices with each peripheral
device having its own intellectual property (IP) named as IP cores. Serial com-
munication is established between these IP cores using various protocols like
RS232, RS422 and UART etc. They perform point to point communication which
requires huge wiring connections, multiplexing of all the bus connections to deliver
the information to the IP Cores. To overcome this I2C protocol is developed by
Philips, which is a two line communication. Here only two pins, i.e., SCL and SDA
establish connection between various devices considering one as master and other
as slave (Eswari et al. in Implementation of I2C Master Bus Controller on FPGA,
2013) [1]. These two pins communicate using particular commands like start,
address, read/write, acknowledgement and stop commands. These commands show
a particular format in which data should transfer. Both 7-bit and 10-bit addressing
formats can be used, 10-bit addressing supports more addressing lines, i.e., 1024
compared to 127 addressing lines in 7-bit mode. The advantage in this protocol is it
has low wiring data transfer rate that can be improved using Ultra-Fast mode
(UFm) (Bandopadhyay in Designing with Xilinx FPGAs. Springer, Switzerland,
2017) [2]. Ultra-Fast mode is a unidirectional data transfer mode, i.e., only writing
data to an address can be done. In this paper they perform verification for the design
of an I2C protocol between a master and a slave using system Verilog and UVM in
the tool SimVision.
1 Introduction
SDA and SCL are the two bidirectional pins employed for data transfer and clock
generation [3, 4]. In this paper work, they employ a master and a slave between
these pins; perform data transfer for both 7-bit and 10-bit addressing in normal and
Ultra-Fast modes. A particular pattern is used to make this transfer, i.e., start bit,
address bit, r/w bit, acknowledgement bit, data bit, acknowledgment bit, stop bit.
Master and slave act as both transmitter and receiver [5]. In ultrahigh speed mode
only unidirectional transfer occurs, i.e., data can only be written but cannot be
retrieved; it has a data rate of 5 Mbits/s.
I2C has various applications like LCD, LED displays, temperature sensors,
system management bus (SMBUS), real time clocks, power supply controlling,
ADC and DAC, etc. Thus it is best employed for short distance communication
with less wiring and high data rates.
Slave is considered as the DUT with Master coding various test cases, i.e., Test
Bench. DUT is coded using behavioral Verilog HDL, Test bench environment is
created in S.V using UVM methodology, is tested for various test cases. S.V is
based on OOPs concepts which make it advantageous to Verilog. Test Bench
environment involves various subparts like transaction, generator, driver, envi-
ronment, test and top. Each part of test bench related to individual blocks is sep-
arately executed and all are finally linked in the top module. Virtual interface is
used for communication between DUT and Test Bench. It is represented in Fig. 1.
Results are simulated in SimVision tool, it is an integrated graphical debugging
environment within Cadence which supports signal and transaction level flows
across the design and the test bench. It is used for simulating for various languages
like VHDL, Verilog, and System Verilog, etc. It is advantageous, i.e., DUT and
Test Bench both can be analyzed anytime during the verification time.
2 Protocol Description
I2C has two pins SDA and SCL, i.e., Serial Data transfer and Serial Clock which are
bidirectional. Devices connected to these pins are Master and Slave, as shown in
Fig. 2.
High Level Verification of I2C Protocol … 3
Fig. 2 Signal transmission between master and slave using the two pins SCL (serial clock) and
SDA (serial data)
SDA, Serial Data, acts as both input and output, on this pin our data is transmitted
and received. When Master transmits the data slave receives it and acknowledges,
similarly when slave transmits the data master receives and acknowledges after
proper reception. For this reason it is a bidirectional pin.
SCL, Serial Clock, is generated by the Master; on this pin the clock signal is
transmitted [6]. The signal description is as follows (Table 1).
Block diagram for the I2C represents the serial flow of data and clock. There is a
particular pattern the protocol follows for transmitting data. Data transmission gets
initiated with a start command ends with a stop command, as in [7].
In standard mode it is represented as (Fig. 3):
S (Start) It represents start command and is generated only by the master. It
occurs when SCL is high and SDA makes a high to low transition.
Slave address It is a 7-bit slave address, which is the address of the slave to which
the corresponding transaction has to be done.
Read/Write If a write action needs to be done, then the SDA bit value to be
assigned ‘0’. If a read action needs to be done SDA bit value will be
assigned ‘1’.
ACK The one which is being addressed needs to acknowledge that it is
ready for data transmission, i.e., write or read by making SDA bit
Fig. 3 Block diagram flow between master and slave with a specific data flow pattern in standard
mode
‘0’. If SDA bit is ‘1’ it means the one addressed is not ready for
transmission, data does not get transmitted.
Wait When the slave is busy, it makes SCL low so that it remains in a
wait state without loss of data until slave gets free.
Data After receiving the acknowledgment signal the one being addressed
transmits 8-bit data to the slave address or reads data from the slave
address based on the condition specified.
ACK/ACK If the one being addressed is ready for another data transmission it
sends an ACK (active low), i.e., ‘0’ else it generates an ACK i.e.,
‘1’.
P (Stop) It represents a stop command and is generated only by the master. It
occurs when SCL is high and SDA makes a high to low transition.
The data transmission with the slave gets terminated when this
command is generated.
Fig. 4 Block diagram representing the data flow between Master and Slave in a specified pattern
in ultra-fast mode
3 Timing Diagram
It represents basic format of the data flow with various commands. Start command
which starts transmission, slave address to which transmission has to be done, write
mode set to write data, acknowledgement from the slave that it will accept the data,
data is written to particular address, not acknowledgment indicating slave can’t
accept any more data, repeated start to perform read action which is similar to start,
slave address from which data to be read, read mode enabling by setting bit to ‘1’,
acknowledgment from slave that it is free to send data, data read from the particular
High Level Verification of I2C Protocol … 7
Fig. 5 Timing analysis for write and read actions in standard mode
4 Results
In standard mode and ultra-fast mode the results acquired for 7-bit and 10-bit
addressing are as follows.
Standard mode. In this mode it has 7-bit and 10-bit addressing ways; both write
and read operations are performed, as in [4].
Firstly 7-bit addressing has 128 ways of addressing; here write and read oper-
ations occur as follows (Figs. 6 and 7).
Now in 10-bit addressing it has two addresses, the first 7-bit has a fixed pattern
of 7’b11110xx and the second address is a byte. The last two bits of the first address
and the second byte build up our 10-bit address. Advantage of having 10-bit
Fig. 6 Writing data into the slave using 7-bit addressing in standard mode. (01) Start bit is set,
(02–08) slave address is mentioned, (09) ‘0’ mentioning write action, (0A) acknowledgment bit as
‘0’ i.e., slave is ready to accept data, (0B–12) data written to slave, (13) acknowledgment from
slave to make repeated start i.e., performing read action from the slave
Fig. 7 Reading data from the slave using 7-bit addressing in standard mode. (01) Start bit is set,
(02–08) slave address is mentioned, (09) ‘1’ mentioning read action, (0A) acknowledgment bit as
‘0’ i.e., slave is ready to accept data, (0A–11) data read from slave, (12) acknowledgment from
slave to make repeated start
8 L.M. Kappaganthu et al.
addressing is that if it has 1024 address locations instead of just 128 locations where
address collisions may occur, as in [6, 7]. Write and read operations here are as
follows (Figs. 8 and 9).
Ultra-Fast mode. In Ultra-Fast mode only write operation is done as the signals
are unidirectional. ACK has no significance and is controlled by the master to make
it compatible with I2C protocol. Remaining is same as per mentioned in the stan-
dard mode, as in [6, 9].
7-bit and 10-bit write operations occur as follows (Figs. 10 and 11).
Fig. 8 Writing data into the slave using 10-bit addressing in Standard mode. (01) Start bit is set,
(02–08) first part of slave address is mentioned, (09) ‘0’ mentioning write action, (0A)
acknowledgment bit as ‘0’ i.e., slave is ready to accept data, (0B–12) 2nd byte address of the slave,
(13) acknowledgment bit as ‘0’ i.e., slave is ready to accept data, (14–1B) data written to slave,
(1C) acknowledgment from slave to make repeated start i.e., performing read action from the slave
Fig. 9 Reading data from the slave using 10-bit addressing in Standard mode. (01) Start bit is set,
(02–08) first part of slave address is mentioned, (09) ‘0’ mentioning write action, (0A)
acknowledgment bit as ‘0’ i.e., slave is ready to accept data, (0B–12) 2nd byte address of the slave,
(13) acknowledgment bit as ‘0’ i.e., slave is ready to send data to the master, (14–1B) data read
from the slave, (1C) acknowledgment from slave to make repeated start
Fig. 10 Writing data into the slave using 7-bit addressing in UFm mode. (01) Start bit is set, (02–
08) slave address is mentioned, (09) ‘0’ mentioning write action, (0A) acknowledgment bit as ‘1’
(ack signal is not required in UFm mode but to retain protocol bit pattern the ack bit is mentioned),
(0B–12) data written to slave, (13) acknowledgment from slave which is always set as high
Fig. 11 Writing data into the slave using 10-bit addressing in UFm mode. (01) Start bit is set,
(02–08) first part of slave address is mentioned, (09) ‘0’ mentioning write action, (0A)
acknowledgment bit as ‘0’ i.e., slave is ready to accept data, (0B–12) 2nd byte address of the slave,
(13) acknowledgment bit as ‘0’ i.e., slave is ready to accept data, (14–1B) data written to slave,
(1C) acknowledgment bit as ‘1’ indicating stop action
High Level Verification of I2C Protocol … 9
5 Conclusion
6 Future Work
Present work can be extended by including clock stretching case in which slave
controls the clock when it is busy to handle new information from the master. The
same concept can be implemented on an FPGA tool.
Acknowledgements Heartfelt thanks to the SEMICON team [CYIENT Ltd, Hyderabad] for
giving me attention and their valuable time at peak times. My special gratitude and love to my
parents.
References
1. Bollam Eswari, N. Ponmagal, K. Preethi, S.G. Sreejeesh.: Implementation of I2C Master Bus
Controller on FPGA. International conference on Communication and Signal Processing
(2013).
2. Saikat Bandopadhyay: Simulation. In: Sanjay Churiwala Nagel. (eds.) Designing with Xilinx
FPGAs. LNCS, pp. 127–140. Springer, Switzerland (2017)
3. Chris Spear.: System Verilog for verification: A Guide to Learning the test bench for Language
Features. Springer, Colorado (2012)
4. I2C-bus specification and user manual Rev. 6 — 4 Apr. 2014, http://www.nxp.com
5. S. Palnitkar.: Verilog HDL: A Guide to Digital Design and Synthesis. Upper Saddle River,
New Jersey, Prentice Hall (1996)
6. Rashinkar, Prakash, Paterson, Peter, Singh, Leena.: System-on-a-Chip Verification:
Methodology and techniques. Norwell, MA, USA (2000)
7. Zheng-wei HU.: I2C Protocol Design for Reusability. In: Third International Symposium on
Information Processing, North China Electric Power University, Baoding, China (2010)
8. J. W. Bruce.: Personal Digital Assistant (PDA) Based I2C Bus Analysis. In: IEEE Transactions
on Consumer Electronics, Vol. 49. pp. 83–89. No. 4, China (2003)
9. Peter Corcoran: Two Wires and 30 Years. In: U.S. Patent 4 689 750, pp. 30–36, (2013)
Pre-informed Level Set for Flower Image
Segmentation
Abstract This work proposes a pre-informed Chan–Vese (CV) based level sets
algorithm. Pre-information includes objects colour, texture and shape fused fea-
tures. The aim is to use this algorithm to segment flower images and extract
meaningful features that will help is classification of floral content. Shape
pre-information modelling is handled manually using advance image processing
tools. Local binary patterns (LBP) features makeup texture pre-information and
RGB colour channels of the object provide colour pre-information. All pre-defined
object information is fused together to for high dimension subspace defining object
characteristics. Testing of the algorithm on flower images datasets shows a jump in
information content in the resulting segmentation output compared to other models
in the category. Segmentation of flowers is important for recognition, classification
and quality assessment to ever-increasing volumes in floral markets.
1 Introduction
Hän nauroi.
"En minä…"
"Hän tulee kohta… kohta… jouduhan… tule, tule… niin kyllä, olen
häijy, irstas, mutta sille nyt en voi enää mitään… joudu, joudu… nyt
on jo myöhäistä."
"Oli kuin olisi ollut ilmestys, joka oli ihan minua varten tarkoitettu",
toistin itsekseni.
Mutta minä huomasin, että hän vallan hyvin ymmärsi, mitä oli
tapahtunut. Hän kääntyi äkkiä ja katosi työhuoneeseen.
*****
Vähät minä enää Ljudmilan kanssa puhuin, mutta hän oli niinkuin
ei mitään olisi tapahtunutkaan.
*****
Usein olen päätellyt, että hän yhä eläisi ja taistelisi, jos vaan
aikoinaan olisi löytänyt tuen. Mutta harva meistä se on joka sellaisen
tuen löytää… näemmehän jokainen päivä ympärillämme ihmisten
lankeavan… toinen vetää alinomaa mukaansa toisen… Mieltäni
liikutti varsinkin tuo heikkouden ja ainaisen innostuksen
yhteensovitus hänen luonteessaan sekä ne ankarat vaatimukset,
jotka hän vaati itseltään, ja hänen tahtonsa tehdä oikein. Hän tiesi,
että se oli hänen elämänsä korkein tehtävä, pyrkien alinomaa
voittamaan tuon eläimellisen, joka saattoi hänelle ja meille kaikille
saattaa tuskaa. Mutta onneton nääntyi taistelussa.
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