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Uart New
Uart New
A
MINOR PROJECT REPORT
SUBMITTED IN PARTIAL FULFILMENT OF
THE REQUIREMENTS FOR THE AWARD OF THE DEGREE
OF
BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
TO
UNDER
THE SUPERVISION OF
Dr.Manish Rai
Professor
Electronics And Communication Engineering
2023
UNDERTAKING
Date:
Place: Bareilly
ii
CERTIFICATE FROM THE GUIDE
This is to certify that project work embodied in this report entitled “DESIGN &
IMPLEMENTATION OF UNIVERSAL ASYNCHRONOUS RECEIVER
TRANSMITTER USING VERILOG”submitted to MJP Rohilkhand University
Bareilly Uttar Pradesh, for the award of the degree of B.Tech (Electronics and
communication Engineering) has been carried out by Naman Soni, Titiksha
Sharma and Sonpal under my supervision.
Date :-
iii
ACKNOWLEDGEMENT
We would like to take this opportunity to express our deep sense of gratitude,
appreciation and indebtedness express Dr. Manish Rai for his perseverance,
excellence guidance, constant encouragement and cooperation which led to the
completion of this project. Without his constant appraisal and effort, this task
would never been successful. Dr.Manish Rai has always guided us with his
helping hands.He provided us with all necessary resources and guided us in
many of important concept used in this project .We would also like to thanks
our project coordinator Dr. Janak Kapoor sir and all respected Institute members
of Electronics & Communication Department. We wish to thank fellow
colleagues and family for their guidance and ideas which gave us
encouragement and hope whenever we had a problem in our project.
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CONTENTS
Undertaking
Certificate from guide
Acknowledgement
Introduction
Basics of serial communication
Historical evolution of UART
Synchronous and asynchronous transmission
Applications
UART Architecture
Functionality of transmitter and receiver circuits
Transmitter Circuit Functionality
Receiver Circuit Functionality
Data Transmission
Steps of UART Transmission
Introduction of VLSI
Operators used in Verilog
Conclusion
Future Work
REFERENCES
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CHAPTER 1: Introduction to UART
1.1Introduction
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In both types of serial communication, the fundamental components include a
transmitter, which formats and sends data, and a receiver, which captures and
processes the data. The baud rate, expressed in bits per second (bps), determines
the speed of data transmission and must be consistent between communicating
devices.
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As technology advanced, UART implementations evolved to support higher
data transfer rates and accommodate the increasing complexity of electronic
systems. The integration of UART into communication protocols, such as RS-
232, further expanded its utility, making it a standard for inter-device
communication.
Synchronous Transmission:
Asynchronous Transmission:
Asynchronous transmission, on the other hand, does not rely on a shared clock
signal. Instead, it uses start and stop bits to frame each unit of data (usually a
byte). These bits help the receiver identify the beginning and end of each byte,
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allowing for communication between devices with slightly different clock
speeds. UART (Universal Asynchronous Receiver/Transmitter) is a common
example of asynchronous transmission.
Applications:
Synchronous Transmission:
Asynchronous Transmission:
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CHAPTER 2: UART Architecture
2.1UART Architecture
Transmitter:
The UART transmitter is responsible for formatting and sending data. It takes
parallel data from the data bus and converts it into a serial format. The
transmitter typically includes a shift register, which serializes the parallel data,
and a control logic block to manage the transmission process.
Receiver:
The UART receiver, located on the receiving device, performs the reverse
process. It takes the incoming serial data, converts it into parallel form, and
makes it available on the data bus. The receiver includes a shift register and
control logic to manage the reception process.
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Baud Rate Generator:
The baud rate generator determines the speed of data transmission by generating
the clock pulses (baud rate) required for the serial communication. Both the
transmitter and receiver must be configured with the same baud rate for
successful communication.
First In, First Out (FIFO) buffers may be included in the UART architecture to
store incoming and outgoing data temporarily. This helps manage data flow
between the UART and the rest of the system, preventing data loss during
transmission or reception.
Control Logic:
The control logic oversees the overall operation of the UART. It manages the
flow of data, controls the start and stop bits, and coordinates the handshaking
process if flow control is employed. It ensures synchronization between the
transmitting and receiving devices.
Registers:
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Interrupts (Optional):
The transmitter receives parallel data from the system's data bus. It is
responsible for formatting this parallel data into a serial format for transmission.
This includes converting the data into a bitstream and appending start and stop
bits.
The transmitter adds start and stop bits to each data byte. The start bit signals
the beginning of a data byte, and the stop bit(s) indicate the end. These bits help
the receiver identify the boundaries of the transmitted data and synchronize with
the incoming bitstream.
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Parallel-to-Serial Conversion:
The parallel data is then shifted out serially, typically using a shift register. The
shift register serializes the data, sending it bit by bit over the communication
line.
The transmitter circuit generates clock pulses, determining the baud rate at
which the serial data is transmitted. Both the transmitter and receiver must
operate at the same baud rate for successful communication.
Control Logic:
The control logic oversees the entire transmission process, ensuring proper
timing, managing the start and stop bits, and coordinating with other
components like FIFO buffers if present.
The receiver circuit receives the serial data and performs the reverse process of
the transmitter. It converts the incoming serial bitstream into parallel data.
The receiver identifies the start and stop bits to determine the boundaries of
each data byte. It synchronizes with the incoming data based on these framing
bits.
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Parallel Data Output:
Once a complete byte is received, the parallel data is made available on the
system's data bus for further processing by the connected microcontroller or
other components.
The receiver's baud rate generator ensures that it operates at the same baud rate
as the transmitter, maintaining synchronization during data reception.
Control Logic:
Similar to the transmitter, the receiver's control logic oversees the reception
process, managing the flow of incoming data, handling start and stop bits, and
coordinating with other components.
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CHAPTER 3: UART Communication Protocol
The transmitting UART is connected to a controlling data bus that sends data in
a parallel form. From this, the data will now be transmitted on the transmission
line (wire) serially, bit by bit, to the receiving UART. This, in turn, will convert
the serial data into parallel for the receiving device.
The UART lines serve as the communication medium to transmit and receive
one data to another. Take note that a UART device has a transmit and receive
pin dedicated for either transmitting or receiving.
For UART and most serial communications, the baud rate needs to be set the
same on both the transmitting and receiving device. The baud rate is the rate at
which information is transferred to a communication channel. In the serial port
context, the set baud rate will serve as the maximum number of bits per second
to be transferred.
Data Transmission
In UART, the mode of transmission is in the form of a packet. The piece that
connects the transmitter and receiver includes the creation of serial packets and
controls those physical hardware lines. A packet consists of a start bit, data
frame, a parity bit, and stop bits.
Start Bit
The UART data transmission line is normally held at a high voltage level when
it’s not transmitting data. To start the transfer of data, the transmitting UART
pulls the transmission line from high to low for one (1) clock cycle. When the
receiving UART detects the high to low voltage transition, it begins reading the
bits in the data frame at the frequency of the baud rate.
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Data Frame
The data frame contains the actual data being transferred. It can be five (5) bits
up to eight (8) bits long if a parity bit is used. If no parity bit is used, the data
frame can be nine (9) bits long. In most cases, the data is sent with the least
significant bit first
Parity
Parity describes the evenness or oddness of a number. The parity bit is a way for
the receiving UART to tell if any data has changed during transmission. Bits
can be changed by electromagnetic radiation, mismatched baud rates, or long-
distance data transfers.
After the receiving UART reads the data frame, it counts the number of bits
with a value of 1 and checks if the total is an even or odd number. If the parity
bit is a 0 (even parity), the 1 or logic-high bit in the data frame should total to an
even number. If the parity bit is a 1 (odd parity), the 1 bit or logic highs in the
data frame should total to an odd number.
When the parity bit matches the data, the UART knows that the transmission
was free of errors. But if the parity bit is a 0, and the total is odd, or the parity
bit is a 1, and the total is even, the UART knows that bits in the data frame have
changed.
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Stop Bits
To signal the end of the data packet, the sending UART drives the data
transmission line from a low voltage to a high voltage for one (1) to two (2)
bit(s) duration.
1. The transmitting UART receives data in parallel from the data bus:
2. The transmitting UART adds the start bit, parity bit, and the stop bit(s) to the
data frame.
Fig:3.2 Tx UART
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3. The entire packet is sent serially from the transmitting UART to the receiving
UART. The receiving UART samples the data line at the pre-configured baud
rate:
4. The receiving UART discards the start bit, parity bit, and stop bit from the
data frame:
Fig:3.4 Rx UART
5. The receiving UART converts the serial data back into parallel and transfers
it to the data bus on the receiving end:
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SIMULATION WAVEFORM:
CHAPTER 4: BASICS OF VERILOG
4.1Introduction to VLSI
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VLSI technology has been a driving force behind the rapid advancement of the
electronics industry, enabling the creation of more powerful and energy-
efficient devices. The field continues to evolve as researchers and engineers
explore new ways to push the limits of semiconductor technology.\
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1. Arithmetic Operators:
Arithmetic operators are used to perform basic math calculations. They
perform a specific operation on two numeric values and return a single
numeric value.
a+b + Add
a–b – Subtract
a*b * Multiply
a/b / Divide
2. Logical Operators:
Logical operators perform a logical operation on the logical value of the
operands and tell you whether it is true or false, i.e., it returns a boolean
value.
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3. Reduction Operators:
This operand is useful for converting a multi-bit vector into a single bit
scalar value. It performs bit by bit logical operation on the vector operand
and returns a boolean value.
For example,
Performs bitwise OR
|A |
operation on A
Performs bitwise XOR
^A ^
operation on A
4. Relational operators:
If we want to check the relation between the given operands, then we use
relational operators. Relational operators test the relation between operands and
return a 1 or 0.
5.1Conclusion:
Some general trends and potential future directions for UART technology:
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4. Advanced Error Handling and Correction: Future UART
implementations may include more sophisticated error detection and
correction mechanisms. This could improve the reliability of data
transfer, especially in environments with high noise or interference.
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REFERENCES:
[1] https://www.watelectronics.com/basics-of-uart-communication
[6] https://www.researchgate.net/publication/308988751_Universal_Asynchr
onous_Receiver_and_Transmitter_UART
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