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SystemVerilog
Assertions and
Functional Coverage
Guide to Language, Methodology and
Applications
Second Edition
SystemVerilog Assertions and
Functional Coverage
Ashok B. Mehta

SystemVerilog Assertions
and Functional Coverage
Guide to Language, Methodology
and Applications
Second Edition

123
Ashok B. Mehta
Los Gatos, CA
USA

Additional material to this book can be downloaded from http://extras.springer.com.

ISBN 978-3-319-30538-7 ISBN 978-3-319-30539-4 (eBook)

DOI 10.1007/978-3-319-30539-4

Library of Congress Control Number: 2016932750

© Springer International Publishing Switzerland 2014, 2016

This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part
of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations,
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The use of general descriptive names, registered names, trademarks, service marks, etc. in this
publication does not imply, even in the absence of a specific statement, that such names are exempt from
the relevant protective laws and regulations and therefore free for general use.
The publisher, the authors and the editors are safe to assume that the advice and information in this
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The registered company is Springer International Publishing AG Switzerland
To
My dear wife Ashraf Zahedi
and
My dear parents Rukshamani
and Biren Mehta
Foreword

Louis H. Sullivan, an American architect, considered the father of the modern

skyscraper, and mentor to Frank Lloyd Wright, coined the phrase ‘form follows
function.’ The actual quote is ‘form ever follows function’ which is a bit more
poetic and assertive than the version that has found its way into the common
vernacular. He wrote those words in an article written for Lippincott’s Magazine
#57 published in March 1896. Here is the passage in that article that contains the
famous quote:
“Whether it be the sweeping eagle in his light or the open apple-blossom, then toiling work
horse, the blithe swan, the branching oak, the winding stream at its base, the drifting clouds—
over all the coursing sun, form ever follows function, and this is the law. Where function does
not change, form does not change. The granite rocks, the ever brooding hills, remain for ages;
the lightning lives, comes into shape, and dies, in a twinkling.

It is the pervading law of all things organic and inorganic, of all things physical and
metaphysical, of all things human and all things superhuman—of all true manifestations
of the head, of the heart, of the soul—that the life is recognizable in its expression, that
form ever follows function. This is the law.”

Earlier in the article, Sullivan foreshadows his thought with this passage:
“All things in nature have a shape, that is to say, a form, an outward semblance, that tells us
what they are, that distinguishes them from ourselves and from each other.”

The precise meaning of this pithy phrase has been debated in art and architecture
circles since Sullivan’s article was first published. However, it is widely accepted to
mean that the form of something—its shape, color, size, etc.—is related to what it
does. Water flows, rocks sit, and birds fly.
In his book ‘The Design of Everyday Things,’ (Basic Books 1988) Don Norman
discusses a similar concept, the notion of affordances. Norman defines the term as
‘… the perceived and actual properties of the thing, primarily those fundamental
properties that determine just how the thing could possibly be used.’ He cites some
examples: ‘A chair affords (“is for”) support and, therefore, affords sitting. A chair

vii
viii Foreword

can also be carried. Glass is for seeing through, and for breaking. Wood is normally
used for solidity, opacity, support or carving.’
Norman’s idea turns Sullivan’s upside down. He is saying function follows
form. The shape, color, size, etc., of an object affects what it does. Nonetheless,
both men would likely agree that form and function, whichever drives the other, are
inextricably linked.
Software designers have the luxury of choosing the form to fit the function. They
are not as constrained by the laws of physics as say, a cabinetmaker. The cabi-
netmaker must choose materials that will not only look nice, but will withstand the
weight of books or dishes or whatever is to be placed on the shelves. Software
designers have some constraints with regard to memory space and processing time,
but beyond that they have a lot of freedom to build whatever comes to mind.
Sullivan referred to ‘all things physical and metaphysical.’ Without much of a
stretch, we can interpret that to include software, a most abstract human creation.
The form of a piece of software is linked to its function. The complex software that
verification engineers build, called a testbench, must be designed before it can be
built. The verification engineer, like an architect, must determine the form of his
creation.
The architecture space is wide open. Computer code, while much more abstract
than say, a staircase or a door handle on a car, has a form and a function. The form
of computer code is the set of syntactic elements strung together in a program. The
function is what the program does when executed, often referred to as its semantics.
A verification engineer is typically presented a set of requirements, often as a
design specification, and asked to build a testbench that meets these requirements.
Because of the tremendous flexibility afforded by the software medium, he must
choose the form carefully to ensure that not only meets the requirements, but is easy
to use, reusable, and robust. He must choose a form that fits the function.
Often an assertion is just the right thing to capture the essence of some part of a
design. The form of an assertion is short sequence of text that can be inserted easily
without disrupting the design. With their compact syntax and concise semantics,
assertions can be used to check low-level invariants, protocols, or end-to-end
behavior.
The function of an assertion, in a simulation context, is to assert that something
is always (or never) the case. It ensures that invariants are indeed invariant.
Assertions can operate as checkers or as coverpoints. The fact that they can be
included in-line in RTL code or in separate checkers and that they can be short or
long for simple or complex checking makes them invaluable in any testbench.
The wise verification engineer uses all the tools as his disposal to create an
effective and easy-to-use testbench. He will consider the function of the testbench
and devise a form that suits the required function. Assertions are an important part
of any testbench.
Ashok Mehta has written a book that makes assertions accessible. His approach is
very pragmatic, choosing to show you how to build and use assertions rather than
engage in a lot of theoretical discussion. Not that theoretical discussion is irrelevant—
it is useful to understand the theoretical underpinnings of any technology. However,
Foreword ix

there are many other books on that topic. This book fills a gap for practicing engineers
where before no text provided the how-tos of building and using assertions in a
real-world context.
Ashok opens up the world of assertions to verification engineers who may have
thought them too opaque to consider using in a real testbench. He does an espe-
cially nice job of deconstructing assertions to show how they work and how to write
them. Through detailed examples, he shows all the pieces that go into creating
assertions of different kinds, and how they fit together. Ashok completes the picture
by demonstrating how assertions and coverage fit together.
Part of the book is devoted to functional coverage. He deconstructs the some-
times awkward SystemVerilog syntax of covergoups and coverpoints. Like he has
with assertions, he takes the mystery out of building a high-quality coverage model.
With the mysteries of assertions unmasked, you can now include them in your
personal vocabulary of testbench forms. This will enable you to create testbenches
with more sophisticated function.

February 2013 Mark Glasser

Preface to the Second Edition

The first edition of this book was well received, and the readers provided many a
good suggestion on further elaboration of language semantics. Readers also pointed
out some errata on the language syntax. I am greatly indebted to the readers and
colleagues for their input and support. In addition, the IEEE 1800-2012 LRM came
along. Many features of the 2012 LRM were missing in the first edition, since the
LRM was not ready yet. This edition incorporates the errata/suggestions from
readers as well as the IEEE 1800-2012 feature set. Among many, features such as
‘checkers,’ ‘let declarations,’ past and future global clock sampled value functions,
strong and weak properties, abort properties, and ‘.triggered’ end point detection
method are included. Furthermore, this edition adds many more examples and adds
further clarification of the semantic nuances of the language.
Pleasant reading.

xi
Preface to the First Edition

Having been an end user of EDA tools for over 20 years, I have seen that many new
technologies stay on wayside because either the engineers do not have time to learn
these new technologies/languages or the available material is too complex to digest.
A few years back I decided to tackle this problem by creating a very practical,
application-oriented down-to-earth SystemVerilog Assertions (SVA) and functional
coverage (FC) class for professional engineers. The class was well received, and I
received a lot of feedback on making the class even more useful. That culminated in
over 500 slides of class material just on SVA and FC. Many suggested that I had
collected enough material for a book. That is how I ended up on this project with
the same goal that the reader should understand the concept clearly in an easy and
intuitive manner and be able to apply the concepts to real-life applications right
away.
The style of the book is such that the concepts are clarified directly in a slide
style diagram with talking points. This will hopefully make it easy to use the book
as a quick reference as well. Applications immediately following a topic will further
clarify the subject matter, and my hope is that once you understand the semantics
and applications of a given topic, you are ready to apply that to your daily design
work. These applications are modeled such that you should be able to use them in
your design with minimal modifications.
This book is meant for both design and verification engineers. As a matter of
fact, I have devoted a complete section on the reasons and practicality behind
having micro-level assertions written by the design engineers and macro-level
assertions written by verification engineers. Gone are the days when designers
would write RTL and throw it over the wall for the verification engineer to quality
check.
The book covers both IEEE 1800-2005 and IEEE 1800-2009/2012 standard
SVA language.
Chapter 1 is introduction to SVA and FC giving a brief history of SVA evo-
lution. It also explains how SVA and FC fall under SystemVerilog umbrella to
provide a complete assertions and functional coverage-driven methodology.

xiii
xiv Preface to the First Edition

Part I: SystemVerilog Assertions (SVA)

Chapter 2 goes in-depth on SVA-based methodology providing detail that you can
right away use in your project execution. Questions such as ‘How do I know I have
added enough assertions?’, ‘What type of assertions should I add’, etc., are
explained with clarity.
Chapter 3 describes immediate assertions. These are non-temporal assertions
allowed in procedural code.
Chapter 4 goes into the fundamentals of concurrent assertions to set the stage for
the rest of the book. How the concurrent multi-threaded semantics work, when and
how assertions get evaluated in a simulation time tick, formal arguments, disabling,
etc., are described here.
Chapter 5 describes the so-called sampled value functions such as $rose, $fell,
$stable, $past, etc.
Chapter 6 is the big one! This chapter describes all the operators offered by the
language including clock delay with and without range, consecutive repetition with
and without range, non-consecutive repetition with and without range, ‘through-
out,’ ‘within,’ ‘and,’ ‘or,’ ‘intersect,’ ‘first_match,’ and ‘if…else,’. Each of the
operator descriptions is immediately followed by examples and applications to
solidify the concept.
Chapter 7 describes the system functions and tasks such as $isunknown and
$onehot.
Chapter 8 discusses a very important aspect of the language that being properties
with multiple clocks. There is not a single design nowadays that uses only a single
clock. A simple asynchronous FIFO will have a read clock and a write clock which
are asynchronous. Properties need to be written such that check in one clock
domain triggers a check in another clock domain. The chapter goes in plenty detail
to demystify semantics to write assertions that cross clock domains. The so-called
CDC (Clock Domain Crossing) assertions are explained in this chapter.
Chapter 9 is probably the most useful one describing local variables. Without
this multi-threaded feature, many of the assertions would be impossible to write.
There are plenty of examples to help you weed through the semantics.
Chapter 10 is on recursive properties. These are rarely used but are very handy
when you want to know that a property holds until another becomes true or false.
Chapters 11–13 describe other useful features such as ‘expect,’ ‘assume,’ and
detecting end point of a sequence. The .triggered and .matched end points of
sequences are indeed very practical features. Note that .ended (of LRM 2005) is
now deprecated and replaced with .triggered.
Chapter 14 is entirely devoted to very powerful and practical features that do not
quite fit elsewhere. Of main interest, here is the example/testbench for asyn-
chronous FIFO checks, concurrent assertions in procedural code, sequence in
Verilog ‘always’ block sensitivity list, and the phenomenon of a ‘vacuous pass’ !
Chapter 15 is solely devoted to asynchronous assertions. The example in this
chapter shows why you need to be extremely careful in using such assertions.
Preface to the First Edition xv

Chapter 16 is entirely devoted to IEEE 1800 2009-2012 features. There are

many useful features added by the language designers.
Chapter 17 describes 6 LABs for you to try out. The LABs start with simple
example moving gradually onto complex ones.
Note: The LABs are available on Springer download site. All required Verilog
files, testbenches, and run scripts are included for both PC and Linux OS.
Chapter 18 provides answers to the LABs of Chap. 17

Part II: SystemVerilog Functional Coverage (FC)

Chapter 19 provides introduction to functional coverage and explains differences

with code coverage.
Chapter 20 is fully devoted to functional coverage including in-depth detail on
covergroups, coverpoints, and bins including transition and cross coverage.
Chapter 21 provides practical hints to performance implications of coverage
methodology. Do not try to cover everything all the time.
Chapter 22 describes coverage options, which you may keep in your back pocket
as reference material for a rainy day!
Acknowledgements

I am very grateful to many who helped with review and editing of the book, in
particular, Mark Glaser for his excellent foreword and in-depth review of the book,
Vijay Akkati for detailed review of the chapters, Dr. Sandeep Goel for motivation
and editing of the book, and Bob Slee for his sustained support throughout the
endeavor and for facilitating close cooperation with EDA vendors. I would also like
to thank Tom Slee, Kea Hunt, Norbert Eng, Joe Chang, and Frank Lee for all things
verification.
And last but certainly not the least, I would like to thank my wife Ashraf Zahedi
for her enthusiasm and encouragement throughout the writing of this book and
putting up with long nights and weekends required to finish the book. She is the
cornerstone of my life always with a positive attitude to carry the day through up
and down of life.

xvii
Contents

1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 1
1.1 How Will This Book Help You? . . . . . . . . . . . . . ........ 4
1.2 SystemVerilog Assertions and Functional Coverage
Under IEEE 1800 SystemVerilog Umbrella . . . . . . ........ 5
1.3 SystemVerilog Assertions Evolution . . . . . . . . . . . ........ 7
2 SystemVerilog Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 What Is an Assertion? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Why Assertions? What Are the Advantages? . . . . . . . . . . . . . 9
2.2.1 Assertions Shorten Time to Develop . . . . . . . . . . . . 10
2.2.2 Assertions Improve Observability . . . . . . . . . . . . . . 11
2.2.3 Assertions Provide Temporal Domain Functional
Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11
2.2.4 Assertion Based Methodology Allows for Full
Random Verification . . . . . . . . . . . . . . . . . . . . . .. 14
2.2.5 Assertions Help Detect Bugs not Easily Observed
at Primary Outputs . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.6 Other Major Benefits . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 How Do Assertions Work with an Emulator?. . . . . . . . . . . . . 16
2.4 Assertions in Static Formal . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5 One-Time Effort, Many Benefits. . . . . . . . . . . . . . . . . . . . . . 19
2.6 Assertions Whining. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6.1 Who Will Add Assertions? War Within! . . . . . . . . . 21
2.7 A Simple PCI Read Example—Creating an Assertions Test
Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.8 What Type of Assertions Should I Add? . . . . . . . . . . . . . . . . 24
2.9 Protocol for Adding Assertions . . . . . . . . . . . . . . . . . . . . . . 25
2.10 How Do I Know I Have Enough Assertions? . . . . . . . . . . . . . 26
2.11 Use Assertions for Specification and Review . . . . . . . . . . . . . 26
2.12 Assertion Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.13 Conventions Used in the Book . . . . . . . . . . . . . . . . . . . . . . . 28

xix
xx Contents

3 Immediate Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4 Concurrent Assertions—Basics (Sequence, Property, Assert) . . ... 35
4.1 Implication Operator, Antecedent and Consequent . . . . . . ... 40
4.2 Clocking Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 42
4.3 Sampling Edge (Clock Edge) Value: How Are Assertions
Evaluated in a Simulation Time Tick?. . . . . . . . . . . . . . . . . . 44
4.3.1 Default Clocking Block . . . . . . . . . . . . . . . . . . . . . 48
4.3.2 Gated Clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.4 Concurrent Assertions Are Multi-threaded . . . . . . . . . . . . . . . 53
4.5 Formal Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.6 Disable (Property) Operator—‘Disable Iff’ . . . . . . . . . . . . . . . 58
4.7 Severity Levels (for Both Concurrent and Immediate
Assertions). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.8 Binding Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.8.1 Binding Properties (Scope Visibility). . . . . . . . . . . . 62
4.8.2 Assertion Adoption in Existing Design . . . . . . . . . . 64
4.9 Difference Between ‘Sequence’ and ‘Property’ . . . . . . . . . . . . 65
5 Sampled Value Functions $rose, $fell, $stable, $past . . . . . . . . . . . 67
5.1 $rose—Edge Detection in Property/Sequence . . . . . . . . . . . . . 68
5.1.1 Edge Detection Is Useful Because … . . . . . . . . . . . 68
5.1.2 $fell—Edge Detection in Property/Sequence. . . . . . . 71
5.1.3 $rose, $fell—in Procedural . . . . . . . . . . . . . . . . . . . 71
5.2 $stable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.2.1 $stable in Procedural Block . . . . . . . . . . . . . . . . . . 73
5.3 $past. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.3.1 Application: $past () . . . . . . . . . . . . . . . . . . . . . . . 78
5.3.2 $past Rescues $fell! . . . . . . . . . . . . . . . . . . . . . . . 78
6 Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.1 ##m—Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.1.1 Clock Delay Operator: ##m Where m=0 . . . . . . . . . 82
6.2 ##[m:n]—Clock Delay Range . . . . . . . . . . . . . . . . . . . . . . . 84
6.2.1 Clock Delay Range Operator: ##[m:n]: Multiple
Threads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 85
6.2.2 Clock Delay Range Operator :: ##[m:n]
(m=0; n=$) . . . . . . . . . . . . . . . . . . . . . . . . . . ... 94
6.3 [*m]—Consecutive Repetition Operator. . . . . . . . . . . . . . ... 94
6.4 [*m:n]—Consecutive Repetition Range . . . . . . . . . . . . . . ... 98
6.4.1 Application: Consecutive Repetition Range
Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.5 [=m]—Repetition Non-consecutive . . . . . . . . . . . . . . . . . . . . 107
6.6 [=m:n]—Repetition Non-consecutive Range . . . . . . . . . . . . . . 111
6.6.1 Application: Repetition Non-consecutive
Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Contents xxi

6.7 [->m] Non-consecutive GoTo Repetition Operator . . . . . . . . . 114

6.8 Difference Between [=m:n] and [->m:n] . . . . . . . . . . . . . . . . 115
6.8.1 Application: GoTo Repetition—Non-consecutive
Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.9 Sig1 throughout Seq1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.9.1 Application: Sig1 throughout Seq1 . . . . . . . . . . . . . 118
6.10 Seq1 within Seq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.10.1 Application: Seq1 within Seq2 . . . . . . . . . . . . . . . . 122
6.10.2 ‘within’ Operator PASS CASES . . . . . . . . . . . . . . . 123
6.10.3 ‘within’ Operator: FAIL CASES . . . . . . . . . . . . . . . 124
6.11 Seq1 and Seq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.11.1 Application: ‘and’ Operator . . . . . . . . . . . . . . . . . . 127
6.12 Seq1 ‘or’ Seq2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.12.1 Application: or Operator . . . . . . . . . . . . . . . . . . . . 128
6.13 Seq1 ‘intersect’ Seq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.14 Application: ‘intersect’ Operator . . . . . . . . . . . . . . . . . . . . . . 132
6.14.1 Application: intersect Operator (Interesting
Application) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.14.2 ‘intersect’ and ‘and’ :: What’s the Difference? . . . . . 137
6.15 first_match. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.15.1 Application: first_match . . . . . . . . . . . . . . . . . . . . . 138
6.16 not <property expr> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.16.1 Application: not Operator. . . . . . . . . . . . . . . . . . . . 141
6.17 if (expression) property_expr1 else property_expr2 . . . . . . . . . 143
6.17.1 Application: if then else. . . . . . . . . . . . . . . . . . . . . 145
6.18 ‘iff’ and ‘implies’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
7 System Functions and Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.1 $onehot, $onehot0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.2 $isunknown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.3 $countones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7.3.1 $countones (as Boolean) . . . . . . . . . . . . . . . . . . . . 151
7.4 $assertoff, $asserton, $assertkill . . . . . . . . . . . . . . . . . . . . . . 151
8 Multiple Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
8.1 Multiply-Clocked Sequences and Properties . . . . . . . . . . . . . . 155
8.1.1 Multiply Clocked Sequences . . . . . . . . . . . . . . . . . 156
8.1.2 Multiply Clocked Sequences—Legal and Illegal
Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
8.1.3 Multiply Clocked Properties—‘and’ Operator . . . . . . 158
8.1.4 Multiply Clocked Properties—‘or’ Operator . . . . . . . 159
8.1.5 Multiply Clocked Properties—‘not’—Operator . . . . . 161
8.1.6 Multiply Clocked Properties—Clock Resolution . . . . 161
8.1.7 Multiply Clocked Properties—Legal and Illegal
Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
xxii Contents

9 Local Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

9.1 Application: Local Variables . . . . . . . . . . . . . . . . . . . . . . . . 179
10 Recursive Property. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
10.1 Application: Recursive Property . . . . . . . . . . . . . . . . . . . . . . 182
10.2 Application: Recursive Property . . . . . . . . . . . . . . . . . . . . . . 183
11 Detecting and Using Endpoint of a Sequence . . . . . . . . . . . . . . . . . 187
11.1 .triggered (Replaced for .ended) . . . . . . . . . . . . . . . . . . . . . . 187
11.2 .matched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
11.2.1 Application: .matched . . . . . . . . . . . . . . . . . . . . . . 198
12 ‘expect’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
13 ‘assume’ and Formal (Static Functional) Verification . . . . . . . . . . . 205
14 Very Important Topics and Applications. . . . . . . . . . . . . . . . . . . . 207
14.1 Asynchronous FIFO Assertions . . . . . . . . . . . . . . . . . . . . . . 207
14.1.1 Asynchronous FIFO Design . . . . . . . . . . . . . . . . . . 208
14.1.2 Asynchronous FIFO Testbench and Assertions . . . . . 210
14.1.3 Test the Testbench . . . . . . . . . . . . . . . . . . . . . . . . 214
14.2 Embedding Concurrent Assertions in Procedural Code . . . . . . 217
14.3 Calling Subroutines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
14.4 Sequence as a Formal Argument . . . . . . . . . . . . . . . . . . . . . 225
14.5 Sequence as an Antecedent . . . . . . . . . . . . . . . . . . . . . . . . . 226
14.6 Sequence in Sensitivity List . . . . . . . . . . . . . . . . . . . . . . . . . 227
14.7 Building a Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
14.8 Clock Delay: What if You Want Variable Clock Delay? . . . . . 229
14.9 What if the ‘Action Block’ Is Blocking? . . . . . . . . . . . . . . . . 231
14.10 Interesting Observation with Multiple (Nested) Implications
in a Property. Be Careful. . . . . . . . . . . . . . . . . . . . . . . . . . . 234
14.11 Subsequence in a Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 235
14.12 Cyclic Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
14.13 Refinement on a Theme . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
14.14 Simulation Performance Efficiency . . . . . . . . . . . . . . . . . . . . 237
14.15 It’s a Vacuous World! Huh? . . . . . . . . . . . . . . . . . . . . . . . . 239
14.15.1 Concurrent Assertion—Without—An Implication . . . 239
14.15.2 Concurrent Assertion—With—An Implication . . . . . 240
14.15.3 Vacuous Pass. What? . . . . . . . . . . . . . . . . . . . . . . 241
14.15.4 Concurrent Assertion–with ‘Cover’ . . . . . . . . . . . . . 241
14.16 Empty Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
15 Asynchronous Assertions!!!. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
16 IEEE-1800-2009/2012 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
16.1 Strong and Weak Sequences . . . . . . . . . . . . . . . . . . . . . . . . 251
16.2 Deferred Immediate Assertions . . . . . . . . . . . . . . . . . . . . . . . 252
16.3 $changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Contents xxiii

16.4 $sampled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

16.5 $past_gclk, $rose_gclk, $fell_gclk, $stable_gclk, $changed_
gclk, $future_gclk, $rising_gclk, $falling_gclk, $steady_gclk,
$changing_gclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
16.6 ‘followed by’ Properties #-# and #=# . . . . . . . . . . . . . . . . . . 261
16.7 ‘always’ and ‘s_always’ Property . . . . . . . . . . . . . . . . . . . . . 262
16.8 ‘eventually’,‘s_eventually’ . . . . . . . . . . . . . . . . . . . . . . . . . . 264
16.9 ‘until’, ‘s_until’, ‘until_with’ and ‘s_until_with’ . . . . . . . . . . . 265
16.10 ‘nexttime’ and ‘s_nexttime’ . . . . . . . . . . . . . . . . . . . . . . . . . 267
16.11 ‘case’ Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
16.12 $inferred_clock and $inferred_disable . . . . . . . . . . . . . . . . . . 271
16.13 ‘let’ Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
16.13.1 let: Local Scope . . . . . . . . . . . . . . . . . . . . . . . . . . 274
16.13.2 let: With Parameters . . . . . . . . . . . . . . . . . . . . . . . 275
16.13.3 let: In Immediate and Concurrent Assertions . . . . . . 277
16.14 ‘restrict’ for Formal Verification . . . . . . . . . . . . . . . . . . . . . . 280
16.15 Abort Properties: reject_on, accept_on, sync_reject_on,
sync_accept_on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
16.16 $assertpassoff, $assertpasson, $assertfailoff, $assertfailon,
$assertnonvacuouson, $assertvacuousoff . . . . . . . . . . . . . . . . 284
16.17 $assertcontrol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
16.18 Checkers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
16.18.1 Nested Checkers . . . . . . . . . . . . . . . . . . . . . . . . . . 295
16.18.2 Checkers: Illegal Conditions . . . . . . . . . . . . . . . . . . 296
16.18.3 Checkers: Important Points. . . . . . . . . . . . . . . . . . . 298
16.18.4 Checker: Instantiation Rules . . . . . . . . . . . . . . . . . . 301
17 SystemVerilog Assertions LABs . . . . . . . . . . . . . . . . . . . . . . . . . . 305
17.1 LAB1: Assertions with/Without Implication and ‘bind’ . . . . . . 305
17.1.1 LAB1: ‘bind’ DUT Model and Testbench . . . . . . . . 306
17.1.2 LAB1: Questions . . . . . . . . . . . . . . . . . . . . . . . . . 308
17.2 LAB2: Overlap and Non-overlap Operators . . . . . . . . . . . . . . 310
17.2.1 LAB2 DUT Model and Testbench . . . . . . . . . . . . . 310
17.2.2 LAB2: Questions . . . . . . . . . . . . . . . . . . . . . . . . . 311
17.3 LAB3: Synchronous FIFO Assertions . . . . . . . . . . . . . . . . . . 313
17.3.1 LAB3: DUT Model and Testbench . . . . . . . . . . . . . 313
17.3.2 LAB3: Questions . . . . . . . . . . . . . . . . . . . . . . . . . 317
17.4 LAB4: Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
17.4.1 LAB4: Questions . . . . . . . . . . . . . . . . . . . . . . . . . 324
17.5 LAB5: Data Transfer Protocol . . . . . . . . . . . . . . . . . . . . . . . 327
17.5.1 LAB5: Questions . . . . . . . . . . . . . . . . . . . . . . . . . 335
17.6 LAB6: PCI Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 336
17.6.1 LAB6: Questions . . . . . . . . . . . . . . . . . . . . . . . . . 340
xxiv Contents

18 SystemVerilog Assertions—LAB Answers . . . . . . . . . . . . . . . . . . . 343

18.1 LAB1: Answers: ‘bind’ and Implication Operators . . . . . . . . . 344
18.2 LAB2: Answers: Overlap and Non-overlap Operators . . . . . . . 349
18.3 LAB3: Answers: Synchronous FIFO . . . . . . . . . . . . . . . . . . . 353
18.4 LAB4: Answers: Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 355
18.5 LAB5: Answers: Data Transfer Protocol . . . . . . . . . . . . . . . . 356
18.6 LAB6: Answers: PCI Read Protocol . . . . . . . . . . . . . . . . . . . 359
19 Functional Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
19.1 Difference Between Code Coverage and Functional
Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
19.2 Assertion Based Verification (ABV) and Functional Coverage
(FC) Based Methodology. . . . . . . . . . . . . . . . . . . . . . . . . . . 362
19.2.1 Follow the Bugs!! . . . . . . . . . . . . . . . . . . . . . . . . . 366
20 Functional Coverage—Language Features. . . . . . . . . . . . . . . . . . . 367
20.1 Covergroup/Coverpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
20.2 System Verilog ‘Covergroup’—Basics … . . . . . . . . . . . . . . . 368
20.3 SystemVerilog Coverpoint Basics . . . . . . . . . . . . . . . . . . . . . 368
20.3.1 Covergroup/Coverpoint Example … . . . . . . . . . . . . 371
20.4 System Verilog ‘Bins’—Basics … . . . . . . . . . . . . . . . . . . . . 372
20.4.1 Covergroup/Coverpoint with Bins—Example … . . . . 374
20.4.2 System Verilog ‘covergroup’—Formal and Actual
Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
20.4.3 ‘covergroup’ in a ‘class’ . . . . . . . . . . . . . . . . . . . . 376
20.5 ‘cross’ Coverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
20.6 More ‘Bins’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
20.6.1 ‘Bins’ for Transition Coverage . . . . . . . . . . . . . . . . 382
20.6.2 ‘wildcard bins’ . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
20.6.3 ‘ignore_bins’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
20.6.4 ‘illegal_bins’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
20.6.5 ‘binsof’ and ‘intersect’. . . . . . . . . . . . . . . . . . . . . . 388
21 Performance Implications of Coverage Methodology . . . . . . . . . . . 391
21.1 Know What You Should Cover . . . . . . . . . . . . . . . . . . . . . . 391
21.2 Know When You Should Cover . . . . . . . . . . . . . . . . . . . . . . 392
21.3 When to ‘Cover’ (Performance Implication). . . . . . . . . . . . . . 392
21.4 Application: Have You Transmitted All Different Lengths
of a Frame? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
22 Coverage Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
22.1 Coverage Options—Instance Specific—Example. . . . . . . . . . . 397
22.2 Coverage Options—Instance Specific Per-Syntactic Level . . . . 397
22.3 Coverage Options for ‘Covergroup’ Type—Example. . . . . . . . 400

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
About the Author

Ashok B. Mehta has been working in the ASIC/SoC design and verification field
for over 20 years. He started his career at Digital Equipment Corporation
(DEC) working first as a CPU design engineer, moving on to hardware design
verification of the VAX11-785 CPU design. He then worked at Data General, Intel
(first Pentium design team) and, after a route of a couple of startups, worked at
Applied Micro and TSMC. He was a very early adopter of Verilog and participated
in Verilog, VHDL, iHDL (Intel HDL), and SDF (standard delay format) technical
subcommittees. He has also been a proponent of ESL (Electronic System Level)
designs, and at TSMC, he released two industry-standard reference flows that take
designs from ESL to RTL while preserving the verification environment for reuse
from ESL to RTL. Lately, he has been involved with 3DIC design verification
challenges at TSMC which is where SystemVerilog Assertions played an instru-
mental role in stacked die SoC design verification.
Ashok earned an MSEE from University of Missouri. He holds 13 US Patents in
the field of SoC and 3DIC design verification. In his spare time, he is an amateur
photographer and likes to play drums on 1970s rock music driving his neighbors up
the wall.

xxv
List of Figures

Figure 1.1 Verification cost increases as the technology

node shrinks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2
Figure 1.2 Design productivity and design complexity . . . . . . . . . . .. 2
Figure 1.3 SystemVerilog assertions and functional coverage
components under SystemVerilog IEEE 1800-2009
umbrella . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 1.4 SystemVerilog evolution . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 1.5 SystemVerilog assertion evolution . . . . . . . . . . . . . . . . . . 7
Figure 2.1 A simple bus protocol design and its SVA property . . . . . . 10
Figure 2.2 Verilog code for the simple bus protocol . . . . . . . . . . . . . 11
Figure 2.3 Assertions improve observability . . . . . . . . . . . . . . . . . . . 12
Figure 2.4 SystemVerilog assertions provide temporal domain
functional coverage . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12
Figure 2.5 Assertions for hardware emulation . . . . . . . . . . . . . . . . .. 17
Figure 2.6 Assertions and assumptions in formal (static functional)
and simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 2.7 Assertions and OVL for different uses . . . . . . . . . . . . . . . 19
Figure 2.8 A simple PCI read protocol. . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3.1 Immediate assertion—basics . . . . . . . . . . . . . . . . . . . . . . 32
Figure 3.2 Immediate assertions: finer points . . . . . . . . . . . . . . . . . . 33
Figure 4.1 Concurrent assertion—basics . . . . . . . . . . . . . . . . . . . . . . 36
Figure 4.2 Concurrent assertion—sampling edge and action
blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 37
Figure 4.3 Concurrent assertion—implication, antecedent
and consequent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 38
Figure 4.4 Property with an embedded sequence . . . . . . . . . . . . . . .. 39
Figure 4.5 Implication operator—overlapping
and non-overlapping. . . . . . . . . . . . . . . . . . . . . . . . . . .. 40
Figure 4.6 Equivalence between overlapping and non-overlapping
implication operators . . . . . . . . . . . . . . . . . . . . . . . . . .. 41
Figure 4.7 Clocking basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 43

xxvii
xxviii List of Figures

Figure 4.8 Clocking basics—clock in ‘assert’, ‘property’

and ‘sequence’. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 43
Figure 4.9 Assertions variable sampling and evaluation/execution in
a simulation time tick . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 4.10 Default Clocking block. . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 4.11 ‘clocking’ and ‘default clocking’ . . . . . . . . . . . . . . . . . . . 50
Figure 4.12 Gated clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 4.13 Multi-threaded concurrent assertions. . . . . . . . . . . . . . . . . 54
Figure 4.14 Formal and actual arguments . . . . . . . . . . . . . . . . . . . . . . 55
Figure 4.15 Formal and Actual arguments—default value and name
based connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 56
Figure 4.16 Formal and actual arguments—default value and position
based connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 57
Figure 4.17 Passing event control to a formal . . . . . . . . . . . . . . . . . .. 57
Figure 4.18 ‘disable iff’ operator. . . . . . . . . . . . . . . . . . . . . . . . . . .. 59
Figure 4.19 Severity levels for concurrent and immediate
assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 60
Figure 4.20 Binding properties . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 62
Figure 4.21 Binding properties to design ‘module’ internal signals
(scope visibility) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 63
Figure 4.22 Binding properties to an existing design. Assertions
adoption in existing design . . . . . . . . . . . . . . . . . . . . . .. 64
Figure 5.1 Sampled value functions $rose, $fell—basics. . . . . . . . . .. 68
Figure 5.2 $rose—basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 69
Figure 5.3 usefulness of ‘edge’ detection and performance
implication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 70
Figure 5.4 ; $rose—finer points. . . . . . . . . . . . . . . . . . . . . . . . . . .. 70
Figure 5.5 $fell—basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 71
Figure 5.6 $rose and $fell in procedural block and continuous
assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 5.7 $stable—basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 5.8 $stable in procedural block . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 5.9 $past—basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 5.10 $past—gating expression . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 5.11 $past—gating expression—simulation log . . . . . . . . . . . . . 77
Figure 5.12 $past application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 5.13 $past rescues $fell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 6.1 ##m clock delay—basics . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 6.2 ##m clock delay with m=0 . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 6.3 ##0—application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 6.4 ##[m:n] clock delay range. . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 6.5 ##[m:n]—multiple threads. . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 6.6 ##[m:n] clock delay range with m=0 and n=$ . . . . . . . . . . 95
Figure 6.7 ##[1:$] delay range application . . . . . . . . . . . . . . . . . . . . 96
List of Figures xxix

Figure 6.8 [*m]—consecutive repetition operator—basics . . . . . . . . . . 96

Figure 6.9 [*m] consecutive repetition operator—application . . . . . . . 97
Figure 6.10 [*m:n] consecutive repetition range—basics . . . . . . . . . . . 98
Figure 6.11 [*m:n] consecutive repetition range—example . . . . . . . . . . 100
Figure 6.12 [*m:n] consecutive repetition range—application . . . . . . . . 101
Figure 6.13 [*m:n] consecutive repetition range—application . . . . . . . . 102
Figure 6.14 [*m:n] consecutive repetition range—application . . . . . . . . 103
Figure 6.15 [*m:n] consecutive repetition range—application . . . . . . . . 104
Figure 6.16 Design application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 6.17 Design application—simulation log . . . . . . . . . . . . . . . . . 108
Figure 6.18 Repetition non-consecutive operator—basics . . . . . . . . . . . 109
Figure 6.19 Non-consecutive repetition operator—example. . . . . . . . . . 110
Figure 6.20 Repetition non-consecutive range—basics . . . . . . . . . . . . . 111
Figure 6.21 Repetition non-consecutive range—application . . . . . . . . . 113
Figure 6.22 Repetition non-consecutive range—[=0:$] . . . . . . . . . . . . . 113
Figure 6.23 GoTo non-consecutive repetition—basics . . . . . . . . . . . . . 114
Figure 6.24 Non-consecutive repetition—example . . . . . . . . . . . . . . . . 115
Figure 6.25 Difference between [=m:n] and [->m:n] . . . . . . . . . . . . . . 116
Figure 6.26 GoTo repetition—non-consecutive
operator—application . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 6.27 Sig1 throughout seq1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 6.28 Sig1 throughout Seq1—application . . . . . . . . . . . . . . . . . 119
Figure 6.29 Sig1 throughout seq1—application simulation log . . . . . . . 120
Figure 6.30 Seq1 within seq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 6.31 Seq1 within seq2—application . . . . . . . . . . . . . . . . . . . . . 122
Figure 6.32 within operator—simulation log
example—PASS cases . . . . . . . . . . . . . . . . . . . . . . .... 123
Figure 6.33 within operator—simulation log
example—FAIL cases . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 6.34 Seq1 and seq2—basics . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 6.35 and operator—application . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 6.36 and operator—application-II . . . . . . . . . . . . . . . . . . . . . . 127
Figure 6.37 and of expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 6.38 Seq1 or seq2—basics . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 6.39 or operator—application . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 6.40 or operator—application II . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 6.41 or operator—application III . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 6.42 or of expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 6.43 Seq1 intersect seq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 6.44 Seq1 ‘intersect’ seq2—application . . . . . . . . . . . . . . . . . . 134
Figure 6.45 Seq1 intersect seq2—application II. . . . . . . . . . . . . . . . . . 134
Figure 6.46 intersect makes sense with subsequences with ranges . . . . . 135
Figure 6.47 intersect operator: interesting application. . . . . . . . . . . . . . 135
Figure 6.48 and versus intersect—what’s the difference . . . . . . . . . . . . 137
xxx List of Figures

Figure 6.49 first_match—application . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 6.50 first_match application . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 6.51 first_match application . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 6.52 not operator—basics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 6.53 not operator—application . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 6.54 not operator—application . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 6.55 if… else . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 6.56 if… else—application . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 7.1 $onehot and $onehot0 . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 7.2 $isunknown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 7.3 $isunknown application . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 7.4 $countones—basics and application . . . . . . . . . . . . . . . . . 150
Figure 7.5 Application $countones. . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 7.6 $countones as boolean . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 7.7 $assertoff, $asserton, $assertkill—basics . . . . . . . . . . . . . . 152
Figure 7.8 Application assertion control . . . . . . . . . . . . . . . . . . . . . . 152
Figure 8.1 Multiply clocked sequences—basics . . . . . . . . . . . . . . . . . 156
Figure 8.2 Multiply clocked sequences—identical clocks . . . . . . . . . . 157
Figure 8.3 Multiply clocked sequences—illegal conditions . . . . . . . . . 158
Figure 8.4 Multiply clocked properties—‘and’ operator
between two different clocks . . . . . . . . . . . . . . . . ...... 159
Figure 8.5 Multiply clocked properties—‘and’ operator
between same clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 8.6 Multiply clocked properties—‘or’ operator . . . . . . . . . . . . 160
Figure 8.7 Multiply clocked properties—‘not’ operator. . . . . . . . . . . . 161
Figure 8.8 Multiply clocked properties—clock resolution . . . . . . . . . . 162
Figure 8.9 Multiply clocked properties—clock resolution—II . . . . . . . 162
Figure 8.10 Multiply clocked properties—clock resolution—III. . . . . . . 163
Figure 8.11 Multiply clocked properties—legal and illegal
conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 9.1 Local variables—basics . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 9.2 Local variables—do’s and don’ts . . . . . . . . . . . . . . . . . . . 169
Figure 9.3 Local variables—and formal argument . . . . . . . . . . . . . . . 170
Figure 9.4 Local variables—visibility. . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 9.5 Local variable composite sequence with an ‘OR’ . . . . . . . . 171
Figure 9.6 Local variables—for an ‘OR’ assign local
data—before- the composite sequence . . . . . . . . . ...... 172
Figure 9.7 Local variables—assign local data in both
operand sequences of ‘OR’ . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 9.8 Local variables—‘and’ of composite sequences . . . . . . . . . 173
Figure 9.9 Local variables—finer nuances III . . . . . . . . . . . . . . . . . . 173
Figure 9.10 Local variables—further nuances IV. . . . . . . . . . . . . . . . . 174
Figure 9.11 Local variable cannot be used in delay range. . . . . . . . . . . 174
List of Figures xxxi

Figure 9.12 Local variables—cannot use a ‘formal’ to size a local

variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 9.13 Local variables—application . . . . . . . . . . . . . . . . . . . . . . 179
Figure 10.1 Recursive property—basics . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 10.2 Recursive property—application. . . . . . . . . . . . . . . . . . . . 183
Figure 10.3 Recursive property—application. . . . . . . . . . . . . . . . . . . . 184
Figure 10.4 Recursive property—further nuances I . . . . . . . . . . . . . . . 185
Figure 10.5 Recursive property—further nuances II . . . . . . . . . . . . . . . 185
Figure 10.6 Recursive property—mutually recursive . . . . . . . . . . . . . . 186
Figure 11.1 .triggered—end point of a sequence . . . . . . . . . . . . . . . . . 188
Figure 11.2 .triggered with overlapping operator . . . . . . . . . . . . . . . . . 189
Figure 11.3 .triggered with non-overlapping operator . . . . . . . . . . . . . . 190
Figure 11.4 .matched—basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 11.5 .matched with non-overlapping operator . . . . . . . . . . . . . . 197
Figure 11.6 .matched—overlapped operator . . . . . . . . . . . . . . . . . . . . 197
Figure 11.7 .matched—application . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 12.1 ‘expect’—basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 12.2 ‘expect’—error conditions . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 13.1 ‘Assume’ and formal verification . . . . . . . . . . . . . . . . . . . 206
Figure 14.1 Embedding concurrent assertions in procedural code . . . . . 217
Figure 14.2 Concurrent assertion embedded in procedural code is
non-blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 218
Figure 14.3 Embedding concurrent assertions in procedural
code—further nuances . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 14.4 Calling subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 14.5 Calling subroutines—further nuances . . . . . . . . . . . . . . . . 223
Figure 14.6 Application: calling subroutines and local variables . . . . . . 224
Figure 14.7 Sequence as a formal argument . . . . . . . . . . . . . . . . . . . . 225
Figure 14.8 Sequence as an antecedent . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 14.9 Sequence in procedural block sensitivity list . . . . . . . . . . . 227
Figure 14.10 Sequence in ‘sensitivity’ list . . . . . . . . . . . . . . . . . . . . . . 228
Figure 14.11 Application: building a counter using local variables . . . . . 229
Figure 14.12 Variable delay—problem statement . . . . . . . . . . . . . . . . . 230
Figure 14.13 Variable delay—solution. . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 14.14 Blocking action block. . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 14.15 Blocking versus non-blocking action block . . . . . . . . . . . . 233
Figure 14.16 Multiple implications in a property. . . . . . . . . . . . . . . . . . 234
Figure 14.17 Subsequence in a sequence—clock inference . . . . . . . . . . . 236
Figure 14.18 Subsequence in a sequence . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 14.19 Cyclic dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 14.20 Refinements on a theme . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 14.21 Simulation performance efficiency . . . . . . . . . . . . . . . . . . 238
Figure 14.22 Assertion without implication operator . . . . . . . . . . . . . . . 239
Figure 14.23 Assertion resulting in vacuous pass . . . . . . . . . . . . . . . . . 240
xxxii List of Figures

Figure 14.24 Assertion with ‘cover’ for PASS . . . . . . . . . . . . . . . . . . . 242

Figure 14.25 Empty match [*m] where m = 0 . . . . . . . . . . . . . . . . . . . 243
Figure 14.26 empty match—example . . . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 14.27 empty match example—II . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 14.28 Empty sequence. Further rules . . . . . . . . . . . . . . . . . . . . . 245
Figure 15.1 Asynchronous assertion—problem statement . . . . . . . . . . . 248
Figure 15.2 Asynchronous assertion—problem statement analysis
continued . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 15.3 Asynchronous assertion—solution . . . . . . . . . . . . . . . . . . 250
Figure 16.1 $changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Figure 17.1 LAB1: ‘bind’ assertions. Problem definition . . . . . . . . . . . 306
Figure 17.2 LAB3: Synchronous FIFO: problem definition. . . . . . . . . . 313
Figure 17.3 LAB4: counter: problem definition. . . . . . . . . . . . . . . . . . 322
Figure 17.4 LAB5: data transfer protocol: problem definition . . . . . . . . 329
Figure 17.5 LAB6: PCI protocol: problem definition . . . . . . . . . . . . . . 337
Figure 18.1 LAB1: ‘bind’ assertions (answers) . . . . . . . . . . . . . . . . . . 344
Figure 18.2 LAB1: Q&A on ‘no_implication’ operator (answers) . . . . . 345
Figure 18.3 LAB1: Q&A on ‘implication’ operator (answers) . . . . . . . . 346
Figure 18.4 LAB1: Q&A on ‘overlap’ operator (answers) . . . . . . . . . . 349
Figure 18.5 LAB1: Q&A on ‘non-overlap’ operator (answers) . . . . . . . 350
Figure 18.6 LAB3: FIFO: answers . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Figure 18.7 LAB4: counter: answers . . . . . . . . . . . . . . . . . . . . . . . . . 355
Figure 18.8 LAB5: data transfer bus protocol: answers . . . . . . . . . . . . 357
Figure 18.9 LAB6: PCI protocol: answers . . . . . . . . . . . . . . . . . . . . . 359
Figure 19.1 Assertion based verification (ABV) and functional
coverage (FC) based methodology . . . . . . . . . . . . . . . . .. 363
Figure 19.2 Assertions and coverage closed loop verification
methodology—I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 364
Figure 19.3 Assertion and functional Coverage closed loop
verification methodology—II . . . . . . . . . . . . . . . . . . . . . . 365
Figure 20.1 ‘covergroup’ and ‘coverpoint’—basics . . . . . . . . . . . . . . . 369
Figure 20.2 ‘coverpoint’—basics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Figure 20.3 ‘covergroup’/‘coverpoint’ example . . . . . . . . . . . . . . . . . . 371
Figure 20.4 ‘bins’—basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Figure 20.5 ‘covergroup’/‘coverpoint’ example with ‘bins’ . . . . . . . . . . 374
Figure 20.6 ‘covergroup’—formal and actual arguments. . . . . . . . . . . . 375
Figure 20.7 ‘covergroup’ in a SystemVerilog class (courtesy LRM
1800-2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Figure 20.8 Multiple ‘covergroup’ in a SystemVerilog class . . . . . . . . . 377
Figure 20.9 ‘cross’ coverage—basics . . . . . . . . . . . . . . . . . . . . . . . . . 379
Figure 20.10 ‘cross’ coverage—simulation log . . . . . . . . . . . . . . . . . . . 380
Figure 20.11 ‘cross’—example (further nuances) . . . . . . . . . . . . . . . . . 381
Figure 20.12 ‘cross’ example—simulation log . . . . . . . . . . . . . . . . . . . 381
Figure 20.13 ‘bins’ for transition coverage . . . . . . . . . . . . . . . . . . . . . . 382
List of Figures xxxiii

Figure 20.14 ‘bins’—transition coverage further features . . . . . . . . . . . . 383

Figure 20.15 ‘bins’ for transition—example with simulation log . . . . . . . 384
Figure 20.16 Example of PCI cycles transition coverage . . . . . . . . . . . . 385
Figure 20.17 wildcard ‘bins’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Figure 20.18 ‘ignore_bins’—basics . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Figure 20.19 ‘illegal_bins’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
Figure 20.20 ‘binsof’ and ‘intersect’ . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Figure 21.1 Functional coverage—performance implication . . . . . . . . . 392
Figure 21.2 Application—have you transmitted all different lengths
of a frame? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 394
Figure 22.1 Coverage options—reference material . . . . . . . . . . . . . . .. 396
Figure 22.2 Coverage options—instance specific—example . . . . . . . .. 397
Figure 22.3 Coverage options—instance specific per-syntactic
level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 398
Figure 22.4 Coverage options type specific per syntactic level . . . . . .. 399
Figure 22.5 Coverage options for ‘covergroup’ type
specific—comprehensive example . . . . . . . . . . . . . . . . .. 400
Figure 22.6 Predefined coverage system tasks and functions. . . . . . . .. 401
List of Tables

Table 2.1 PCI read protocol test plan by functional verification team . . . 23
Table 2.2 PCI read protocol test plan by design team . . . . . . . . . . . . . . 24
Table 2.3 Conventions used in this book . . . . . . . . . . . . . . . . . . . . . . . 28
Table 6.1 Concurrent assertion operators . . . . . . . . . . . . . . . . . . . . . . . 82

xxxv
Chapter 1
Introduction

As is well known in the industry, the design complexity at 16 nm node and

below is exploding. Small form factor requirements and conflicting demands of
high performance and low power and small area result in ever so complex design
architecture. Multi-core, multi-threading and Power, Performance and Area
(PPA) demands exacerbate the design complexity and functional verification
thereof.
The burden lies on functional and temporal domain verification to make sure that
the design adheres to the specification. Not only is RTL (and Virtual Platform level)
functional verification important but so is silicon validation. Days when engineering
teams would take months to validate the silicon in the lab are over. What can you
do during pre-silicon verification to guarantee post-silicon validation a first pass
success.
The biggest challenge that the companies face is short time-to-market to deliver
first pass working silicon of increasing complexity. Functional design verification is
the long poll to design tape-out. Here are two key problem statements.
1. Design Verification Productivity: 40–50 % of project resources go to functional
design verification. The chart in Fig. 1.1 shows design cost for different parts of
a design cycle. As is evident, the design verification cost component is about
40+ % of the total design cost. In other words, this problem states that we must
increase the productivity of functional design verification and shorten the design
⇔ simulate ⇔ debug ⇔ cover loop. This is a productivity issue, which needs to
be addressed.
Continuing with the productivity issue, the chart in Fig. 1.2 shows that the
compounded complexity growth rate per year is 58 % while the compounded
productivity growth rate is only 21 %. There is a huge gap between what needs
to get done and what is getting done. This is another example of why the
productivity of design cycle components such as functional design verification
must be improved.

© Springer International Publishing Switzerland 2016 1

A.B. Mehta, SystemVerilog Assertions and Functional Coverage,
DOI 10.1007/978-3-319-30539-4_1
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 THE CRISIS
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Mr. W. Justin Carter, Harrisburg, Pa.
Rev. Harvey Johnson, D.D., Baltimore, Md.
Hon. Wm. S. Bennett, Washington, D. C.
Mr. L. M. Hershaw, Washington, D. C.
Prof. Kelly Miller, Washington, D. C.
Prof. L. B. Moore, Washington, D. C.
Justice W. P. Stafford, Washington, D. C.
[1]Mrs. Mary Church Terrell, Washington, D. C.
[1]Rev. J. Milton Waldron, Washington, D. C.
Prest. John Hope, Atlanta, Ga.
Mr. Leslie P. Hill, Manassas, Va.

1. Executive Committee.
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 Along the Color Line

POLITICAL.
Objections to the proposed appointment of William R. Lewis, a
Negro attorney of Boston, as an assistant attorney-general are being
presented to Attorney-General Wickersham. President Taft’s
intention to appoint Lewis was learned semi-officially at the White
House several weeks ago. Booker T. Washington has called upon Mr.
Wickersham to urge his approval of the appointment, and Speaker
Cannon has opposed it.

President Taft said in his message: “I renew my recommendation

that the claims of the depositors in the Freedman’s Bank be
recognized and paid by the passage of the pending bill on that
subject. I also renew my recommendation that steps be taken looking
to the holding of a Negro exposition in celebration of the fiftieth
anniversary of the issuing by Mr. Lincoln of the Emancipation
Proclamation.”

There is only one feature of the apportionment matter which is apt

to precipitate trouble, and that is the proposal to reduce the
representation of the Southern States which have deprived a part of
their population of the right of suffrage. Louisiana, Mississippi,
North Carolina, South Carolina and other Commonwealths below the
Mason and Dixon line have imposed restrictions upon the Negroes
which make it impossible for them to vote at any election.—Denver
Times.
 THE COURTS.
In Richmond, Va., Judge Goff, in the United States Circuit Court of
Appeals, decided that no deed conveying real estate could legally
preclude the subsequent conveyance of any part of that real estate to
persons of African descent. He held that any provision or clause
providing that real estate shall not be acquired by Negroes is invalid
and void, and that no such provision can be put into a deed. The case
was argued for the Negroes by George J. Hooper and William L.
Royall. A. O. Boschen argued for the other side. The decision of
Judge Goff will be appealed to the Supreme Court of the United
States. It is attracting wide attention and much comment among
members of the local bar. The case was that of the People’s Pleasure
Park vs. Worsham.

Having been defeated in the Supreme Court of New York, and that
defeat having been affirmed by the Appellate Division, the colored
Order of Elks has filed an appeal to the Court of Appeals and has
filed a bond of the National Surety Company to cover the payment of
any costs that may be awarded against it. The colored order was
enjoined from using the name or the emblem of the white Order of
Elks.

The verdict of $1,000 awarded George W. Griffin, a Pullman car

porter, against Daniel L. Brady, brother of “Diamond Jim” Brady,
was affirmed by the Appellate Division of the Supreme Court. Griffin
was arrested by Brady on a charge of theft, and after proving his
innocence sued his accuser.

Joseph Atwater, an Oklahoma Negro, filed in the Supreme Court

of the United States at Washington his appeal from the decision of
the Oklahoma courts which had refused to enjoin election officials in
Oklahoma City from denying him the right to vote on Nov. 8th. The
petition for injunction was based on the claim that the “grandfather
clause” placed in the Oklahoma constitution by amendment was
invalid, because it would deny the right to vote to a large number of
Negroes in the State entirely on account of color or previous
condition of servitude.