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8086 Interfacing
with IC

Memory Interfacing-I

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Outline
 Introduction
 Bit/Byte/Word addressable
 Memory Interfacing (using NAND)
 Memory Interfacing (using decoder)
 Examples
 References

Introduction
 Memory is a storage component in the computer used to store application
programs and data.
 The Memory chip is divided into equal parts called as CELLS.
 Each Cell is uniquely identified by a binary number called
as “ADDRESS”.
Memory Address Memory
Binary Hex Contents
00-0000-0000 000 10011001
00-0000-0001 001 00111000
00-0000-0010 002 11001001
00-0000-0011 003 00111011

11-1111-1100 3FC 01101000

11-1111-1101 3FD 10111001
11-1111-1110 3FE 00110100
11-1111-1111 3FF 00011000

1024 X 8 (or 1KX8) Memory

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Bit/Byte/Word Addressable memory

 The most important point to be noted is that in case of either of Byte
Address or Word Address, the address size can be any number of bits
(depends on the number of cells in the chip) but the cell size differs in
each case.
 The default memory configuration in the Computer design is Byte
Addressable.
Byte Addressable Memory Word Addressable Memory
When the data space in the cell = 8 bits then When the data space in the cell = word length of
the corresponding address space is called as CPU then the corresponding address space is
Byte Address. called as Word Address.

64K x 8 chip has 16 bit Address and cell size = For a 16-bit CPU, 64K x 16 chip has 16 bit
8 bits (1 Byte) which means that in this chip, Address & cell size = 16 bits (Word Length of
data is stored byte by byte. CPU) which means that in this chip, data is stored
word by word.

Memory Interfacing
 Memory Interfacing in 8086 is used to access memory by the 8086 for
reading the instruction codes (EPROM) and data stored (RAM) in it.
 A memory device or memory chip must have four types of lines:
Address, Data, Control and selection.

Size Lines (n) Range (Hex)

1K*8 1024 210 10 00000 - 003FF

2K*8 2048 211 11 00000 - 007FF

4K*8 4096 212 12 00000 - 00FFF

1M*8 1048576 220 20 00000 - FFFFF

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Memory Interfacing
 Interface an 8088 microprocessor to a single 2716 (2K x 8) EPROM such
that memory starts at address FF800h.
Start Add = FF800h; Size: 2k (800h)
End Add = FF800h + 800h -1= 0FFFFFh
Address range = FF800h - 0FFFFFh
No. of address line = 11 (A0-A10)
Available address lines =20
No. of Chip =1

8086 Memory Bank

 The 8086 has 20-bit address bus, so it can address maximum 220
or 10,48,576 memory locations.
 Memory is divided into two equal banks to make the possibility
for reading or writing a word in one machine cycle by the
processor.
 The memory for an 8086 is set up in 2 bank, up to 5,24,288
memory locations in each.

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Memory Interfacing
Interface two 4K x 8 EPROMS and two 4K x 8 RAM chips with
8086. Select suitable chips.
Solution:
The CS and IP are initialized to form address FFFF0h after reset
the processor. Hence, this address must be lie in the EPROM.
Device Size Address No of No of Address Selection Data Bus
Range Address lines lines Selection
used remaining

ROM 1 8k x 8 FFFFFh- 13 lines 20 -13 =7 A0 = 0 BHE = 0 D0 - D15

ROM 2
FE000h A0 = 1 BHE = 0 D8 - D15
A0 = 0 BHE = 1 D0 -D7
RAM 1 8K x 8 FDFFFh- 13 lines 20 -13 =7 A0 = 0 BHE = 0 D0 - D15
RAM 2
FC000h A0 = 1 BHE = 0 D8 - D15
A0 = 0 BHE= 1 D0 - D 7

Memory Interfacing
Chip Hex
Address
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

4Kx8 FFFFFh 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ROM (2)
FF000h 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0

To ROM IC 2
4Kx8 ROM FEFFFh 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
(1)
FE000h 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

To ROM IC 1
4K x 8 FDFFFh 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
RAM (2)
FD000h 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0

To RAM IC 2
4K x 8 FCFFFh 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
RAM(1)
FC000h 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

To RAM IC 1

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Memory Interfacing
Decoder Input (3 x 8) Bank Selected
Decimal Chip
A13 BHE A0
0 0 0 0 EVEN+ODD RAM Chip
(Both)

1 0 0 1 ODD RAM chip 1

2 0 1 0 EVEN RAM chip 2
3 0 1 1 ---------- Not selected
4 1 0 0 EVEN+ODD ROM Chip
(Both)
5 1 0 1 ODD ROM chip 1
6 1 1 0 EVEN ROM chip 2
7 1 1 1 -------------- Not selected

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Memory Interfacing

Memory Interfacing

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Memory Interfacing

Memory Interfacing

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Memory Interfacing
Design a memory interface for the 8086 which will provide
256k bytes of SRAM, organized as 128k x 16bits, starting at
address 40000H and using 62256 SRAM chips (32k x 8bit).
Assume that 8086 address, data, status, and control busses are
already de-multiplexed and buffered.
We want 128k x 16 bits i.e. 128k x 16bits → 4 chips for both
the high and low banks.
8 chips total
62256 chips are 32k x 8 bit; 32k = 25 x 210 ← 15 address lines
We will use a 2-to-4 decoder (74LS139) to select one out of
four chips from each bank.

Interfacing I/O Ports

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Input-Output port Interfacing

• I/O ports are the devices through which the microprocessor
communicates with external source/destination.
• Input-devices can only be read and an output device (accept data from
the microprocessor) can only be write (IORD or IOWR).
• IN and OUT instructions are used to read and write the data from/to
port respectively in case I/O mapped.
• On the execution of an OUT instruction, data appears on the data bus
and simultaneously a device select signal is generated from the address
and control signals.
• Latch is considered as an good output port which holds the data put
into it, 1 or 0, until cleared. Now, if the data is to be there, at the output
of the device till the next change, it must be latched.
• A buffer is considered as an input port (either analog or digital), to
increase the power of the input signal without changing the value.

Input-Output Interfacing
• The chip 74LS373 is used as an 8 bit Output port. It contains 8 buffered latches to hold
the 8-bit data at the output port till the next change.
• The chip 74LS245 is used as an 8 bit input port. It contains eight tri-state bidirectional
buffer, only one direction (D=1; A (I/P)  B (O/P) is useful while using as an input
device.

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Input-Output Interfacing
The following steps are performed to interface a general I/O device with
a CPU:
(i) Connect the data bus of the microprocessor system with the data
bus of the I/O port.
(ii) Derive a device address pulse by decoding the required address of
the device and use it as the chip select of the device.
(iii) Use a suitable control signal, i.e. IORD and/or IOWR to carry out
device operations, i. e. Connect IORD to RD input of the device if it is
an input device, otherwise connect IOWR to WR input of the output
device. In some cases the RD or WR control signals are combined
with the device address pulse to generate the device select pulse.

Input-Output Interfacing
Problem 5.6: Interface an input port 74LS245 to read the status of the switches SW1 to SW8.
The switches when shorted input a '1' else input a '0' to the 8086 microprocessor. The store
the status in register BL. The address of the port is 0740H.
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0

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Input-Output Interfacing
Problem: Interface an input port 74LS245 to read the status of the switches SW1 to
SW8. The switches when shorted input a '1' else input a '0' to the 8086
microprocessor. Store the status in register BL. The address of the port is 0740H.
MOV BL, 00H ; Clear BL for Status
MOV DX, 0740H ; 16 bit port address in DX
IN AL, DX ; Read port 0740H for the switch positions
MOV BL, AL ; Store the status of switches from AL into BL
HLT ; Stop
• The address, control and data lines are assumed to be readily available at
the microprocessor systems.
• LSB of BL corresponds to the status of SW1 and likewise the MSB of BL
corresponds to the SW8.
• A lot of hardware is required to decode the port address absolutely. For
hardware design, instead of decoding the address completely, only a part
of it may be decoded.

Input-Output Interfacing
Problem : Design an interface of an input port 74LS245 to read the status of switches SW1 to
SW8 and an output port 74LS373 with 8086. Display the number a key that is pressed, i.e. from 1
to 8 on a 7 Segment display with help of the output port write an ALP for this task assume that
only one key is pressed at a time. Draw the schematic of the required hardware. The input port
address 0008H and the output port address is 000AH.

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Input-Output Interfacing
Write an ALP for this task assume that only one key is pressed at a time. The
input port address 0008H and the output port address is 000AH.
MOV BL, 00H ; Clear BL for Switch status
MOV CL, 00H ; Clear CL for Switch Number
XOR AX, AX ; Clear accumulator and Flag
IN AL, 08H ; Read Switch Status
INC CL ; Increment CL for first Switch
YY: ROR AL, 01h ; Rotate switch status
JC XX ; If carry, jump to label XX
INC CL ; Else increment CL for next switch
JMP YY ; Number till carry is 1
XX: MOV AL,CL ; Take switch number into AL
OUT 0AH, AL ; Out BCD switch number for Display
HLT ; STOP

Input-Output Interfacing
Problem: Using 74LS373 output ports and 7-segment displays, design a
seconds counter that counts from 0 to 9. Draw the suitable hardware
schematic and write an ALP fro this problem. Assume that a delay of 1
sec is available as a subroutine. Select the port address suitably.

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Input-Output Interfacing
Problem: Draw a schematic hardware circuit for interfacing five, 7-segment
displays with 8086 using output ports. Display numbers 1 to 5 on them
continuously (common cathode) with 8086 using output ports. The 7
segment codes are stored in a look-up table serially at the address
2000:0000H onwards starting from code for 1.

Input-Output Interfacing

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Input-Output Interfacing
MOV AX, 2000H ;
MOV DS, AX ;
MOV BX, 0000H; Initialize code table with
DS:BX
Next: MOV AL, 00H; Get first number from the
table
MOV DH, AL
MOV CL, 05H; Count for the display
MOV DL, 01H; Selection code for first display
AGAIN: XLAT; translate the code
OUT 04H, AL;
ROL DL, 01H;

Input-Output Interfacing
Problem: Interface an input port 74LS245 to read the status of the
switches SW1 to SW8. The switches when shorted input a '1' else input a
'0' to the 8086 microprocessor. The store the status in register BL. The
address of the port is 0740H.

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Input-Output Interfacing
Problem 5: Interface an input port 74LS245 to read the status of the
switches SW1 to SW8. The switches when shorted input a '1' else input a
'0' to the 8086 microprocessor. The store the status in register BL. The
address of the port is 0740H.

Intel 8255: Programmable Peripheral Interface

• The 8255A is a general purpose programmable I/O device designed to transfer the data from
I/O to interrupt I/O under certain conditions as required. It can be used with almost any
microprocessor.
• It consists of three 8-bit bidirectional I/O ports (24 I/O lines) which can be configured OR
programmed as per the requirement.
• It has three PORT A (PA0-PA7) , PORT B (PB0-PB7) and PORT C (PC0-PC7) i.e. total 24
input/output lines.
• Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper (PC7-PC4)
by the control word.
• These three ports are further divided into two groups, i.e. Group A includes PORT A and
upper PORT C. Group B includes PORT B and lower PORT C.
• Port functioning are independent to each other either use as input or output port. It is
achieved with the use of Control Word Register (CWR) which is the internal register of 8255.
• It includes an 8-bit bidirectional data bus D0-D7. Over these lines commands, status
information, and data are transferred between CPU (8086) and 8255.

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PPI 8255: Pin and Architecture

RESET: A high on this input pin clears the control register and all ports (A, B & C) are set to input
mode.
Read/Write and Control Logic: The function of this block is to manage all of the internal and
external transfers of both Data and Control or status words.
Data Bus Buffer: This 3-state bidirectional 8-bit buffer is used to interface the 8255A to the system
data bus. Data is transmitted or received by the buffer upon execution of input or output
instructions by the CPU. Control words and status information are also transferred through the data
bus buffer.

PPI 8255: Port Selection and Decoding

CS: A “low” on this input pin enables the
communication between the 8255A and
the CPU.
RD: A “low” on this input pin enables
the 8255A to send the data or status
information to the CPU on the data bus.
In essence, it allows the CPU to “read
from the 8255A.
WR: A “low” on this input pin enables
the CPU to write data or control words
into the 8255A.
A0 and A1 (Port Selection): These input
signals, along with RD and WR inputs,
control the selection of one of the three
ports or the control word registers. They
are normally connected to the least
significant bits of the address bus (A0
and A1)

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PPI 8255: Modes of Operation

BSR Mode of Operation:
• Only port C (PC0- PC7) to set or reset its individual
port bits.

PPI 8255: Modes of Operation

To access either a port or the control register of the
82C55A/8255, CS must be active. Then the code A1A0 selects
the port or control register to be accessed.
8255A has three different operating modes:
Mode 0 (Basic Input/Output) – This functional configuration
provides simple input and output operations for each of the
three ports. No “handshaking is required, data is simply
written to or read from a specified port.
• Any port can be input or output.
• Outputs are latched.
• Inputs are not latched.
• 16 different Input/Output configurations are possible in
this Mode.

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PPI 8255: Modes of Operation

Mode 1 (Strobed Input/Output) – This functional configuration provides a means for transferring I/O
data to or from a specified port along with strobes or handshaking signals. In mode 1, port A and port B
use the lines on port C to generate or accept these “handshaking signals.
• Two Groups (Group A and Group B) Any port can be input or output.
• Each group contains one 8-bit data port and one 4-bit control/data port.
• The 8 bit data port can be either input or output. Both inputs and outputs are latched.
• The 4-bit port is used for control and status of the 8-bit data port.

Example: A CPU wants to transfer data to a printer. In this case since speed of processor is very fast as
compared to relatively slow printer, so before actual data transfer it will send handshake signals to the
printer for synchronization of the speed of the CPU and the peripherals.

PPI 8255: Modes of Operation

Mode 2 (Bi-directional Bus) - In this mode, Port A can be
configured as the bidirectional port and Port B either in Mode
0 or Mode 1. Port A uses five signals from Port C as
handshake signals for data transfer. The remaining three
signals from Port C can be used either as simple I/O or as
handshake for port B.

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PPI 8255: Modes of Operation

Control word Register and Mode Selection

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Control word Register and Port status

What is the mode and I/O
configuration for ports A, B, C of an
8255/82C55A after its control
register is loaded with 82H.

Control word Register and Port status

Problem: Interface an 8255 with 8086 to work as an I/O port. Initialize port A as output port, port B as input port and
port C as output port. Port A address should be 0740H. Write a program to sense switch positions SW0-SW7 connected
at port B. The sensed pattern is to be displayed on a port A, to which 8 LEDs are connected, while the port C lower
displays number of ON switches out of the total eight switches.
Solution: For the given requirement, the control word should be loaded with 82h.

D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 1 0

Address Mapping table:

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8086 Interfacing with 8255A

MOV DX, 0746H
MOV AL, 82H
OUT DX, AL
SUB DX, 04
IN AL, DX
SUB DX, 02
OUT DX, AL
MOV BL, 00H
MOV CH, 08H
YY: ROL AL,01h
JNC XX
INC BL
XX: DEC CH
JNZ YY
MOV AL, BL

8086 Interfacing with 8255A

Problem: Interface 16-bit 8255
ports with 8086. The address of
port A is F0h.
Solution: For implementing a 16-
bit port, two 8255 IC are required.
One will act as the lower 8-bit port,
i.e. D0-D7, while the other will act
as the upper 8-bit port D8-D15.
While initializing AL and AH (AX)
both should be loaded with a
suitable (common) control word. In
this system, port A, port B and port
C all may work as 16-bit ports.

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8255A: Modes of Operation

Interrupt Control Functions:
When the 8255A is programmed to operate in mode 1 or mode 2,
control signals are provided that can be used as interrupt request inputs
to the CPU. The interrupt request signals, generated from port C, can be
inhibited or enabled by setting or resetting the associated INTE flip-flop,
using the bit set/reset function of port C.
This function allows the Programmer to disallow or allow a specific I/O
device in the interrupt structure.
INTE flip-flop definition:
(BIT-SET)- INTE is set - Interrupt enable
(BIT-RESET)- INTE is RESET- Interrupt disable.
Note:- All mask flip-flops are automatically reset during mode selection
and device Reset.

8255A: Modes of Operation

Input Control Signal Definition Mode 1 Operation of 8255: Port A as Input Port
STB (Strobe Input):
• A “low” on this input loads data into
the input latch.
IBF (Input Buffer Full F/F):
• A “high” on this output indicates that
the data has been loaded into the
input latch; in essence, an
acknowledgement .
• IBF is set by STB input being low and is
reset by the rising edge of the RD
input.
INTR (Interrupt Request) :
• A high on this output can be used to
interrupt the CPU when an input
device is requesting service. INTR is a
“one” .

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8255A: Modes of Operation

Mode 1: Port A as an Input Port (Timing diagram)

8255A: Modes of Operation

Output Control Signal Definition Mode 1 Operation of 8255: Port A as an Output Port
OBF (Output Buffer Full F/F):
• A OBF output will go low to indicate that the CPU
has written data out to the specified port.
• The OBF F/F will be set (low) by the rising edge of
the WR input and reset (high) by ACK input being
low.
ACK (Acknowledge Input):
• A “low” on this input informs the 8255A that the
data from port A or port B has been accepted.
• In essence, a response from the peripheral device
indicating that it has received the data output by
the CPU.
INTR (Interrupt Request) :
• A “high” on this output can be used to interrupt
the CPU when an output device has accepted
data transmitted by the CPU.
• INTR is set when ACK is a one, OBF is a one and
INTE is a one. It is reset by the falling edge of WR

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8255A: Modes of Operation

Mode 1: Port A as an Output Port (Timing diagram)

8255A: Modes of Operation

Mode 1 Operation of 8255: Port A and B as an Input Port

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8255A: Modes of Operation

Mode 1: Port A and B as an Output Port

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