CND 221

ADVANCED FULL CUSTOM VLSI DESIGN

LAB 10: ALU System Integration

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Contents
OBJECTIVE: ....................................................................................................................................................................................... 3
ALU BLOCK DIAGRAM: ..................................................................................................................................................................... 3
CONTROL UNIT:................................................................................................................................................................................ 4
BARREL SHIFTER: .............................................................................................................................................................................. 5
RIPPLE CARRY ADDER: ...................................................................................................................................................................... 6
MUX SELECTION: .............................................................................................................................................................................. 7
SIMULATION TB: .............................................................................................................................................................................. 8

List of Figures
Figure 1 4-bit ALU block diagram ......................................................................................................................... 3
Figure 2 The control unit block diagram ................................................................................................................ 4
Figure 3 Decoder and Tri-state buffer layout ......................................................................................................... 4
Figure 4 The layout of the control unit ................................................................................................................... 4
Figure 5 4-bit Barrel Shifter schematic diagram a) rotate right operation b) arithmetic shift operation ................ 5
Figure 6 Layout of the Arithmetic Barrel Shifter ................................................................................................... 5
Figure 7 4-bit ripple carry adder block diagram ..................................................................................................... 6
Figure 8 1-bit adder ................................................................................................................................................ 6
Figure 9 Layout of the4-bit ripple carry adder ....................................................................................................... 6
Figure 10 Schematic diagram for the 8-bit MUX................................................................................................... 7
Figure 11 Schematic diagram for the 4 to 1 (1-bit) MUX ...................................................................................... 7
Figure 12 Layout of the (4 to 1) 8-bit MUX........................................................................................................... 7
Figure 13 ALU Testbench block diagram .............................................................................................................. 8
Figure 14 Case 1, Adding A+B = 10001 ................................................................................................................ 8
Figure 15 Case 2 Arithmetic Shifting A>>B .......................................................................................................... 8

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OBJECTIVE:
The purpose of this laboratory exercise is to provide students with a comprehensive understanding of integrating
various arithmetic blocks to form a low power 4-bit Arithmetic Logic Unit (ALU). The ALU is designed using
custom circuitry. The lab manual will guide students through a detailed step-by-step process, starting from
creating the top-level schematic, designing the layout for the integrated system, and conducting simulations to
test its functionality.

ALU Block Diagram:

Figure 1 depicts the schematic of the low power 4-bit ALU system with three mathematical operations; Addition,
Arithmetic shifting and Rotating right. The ALU inputs are two 4-bit operands A and B and a 5-bit operation
code (OP). The least significant bit of the operation code (OP[1:0]) is responsible for selection the operation need
to be done, however OP[3:2] are the key used in the shifter (Rotate and Arithmetic shift operations). Finally, a
MUX is used to select which output result will be represented.

NOTE: In this design, the OP code is 5-bit. However, only 4-bit are used and the extra redundant bit for the future
use.

Figure 1 4-bit ALU block diagram

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Control Unit:
The control unit presented in Figure 2 is designed to be a low-power which works only while an operation
decoded; otherwise it will be off. It consists of a 2-4 bit decoder that decodes the OP code and the output values
will be the enable signals of the tri-state buffers which control the operand transmission to the following blocks.
Find the layout of both 2-4 decoder and the 4-bit tri-state buffer at Figure 3. The layout for the control unit is
shown at Figure 4.

Figure 2 The control unit block diagram

Figure 3 Decoder and Tri-state buffer layout

Figure 4 The layout of the control unit

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Barrel Shifter:
The barrel shifter operations are illustrated in detail previously in lab 4 – part 2. Check it back to refresh your
mind. Schematic diagrams for both 4-bit barrel arithmetic shifting and rotate right operations are shown in
Figure 5. The layout of the Arithmetic Barrel Shifter is also represented at Figure 6.

Figure 5 4-bit Barrel Shifter schematic diagram a) rotate right operation b) arithmetic shift operation

Figure 6 Layout of the Arithmetic Barrel Shifter

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Ripple Carry adder:
Figure 7 reveals the 4-bit ripple carry adder which comprises of four cascaded 1-bit adders –refer to Figure 8 –.
The OP [3:2] is the selector that chooses which output will be represented. The layout for the adder is displayed
at Figure 9.

Figure 7 4-bit ripple carry adder block diagram

Figure 8 1-bit adder

Figure 9 Layout of the4-bit ripple carry adder

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MUX selection:
The multiplexer used in the MUX selection block is (4 to 1) 8-bit MUX. OP[3:2] is the selector that chooses
which output will be represented as depicted in Figure 10. The MUX is combined from eight 4 to 1 (1-bit)
MUXs –See Figure 11–. The layout of the (4 to 1) 8-bit MUX is presented at Figure 12.

Figure 10 Schematic diagram for the 8-bit MUX

Figure 11 Schematic diagram for the 4 to 1 (1-bit) MUX

Figure 12 Layout of the (4 to 1) 8-bit MUX

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Simulation TB:
Figure 13 shows the block diagram for the simulation TB of the 4-bit ALU. Two different test cases are tested
using the same input patterns for A = 1101 and B = 1100. Case 1 is addition (A + B) and Case 2 is arithmetic
shifting (A>>B).

Figure 13 ALU Testbench block diagram

Figure 14 Case 1, Adding A+B = 10001

Figure 15 Case 2 Arithmetic Shifting A>>B

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