Counters

A digital counter is a set of flip-flops whose states changes in response to pulses applied at the input to
the counter. The flip-flops are so interconnected that their combined state at any instant is the binary equivalent
of the total number of pulses that have occurred up to that instant. Counters can be used for,
• Counting pulses
• Frequency division
• Providing time delays
• Generation of non-sequential pulses
• Generation of pulse trains
• Counting frequency, etc
Depending upon overall triggering counters are classified into two types, asynchronous and
synchronous. In asynchronous type all the flip-flops are not triggered simultaneously. It is also called ripple
counter since the signal travels through the system just like ripple moving on water surface. It is also known
as serial or series counter.
In synchronous counter all the flip-flops are clocked at the same time.
In terms of mode of counting, counters are of 2 types, up counter and down counter. An up counter
counts in the upward direction 0,1,2,3,.. N and the down counter counts down N, N-1, N-2, …. 2,1,0.
Each count is called a state of the counter. The number of states through which the counter passes before
returning to starting is called the modulus of the counter. An n bit counter have n flip-flops and 2n states. It
divides the frequency by 2n. So it is a divide by 2n counter.

The counter that goes through all possible states before restarting is
called full modulus counter. When the maximum number of states is variable it
is variable modulus counter. The final state of counting is called terminal
count. The modulus of a counter can be shortened by suitable means. One problem
with shortened modulus counter is lock-out. Sometimes when the counter is switch-on or any time during
counting because of noise spikes the counter lands in one of the invalid states and moves through them never
returning to the normal states. The unwanted states called invalid states can be bypassed
by suitable feedback networks. This is lock-out and to avoid this suitable circuits are used.
Counters with lock-out problem are not self-starting. A counter is said to be self starting if it returns to a valid
state and counts normally after one or more clock pulses, even if it enters an invalid state.
The number of flip-flops required to construct a mod-N counter equals
the smallest n for which N ≤ 2n. The LSB of any counter is that bit that changes most often.
Counters of different modes can be combined to get higher mode counter. Mod-M and mod-N counters
can be combined to get mod-MN counter. Such cascading is called full modulus cascading.
Asynchronous counters
2-bit up- counter with negative edge triggered flip-flops
It consists of 2 F.Fs and it counts in the order 00, 01, 10, 11, 00,… …. or 0, 1,2,3,0,….. Initially it is
reset to 00. Using logic diagram and timing diagram the working can be explained. For constructing counters
generally T flip-flops are used. The inputs of all flip-flops are connected to high state. During negative
transition each flip-flop toggles. The first flip-flop is given a clock signal and the Q o/p of each flip-flop clocks
the next flip-flop. By adding more flip-flops higher modulus counters can be formed.

Fig: 01 2-bit up- counter with ─ ve edge triggering & Timing diagram

2-bit down- counter with negative edge triggered flip-flops

This counter counts in the order 00, 11, 10, 01, 00, …or 0,3,2,1,0,3,…. Initially all the flip-flops are
reset. The inputs of all flip-flops are connected to high state. During negative transition each flip-flop toggles.

The first flip-flop is given a clock signal and the o/p of each flip-flop clocks the next flip-flop. By adding
more flip-flops higher modulus counters can be formed.

Fig: 02 2-bit down- counter with ─ ve edge triggering & Timing diagram
2-bit up/down counter with negative edge triggered flip-flops
It is called bidirectional counter. Mode signal M= 1 for up counting and M= 0 for down counting. When

mode signal M =1, Q o/p of each flip-flop clocks the next flip-flop. When mode signal M = 0, o/p of each
flip-flop clocks the next flip-flop.

Fig:03 Logic diagram of 2-bit up/down counter & Timing diagram

We can use +ve edge triggered flip-flop for Up / down counters. In up counter output of each flip-flop is
used to clock the next flip-flop. In down counter Q o/p of each flip-flop clocks the next flip-flop.
By adding mode signal Up/ down counter can be formed.
Example : Construct a mod-8 ripple counter.
Here 8 = 23. So 3 F.Fs are needed. The counting sequence is given below,

No. of Count
pulses Q3 Q2 Q1
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

Fig:05 logic diagram of mod-8 counter & Timing diagram

Cascading of counters
To increase the modulus counters can be cascaded. By cascading a mod-M counter and mod-N counter
a mod- MN counter results. The frequency division is not affected by order of cascade. The output frequency
in a mod-8 counter is fin / 8. In a mod -12 counter it is fin / 12.
The o/p frequency is fin / 24 in mod-6 X mod-4 as well as mod-4 X mod-6 counters.
Propagation delay in counters
All flip-flops have some propagation delay. In ripple counters these delays accumulate as the count
advances and this may lead to skipping of certain counts. This is more evident when clock frequency is high.
Suppose Tpd be the propagation delay of one stage. Due to accumulation of delays the system may skip some
state say 1000 after 0111 and go directly to 1001. Thus it affects accuracy. So a ripple counter imposes some
limitation on the frequency of clock pulses.
Suppose Tc is the period of clock pulses and n, the number of stages and Tpd is the delay in each stage. For

preventing skipping of stages, the clock frequency fc = < . or Tc > nTpd

Synchronous counters
Serial counters are slow and in them each flip-flop is clocked by the output of previous flip-flop. In
synchronous counters all the flip-flops are clocked simultaneously and the
state change of flip-flop depends on inputs like S-R, J-K, D, T …. Here overall propagation delay is equal to
that of a single flip-flop + that of gates. So parallel counters operate at higher frequency than serial counters.
Four bit synchronous up counter
This counts up in the order 0000, 0001,0010,… In a ripple counter the time delay is 4 Tpd for 1000—
1001 transition. But in parallel counter t is Tpd itself.

Fig :10 4 bit synchronous up-counter & waveforms.

Four bit synchronous down counter
It counts in the order 0000, 1111, 1110, ….. 0001,0000.

Fig: 11 4 bit synchronous down -counter

Look ahead carry

In the four bit counters discussed above the terms Q1Q2, Q1Q2 Q3 etc are called carry. They are brought
forward to each stage and they ripple through the successive AND gates. The propagation delay of these AND
gates accumulate and this cumulative delay limits the counting speed of synchronous counter. To remedy this
speed limitation of synchronous counters IC versions use the look ahead carry method. Here the carries are
forwarded simultaneously to all the succeeding
AND gates thereby eliminating the accumulation of delay. So the total delay is the delay of a single flip-
flop plus that of a gate.
 Fig: 12 Synchronous counters using look ahead carry method.

Comparison of synchronous and asynchronous counters

1. In serial counters all the flip-flops do not change simultaneously. Outputs of preceding flip-flops act as
the clock signals of succeeding F.Fs. Here the clock signal travel in a serial manner just like ripple on
liquid surface.
In synchronous counters all the flip-flops are clocked simultaneously. Flip-flops are parallel as far as
clock signal is concerned.
2. In ripple counters there is accumulation of propagation delay and this may lead to skipping of counts
with increase in clock frequency and number of stages of flip-flops.
In parallel counters Tpd of individual flip-flops do not get added up and the total delay is always equal
to sum of Tpd of flip-flop and that of gate.
3. Parallel CTRs have the advantage of high speed and minimum decoding problem but the disadvantage
of complex circuit than asynchronous counters.
4. Parallel CTRs of any count sequence other than normal count can be easily designed but it is not so easy
in ripple CTRs.
5. Many IC counters are pre-settable, that is one can preset to any desired count either synchronously or
asynchronously. This presetting is called loading of the counter.

Applications of counters
Digital counters can be used for a number of applications. Some of them are,
Digital clock:
For accurate time measurement, a digital clock requires a stable clock frequency. In battery operated
device a crystal is used for this. In line operated clocks, the 50Hz line frequency is used as the basic clock
frequency. The 50Hz signal is passed through wave shaping circuits to produce square pulses at the rate of 50
pps. This is fed to mode 50 counter to produce 1pps signal. This is fed to seconds section of clock which counts
and display seconds 0—59.
This section consists of a BCD counter and display for units and a mod-6 counter and display for tens. After
9 seconds BCD counter resets to 0 and triggers a mod-6 counter. After count 59, the BCD and mod-6 counters
reset and triggers minute section which is similar to seconds section and counts up to 59 minutes. After 59
minutes the system triggers the hour section. The hour section consists of a BCD counter and a mod-2 counter
with special features. After 12 or 24, the mod-2 resets to 0 and BCD resets to 1 to produce 01.
Parallel to serial data conversion:
Parallel data is a group of bits appearing simultaneously on parallel lines. Serial data is a group of bits
appearing on a single line sequentially. A counter, multiplexer combination can be used for parallel – serial
conversion. To convert an 8 bit parallel data, the output of a mod-8 counter is connected to the data select
inputs of an 8-1 multiplexer. As the counter moves through the binary sequence of 000 – 111, each bit from
D0 is selected sequentially and passed through the MUX to the output line. So after 8 clock pulses the parallel
form is converted into serial format and sent out to the output line. After this the counter recycles back to 0
and handles the next byte.
Frequency counter:
It is a circuit used to measure and display frequency of a signal. It consists of a counter with its
associated decoder/ display and an AND gate. The inputs of AND gate are unknown frequency signal and a
sample pulse. The sample pulse decides how long the unknown pulses are allowed to pass through the AND
gate into the counter. The counter is made up of cascaded BCD counters.
A decoder / display unit converts the BCD outputs into decimal display.

1. Distinguish between asynchronous counters and synchronous counters.(3)(2020)

2. Explain the synchronous counters with its advantages and disadvantages. Write the design steps of
synchronous counter with excitation of various flip flops. (2019) (12)
3. (a)Why are asynchronous counters also called ripple counters? (b) Compare synchronous counters and
asynchronous counters. (c) A binary ripple counter is required to count up to 16,383 . How many flip
10

flops are required? If the clock frequency is 8.192MHz, what is the frequency at the output of the MSB.
(1-3-5) (2017)
4. What are the advantages and disadvantages of ripple counters. Explain the construction and working
of a mod-8 ripple counter. What is problem of lock out? How is it eliminated? (12) (2016)
5. Distinguish between asynchronous counters and synchronous counters. Design a mod 6 asynchronous
counters using T flip flops (TFF). Explain the effects of propagation delay in Ripple counters.(12)
(2015)
6. Explain the function of a 4stage ring counter (5) (2014)