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Energy Reports 9 (2023) 210–217

www.elsevier.com/locate/egyr

2022 The 3rd International Conference on Power and Electrical Engineering (ICPEE 2022)
29–31 December, Singapore

DC-bus voltage balancing control for 3-level DC/DC converters in

renewable generation systems
Wenping Zhanga,b ,∗, Yiming Wangb , Po Xub , Donghui Lia , Baosong Liub
a Tianjin University, 92 Weijin Road Nankai District, Tianjin, 300072, China
b Ginlong Technologies Co., Ltd., 57 Jintong Road, Xiangshan, Ningbo, 315712, China
Received 18 April 2023; accepted 20 May 2023
Available online 31 May 2023

Abstract
This paper investigates the dc-bus voltage balancing for 3-level DC/DC converters. First, the system control diagram is
introduced. Then, based on duty cycle and operating modes, four different cases are illustrated. The output voltages under four
cases are detailed, and the dc-bus voltage balancing actions for different cases are summarized. The dc-bus voltage balancing
situation becomes worse when the system is in the condition of D > 0.5 and DCM. Therefore, three methods are proposed
to solve the issue raised. The first method is to limit D ≤ 0.5. The second method applies an opposite control when D > 0.5
and DCM. The third solution adopts an intelligent control.
© 2023 The Author(s). Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license
(http://creativecommons.org/licenses/by-nc-nd/4.0/).
Peer-review under responsibility of the scientific committee of the 3rd International Conference on Power and Electrical Engineering, ICPEE, 2022.

Keywords: 3-level converter; DC/DC; DC-bus balancing

1. Introduction
3-level converters feature high voltage and high efficiency, which are widely applied for renewable generation
systems, such as PV, and fuel cell systems [1]. The dc-bus voltage balancing is quite challenging, and this issue
becomes worse, when DC/AC side loads are unbalanced and non-linear. It is noted unbalanced dc-bus voltage can
cause several problems. For example, the quality of the DC/AC output is affected with high harmonics, and it
can worsen the voltage stress on semiconductors [2]. Therefore, it is quite important to investigate dc-bus voltage
balancing.
For the dc-bus voltage balancing, following scenarios are normally applied. (1) Increase the dc-bus capacitance,
which brings higher costs. (2) Introduce extra dc-bus balancing converters, which also increases system costs [3,4].
(3) No need to add extra hardware, and only dc-bus voltage balancing control is applied. Presently, this software
scenario is widely adopted for 3-level converters. Numerous papers explore dc-bus balancing control for 3-level
∗ Corresponding author at: Ginlong Technologies Co., Ltd., 57 Jintong Road, Xiangshan, Ningbo, 315712, China.
E-mail address: wenping.zhang@ginlong.com (W. Zhang).

https://doi.org/10.1016/j.egyr.2023.05.174
2352-4847/© 2023 The Author(s). Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license (http:
//creativecommons.org/licenses/by-nc-nd/4.0/).
Peer-review under responsibility of the scientific committee of the 3rd International Conference on Power and Electrical Engineering, ICPEE,
2022.
W. Zhang, Y. Wang, P. Xu et al. Energy Reports 9 (2023) 210–217

DC/AC converters. For carrier modulation, injecting zero-sequence component is widely used [5,6]. For space vector
modulation, applying redundant vectors for dc-bus voltage balancing is considered as an effective method [7,8].
Furthermore, some researchers focus on how to reduce negative effects of the dc-bus voltage balancing, such
as efficiency. Generally, current research is mainly for 3-level DC/AC converters, and there are quite few papers
focusing on DC/DC converters [9]. Therefore, this paper investigates the dc-bus voltage balancing for 3-level DC/DC
converters.

2. System control architecture

Fig. 1 presents the control diagram for a 3-level DC/DC system. The control system includes voltage sum loop,
current loop, voltage difference loop, and duty cycle generation. The voltage sum loop maintains the dc-bus voltage
sum, while the voltage difference loop maintains the dc-bus voltage difference. There are two switches (S1 , S2 ). The
duty cycle sum of these two switches dsum is generated by the voltage sum loop, while the duty cycle difference
ddi f is generated by the voltage difference loop. It is noted the DC/DC converter can be in different operating
conditions. For example, when the input voltage vin varies, the duty cycle changes. Also, when the output power
changes, the system can be in discontinuous conduction mode (DCM) or continuous conduction mode (CCM). For
different operating conditions, the dc-bus balancing control is different. The following analyses the dc-bus balancing
for different cases.

Fig. 1. Control diagram for a 3-level DC/DC converter.

3. Analysis on four cases

Suppose the input voltage is vin and the output dc-bus voltage is vdc equal to vdc1 + vdc2 , define the duty cycle
D is vdc /vin . Then, based on the duty cycle D and the operating mode (DCM/CCM), there are four different cases
(see Fig. 2).

Fig. 2. Operating diagram (a) D ≤ 0.5 and CCM; (b) D > 0.5 and CCM; (c) D ≤ 0.5 and DCM; (d) D > 0.5 and DCM.

3.1. Case 1: D ≤ 0.5 and CCM

Fig. 2(a) presents the condition of D ≤ 0.5 and CCM. There are 4 stages, and the details are shown in Fig. 3.
In stage ⃝ 1 (Fig. 3(a)): S1 is ON and S2 is OFF, and the time duration is d1 Ts . In stage ⃝
2 (Fig. 3(b)): S1 is OFF
and S2 is OFF, and the time duration is (0.5-d1 )Ts . In stage ⃝ 3 (Fig. 3(c)): S1 is OFF and S2 is ON, and the time
duration is d2 Ts . In stage ⃝
4 (Fig. 3(d)): S1 is OFF and S2 is OFF, and the time duration is (0.5-d2 )Ts . The average
current of i L during one switching cycle is ⟨i L ⟩Ts . From Fig. 3, the upper capacitor Cdc1 is charged during stages
⃝2 ⃝
3 ⃝.
4 Also, the lower capacitor Cdc2 is charged during stages ⃝ 1 ⃝
2 ⃝.
4 Therefore, the output voltages vdc1 and
vdc2 can expressed as (1).
vdc1 = ⟨i L ⟩Ts × (1 − d1 ) Ts /Cdc1
{
(1)
vdc2 = ⟨i L ⟩Ts × (1 − d2 ) Ts /Cdc2
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Fig. 3. Four stages (D ≤ 0.5 and CCM) (a) stage⃝:

1 d1 Ts ; (b) stage⃝:
2 (0.5−d1 )Ts ; (c) stage⃝:
3 d2 Ts ; (d) stage⃝:
4 (0.5−d2 )Ts .

From (1), the dc-bus voltage balancing can be achieved by regulating the duty cycle d1 and d2 . When vdc1 is
higher, increase d1 and decrease d2 to balance vdc1 and vdc2 . Similarly, when vdc2 is higher, increase d2 and decrease
d1 .

3.2. Case II: D> 0.5 and CCM

Fig. 2(b) presents the operating diagram under D > 0.5 and CCM, and the detailed diagrams are shown in Fig. 4.

Fig. 4. Four stages (D > 0.5 and CCM) (a) stage⃝:

1 (d2 −0.5)Ts ; (b) stage⃝:
2 (1−d2 )Ts ; (c) stage⃝:
3 (d1 −0.5)Ts ; (d) stage⃝:
4 (1−d1 )Ts .

From Fig. 4, the upper capacitor Cdc1 is charged during stage ⃝. 4 Also, the lower capacitor Cdc2 is charged
during stage ⃝.
2 Therefore, the output voltages vdc1 and vdc2 can expressed as (2).
vdc1 = ⟨i L ⟩Ts × (1 − d1 ) Ts /Cdc1
{
(2)
vdc2 = ⟨i L ⟩Ts × (1 − d2 ) Ts /Cdc2
From (2), when vdc1 is higher than vdc2 , increase d1 and decrease d2 to balance vdc1 and vdc2 . Similarly, when
vdc2 is higher than vdc1 , increase d2 , and decrease d1 , which can balance vdc1 and vdc2 .

3.3. Case III: D ≤ 0.5 and DCM

Fig. 2(c) presents the operating diagram under D ≤ 0.5 and DCM, and the detailed diagrams are shown in Fig. 5.
From Fig. 5, the upper capacitor Cdc1 is charged during stages ⃝ 1 ⃝2 ⃝.
4 Also, the lower capacitor Cdc2 is charged
during stages ⃝ 2 ⃝ 4 It is noted that in stages ⃝
3 ⃝. 4 the current is dropped to zero. Thus, the charge for the dc-bus
2 ⃝,

capacitors in stage ⃝2 and ⃝ 4 is Q1 Q2 , respectively, as shown in Fig. 2(c). Therefore, the output voltages vdc1
and vdc2 can expressed roughly as (3). In (3), I L p1 is the peak current in stage ⃝ 1 and I L p2 is the peak current in

stage ⃝3 as shown in Fig. 2(c).

Vdc1 = (0.5Q 1 + 0.5I L P2 d2 TS + 0.5Q 2 ) /Cdc1

{
(3)
Vdc2 = (0.5I L P1 d1 TS + 0.5Q 1 + 0.5Q 2 ) /Cdc1
From (3), Vdc1 increases with increasing of d2 , and Vdc2 increases with increasing of d1 . When vdc1 is higher,
increase d1 and decrease d2 , which can balance vdc1 and vdc2 . Similarly, when vdc2 is higher, increase d2 and decrease
d1 .
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Fig. 5. Four stages (D ≤ 0.5 and DCM) (a) stage⃝:

1 d1 Ts ; (b) stage⃝:
2 (0.5-d1 )Ts ; (c) stage⃝:
3 d2 Ts ; (d) stage⃝:
4 (0.5-d2 )Ts .

3.4. Case IV: D> 0.5 and DCM

Fig. 2(d) presents the operating diagram under D > 0.5 and DCM, and the details are in Fig. 6. From Fig. 6,
the upper capacitor Cdc1 is charged during stage ⃝. 4 Also, the lower capacitor Cdc2 is charged during stage ⃝. 2 In
stages ②④, the current is dropped to zero. Thus, the charge for the dc-bus capacitors in stage ② and ④ is Q1 and
Q2 , respectively, (see Fig. 2(d)). Note Q1 is proportional to I L P1 , and Q2 is proportional to I L P2 . Furthermore, I L P1
is proportional to the duration (d2 −0.5)Ts , and Q2 is proportional to (d1 −0.5)Ts . Therefore, the output voltages vdc1
and vdc2 is roughly as (4).
Cdc1 Vdc1 = Q 2 , ∝ I L P2 , ∝ (d1 − 0.5)
{
(4)
Cdc2 Vdc2 = Q 1 , ∝ I L P1 , ∝ (d2 − 0.5)

Fig. 6. Four stages (D > 0.5 and DCM) (a) stage⃝:

1 (d2 −0.5)Ts ; (b) stage⃝:
2 (1−d2 )Ts ; (c) stage⃝:
3 (d1 −0.5)Ts ; (d) stage⃝:
4 (1−d1 )Ts .

From (4), when vdc1 is higher, increase d2 and decrease d1 , which can balance vdc1 and vdc2 . Similarly, when
vdc2 is higher, increase d1 and decrease d2 . Therefore, the voltage balancing action for this case is different. The
above four cases are summarized as shown in Table 1. Therefore, if the same action is applied for four cases, the
dc-bus voltage balancing condition becomes worse when the system is in the condition of D > 0.5 and DCM.

Table 1. Summary for four cases.

Cases DC Bus voltages Voltage balancing action DC Bus voltages Voltage balancing action
D ≤ 0.5, CCM Vdc1 > Vdc2 d1 ↑, d2 ↓ Vdc1 < Vdc2 d2 ↑, d1 ↓
D > 0.5, CCM Vdc1 > Vdc2 d1 ↑, d2 ↓ Vdc1 < Vdc2 d2 ↑, d1 ↓
D ≤ 0.5, DCM Vdc1 > Vdc2 d1 ↑, d2 ↓ Vdc1 < Vdc2 d2 ↑, d1 ↓
D > 0.5, DCM Vdc1 > Vdc2 d1 ↓, d2 ↑ Vdc1 < Vdc2 d2 ↓, d1 ↑

4. Proposed solutions
There are three methods proposed to solve the issue raised earlier.

4.1. Method 1: limit D ⩽ 0.5

Limit the range of the input voltage, and make sure the duty cycle is always less than 0.5. For instance, the input
is PV, and this method can be easily implemented. As shown in Fig. 7, set the lower limit for the MPPT output
V P V limit . Also, V P V limit is set as half of the dc-bus voltage. Then, the case with D > 0.5 will not occur. However,
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Fig. 7. Solution 1.

when the MPPT voltage is lower than V P V limit , the maximum power cannot be achieved, which means some PV
power is missing.

4.2. Method 2: opposite control when D> 0.5 and DCM

As shown in Fig. 8, a channel selection unit is added and the condition for the selection is D > 0.5 and DCM.
When the selection condition is not satisfied, the switch is located at “1”, and the voltage balancing adopted is
applied for cases I∼III. When the selection condition is satisfied, the switch is located at “2”, and the voltage
balancing adopted is applied for cases IV. Therefore, when the system is in D > 0.5 and DCM, the voltage balancing
is opposite to other cases. This solution is easily implemented. However, the challenge is to determine if the system
is in DCM.

Fig. 8. Solution 2.

In solution 2, there are two factors to determine. The first one is to determine the duty cycle, and the second
one is to determine DCM. The duty cycle is easy to obtain, which is bound by the input voltage vin and the dc-bus
voltage vdc . The difficult part is to determine if the system is in DCM. The following introduces two methods.
This first method is based on peak current and duty cycle. First, sample the peak current. As shown in Fig. 9, if
the sampling delay is ∆t, the sample starting time is moved ahead to (d2 −0.5)Ts –∆t. Then, with the peak current
I L p1 and the current dropping rate (Vdc2 –Vin )/L, the timing of the current dropped to zero can be calculated. If the
calculated dropping time is less than (1-d2 )Ts , it can be determined that the system is in DCM. Otherwise, the
system is in CCM.

Fig. 9. Method 1 to determine DCM.

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The second method is based on the average current of the inductor. First, the inductor current passes through a
low-pass filter and then obtain the average current. Meanwhile, the controller calculates the critical current for the
DCM and CCM with the present duty cycle and the input/output voltages. If the sensed average current is less than
the calculated critical current, the system is considered in DCM. Otherwise, the system is in CCM.

4.3. Solution 3: Intelligent control

For solution 2, the challenge is to precisely determine that the system is in DCM. Therefore, solution 3 is
proposed, which does not need to determine whether the system is in DCM. Instead, solution 3 can intelligently
switch between the mode of D > 0.5 and DCM and other modes. As shown in Fig. 10, there is a channel selection
and the condition is D > 0.5, and i L <5%×Irate . Note that 5%× Irate can be set as other values based on different
applications. It represents that the current is small and the system may be in DCM. When the switching condition
is met, the channel is located in “1”. Otherwise, the system is switched to the intelligent switching mode.

Fig. 10. Solution 3.

The diagram for the intelligent switching is shown in Fig. 11. First, determine if the system starts the intelligent
switching. If so, check if the dc-bus voltage difference is over the threshold Vdc di f T . If over the threshold, the
channel selection is switched to “1”, and then stay for 5 switching cycles. Then, record the dc-bus voltage difference
change for these 5 switching cycles and named as ∆Vdc dif1 . Then, the channel selection is switched to “2”, and stay
for 5 switching cycles. Record the voltage difference change for these 5 switching cycles and named as ∆Vdc dif2 .

Fig. 11. Diagram for the intelligent switching.

Compare two voltage difference changes ∆Vdc dif1 and ∆Vdc dif2 . If ∆Vdc dif1 is less than ∆Vdc dif2 , set the channel
at “1”. Otherwise, set the channel at “2”. Then, maintain the position for the following 100 switching cycles. Then,
check if the voltage difference is over the threshold Vdc di f T . If over the threshold, go through the earlier procedure
again. Otherwise, maintain the current position. The advantage of this method is that there is no need to determine
if the system is in DCM, and the system can intelligently switch between two modes.
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5. Verification
The experiment is implemented and the corresponding parameters are as follows. The input voltage is 100 V, and
the output dc-bus voltage is controlled to 800 V. For the light loads, we can calculate that the system is operated
at D > 0.5 and DCM. Also, the upper side load is slightly different with the lower side load, which can generate
the unbalanced load condition.
In Fig. 12(a), the original control strategy is applied. Specifically, when vdc1 is higher, increase d1 , and when vdc2
is higher, increase d2 . It can be seen the current is in DCM and the dc-bus voltage balance cannot be maintained
with the original control strategy. The upper dc-bus voltage can reach roughly 550 V and the lower dc-bus voltage
is maintained as 250 V instead.
In Fig. 12(b), the proposed control strategy is applied instead. It can be seen the current is in DCM and the
dc-bus voltage balance can be maintained with the proposed control strategy. The upper dc-bus voltage and the
lower dc-bus voltage is maintained as 400 V. Thus, from Fig. 12, the proposed method is valid for the case with
D > 0.5 and DCM.

Fig. 12. Experimental results (a) with original control method; (b) with proposed solution 2.

6. Conclusion
This paper investigates the dc-bus voltage balancing for 3-level DC/DC converters. The output voltages under
four cases are detailed, and the dc-bus voltage balancing actions for different cases are summarized. The dc-bus
voltage balancing condition becomes worse when the system is in the condition of D > 0.5 and DCM. Three
methods are proposed to solve the issue raised.

Declaration of competing interest

The authors declare no conflict of interest.

Data availability
Data will be made available on request.

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