Name: Kanoria Shubham Anil BITS ID: 2023HT01569

Assignment – 1 Hardware Software Co-Design

Part 1: Design RGB to Gray converter for 4x4 image.

Here I have considered the 4x4 image in 1D array and passed it to PL for Gray conversion. The
code files are attached separately and images from simulation results are attached below.

Image 1 Shows RGB_2_Gray .v file in project

1
Hardware Software Co-Design Assignment
Name: Kanoria Shubham Anil BITS ID: 2023HT01569

Image 2 Shows RGB_2_Gray Testbench .v file in project

Here, RGB input values are passed using this testbench and RGB to Gray module is initiated.

2
Hardware Software Co-Design Assignment
Name: Kanoria Shubham Anil BITS ID: 2023HT01569

Image 3 Shows Simulation results for RGB to Gray Conversion in project

Above waveform shows the input (RGB) and output (Gray) in 1D and 2D format.

Here, value of input for pixel (0,0) is {25h,87h,91h}

According to Luminosity formula:
G = (0.296875 * R) + (0.58984375 * G) + (0.11328125 * B)
Implying for pixel (0,0) then,
G = (0.296875 * 37) + (0.58984375 * 135) + (0.11328125 * 145)
G = 107.0390 & This is matching with simulation results

3
Hardware Software Co-Design Assignment
Name: Kanoria Shubham Anil BITS ID: 2023HT01569

Part 2: Integrate the RGB to gray converter with the PS

For integrating the converter with PS, I used ZYNQ7 PS and with help of GPIO, series of bits are
transmitted via AXI interconnect. To enable GPIO and parse data to PS, a logic in code is added
as mentioned in below image. The below images show the block diagram for PS and same is also
attached separately.

Image 4 Shows Code line used to parse data to PS via GPIO

design_1 (.op_image_2_ps (gray_img_8_bit_tri_i));

This code line parses the gray image from 1D (1 byte at a time) to PS through GPIO.

4
Hardware Software Co-Design Assignment
Name: Kanoria Shubham Anil BITS ID: 2023HT01569

Image 5 Shows Block Diagram Design for PS

The block diagram above explains the connection between ZYNQ PS7 connected with GPIO via
AXI interconnect and PS reset is used for resetting ZYNQ PS7.
The Processing System (PS) communicates with the Programmable Logic (PL) via the Advanced
eXtensible Interface (AXI). AXI is a high-performance, high-frequency protocol used for
interconnecting components in a System-on-Chip (SoC) design.
The overview of the PS communicating with the PL via AXI is as follows:
AXI Interconnect: The PS and PL are connected through an AXI interconnect. This interconnect
can be configured with various parameters like the number of AXI masters and slaves, data
widths, and arbitration schemes depending on the specific system requirements.

5
Hardware Software Co-Design Assignment
Name: Kanoria Shubham Anil BITS ID: 2023HT01569

AXI Master Interface in PS: In the PS, there are AXI Master interfaces instantiated to
communicate with the PL. These interfaces are typically controlled by the Processing System Unit
(PSU) or the Central Processing Unit (CPU) running software. The CPU can initiate read and write
transactions to the PL using these AXI Master interfaces.
AXI Slave Interface in PL: In the PL, there are AXI Slave interfaces instantiated to communicate
with the PS. These interfaces are typically connected to the custom IP cores or the programmable
fabric of the FPGA. The PL responds to read and write transactions initiated by the PS through
these AXI Slave interfaces.
AXI Transactions: The PS initiates read or write transactions by sending AXI protocol-compliant
signals such as address, data, control, and handshake signals through the AXI Master interfaces.
These transactions can be burst or single transactions depending on the access pattern and
configuration.
PL Response: When the PL receives an AXI transaction from the PS through the AXI Slave
interfaces, it processes the transaction accordingly. For example, if it's a read transaction, the PL
fetches the requested data from internal memory or registers and sends it back to the PS. If it's
a write transaction, the PL updates its internal state or memory with the received data.
Handshaking: AXI protocol involves handshaking signals like read data (RDATA), write response
(BRESP), and acknowledgment signals to ensure data integrity and flow control between the PS
and PL.
Address Mapping: The PS and PL must agree on address mappings to ensure proper addressing
of memory-mapped registers and memory locations in the PL from the perspective of the PS.
Overall, AXI provides a robust and efficient means for communication between the PS and PL in
Xilinx Zynq SoCs.
Therefore, here AXI used for communicating between PS and PL.

6
Hardware Software Co-Design Assignment