Microprocessors and Applications

(BEC-32)

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 Syllabus
Unit-I
Introduction to Microprocessors: Evolution of Microprocessors, Microprocessor
Architecture and its operations, Memory devices, I/O Devices, 8-bit
Microprocessor (8085): Introduction, Signal Description, Register Organization,
Architecture, Basic Interfacing Concepts for Memory and I/O Devices

Unit-II
8085 Assembly Language Programming: Instruction Classification, Instruction
Format, Addressing Modes, 8085 Instructions: Data Transfer operations,
Arithmetic operations, Logic Operations, Branch operation, Flow Chart, Writing
assembly language programs, Programming techniques: looping, counting and
indexing.

Unit-III
16-bit Microprocessors (8086/8088): Architecture, Physical address segmentation,
memory organization, Bus cycle, Addressing modes, difference between 8086 and
8088, Introduction to 80186 and 80286, Assembly Language Programming of
8086/8088.
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Unit-IV
Data Transfer Schemes: Introduction, Types of transmission, 8257 (DMA), 8255
(PPI), Serial Data transfer (USART 8251), Keyboard-display controller (8279),
Programmable Interrupt Controller (8259), Programmable Interval Timer/ Counter
(8253/8254): Introduction, modes, Interfacing of 8253, applications, ADC and DAC

Books & References

1. R. S. Gaonkar: Microprocessor Architecture, Programming and Applications with
8085, Penram Publication

2. R. Singh and B. P. Singh: Microprocessor Interfacing and Application, New Age

International Publishers.

3. D. V. Hall: Microprocessors and Interfacing, TMH (2nd Edition).

4. Y.C. Liu and G.A. Gibson: Microcomputer Systems: The 8086/8088 Family:
Architecture, Programming and Design, PHI 2nd Edition

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EXPERIMENTS

1. Write a program using 8085 Microprocessor for Decimal addition and

subtraction of two numbers.

2. Write a program using 8085 Microprocessor for Hexadecimal addition and

subtraction of two numbers.

3. Write a program using 8085 Microprocessor for addition and subtraction of

two BCD numbers.

4. To perform multiplication and division of two 8 bit numbers using 8085.

5. To find the largest and smallest number in an array of data using 8085
instruction set.

6. To write a program to arrange an array of data in ascending order.

7. To convert given Hexadecimal number into its equivalent ASCII number

and vice versa using 8085 instruction set.
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8. To write a program to initiate 8251 and to check the transmission and
reception of character.

9. To interface 8253 programmable interval timer to 8085 and verify the

operation of 8253 in six different modes.

10. To interface 8255 with 8085 and verify the operation of 8255 in
different modes.

11. To interface 8259 with 8085 and verify the operation of 8259.

12. Serial communication between two 8085 microprocessors through RS-

232 C port.

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 What is Microprocessor?
Microprocessors is a programmable logic
device, designed with registers, flip-flop and
timing elements to perform arithmetic and
logical operation according to given
instructions.

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 Microprocessor based System
Architecture

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 Processor System Architecture
The typical processor system consists of:
▪ CPU (central processing unit)
▪ ALU (arithmetic-logic unit)
▪ Control Logic
▪ Registers, etc…
▪ Memory
▪ Input / Output interfaces
Interconnections between these units:
▪ Address Bus
▪ Data Bus
▪ Control Bus
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 Evolution of Microprocessors

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 Introduction to 8085
 It was introduced in 1977.
 It is 8-bit microprocessor.
 Its actual name is 8085 A.
 It is single NMOS device.
 It contains 6200 transistors
approx.
 Its dimensions are
164 mm x 222 mm.
 It is having 40 pins Dual-
Inline-Package (DIP).
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 Introduction to 8085
 It has three advanced
versions:
◦ 8085 AH
◦ 8085 AH2
◦ 8085 AH1

 These advanced
versions are designed
using HMOS
technology.
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 Salient Features of 8085
1. It is 8-bit microprocessor.
2. It has 16-bit address bus and hence can address up to 216 = 65536
bytes (64KB) memory locations through A0-A15.
3. The first 8 lines of address bus and 8 lines of data bus are
multiplexed AD0 – AD7.
4. Data bus is a group of 8 lines D0 – D7.
5. It supports 5 hardware interrupt and 8 software interrupt.
6. A 16-bit program counter (PC)
7. A 16-bit stack pointer (SP)
8. Six 8-bit general purpose registers( B, C, D, E, H and L)
9. Also arranged in pairs( BC,DE, HL) for 16-bit operands.
10. It requires a signal +5V power supply
11. Maximum Clock Frequency is 3MHz and Minimum Clock
Frequency is 500kHz
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 The 8085 Bus Structure

Address Bus
▪ Consists of 16 address lines: A0 – A15

▪ Operates in unidirectional mode: The address

bits are always sent from the MPU to peripheral
devices, not reverse.

▪ 16 address lines are capable of addressing a

total of 216 = 65,536 (64k) memory locations.

▪ Address locations: 0000 (hex) – FFFF (hex)

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 The 8085 Bus Structure
Data Bus
▪ Consists of 8 data lines: D0 – D7
▪ Operates in bidirectional mode: The data bits are
sent from the MPU to peripheral devices, as well
as from the peripheral devices to the MPU.

▪ Data range: 00 (hex) – FF (hex)

Control Bus
▪ Consists of various lines carrying the control
signals such as read / write enable, flag bits.

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 8085 Microprocessor Architecture

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 The 8085: CPU Internal Structure

The internal architecture of the 8085 CPU is

capable of performing the following operations:

▪ Store 8-bit data (Registers, Accumulator)

▪ Perform arithmetic and logic operations (ALU)

▪ Test for conditions (IF / THEN)

▪ Sequence the execution of instructions

▪ Store temporary data in RAM during execution

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 The 8085: Registers

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 The 8085: CPU Internal Structure
Registers
▪ Six general purpose 8-bit registers: B, C, D, E, H, L

▪ They can also be combined as register pairs to

perform 16-bit operations: BC, DE, HL
▪ Registers are programmable (data load, move, etc.)
Accumulator
▪ Single 8-bit register that is part of the ALU !
▪ Used for arithmetic / logic operations – the result is
always stored in the accumulator.
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 The 8085: CPU Internal Structure
Flag Bits
▪ Indicate the result of condition tests.

▪ Carry, Zero, Sign, Parity, etc.

▪ Conditional operations (IF / THEN) are executed

based on the condition of these flag bits.
Program Counter (PC)
▪ Contains the memory address (16 bits) of the
instruction that will be executed in the next step.
Stack Pointer (SP)
▪ Contains the address (16 bits) of a memory
location in R/M memory, called the stack
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 • S-sign flag
– The sign flag is set if bit D7 of the accumulator is set after an
arithmetic or logic operation.
• Z-zero flag
– Set if the result of the ALU operation is 0. Otherwise is reset. This
flag is affected by operations on the accumulator as well as other
registers. (DCR B).
• AC-Auxiliary Carry
– This flag is set when a carry is generated from bit D3 and passed to
D4 . This flag is used only internally for BCD operations.
• P-Parity flag
– After an ALU operation if the result has an even # of 1’s the p-flag
is set. Otherwise it is cleared. So, the flag can be used to indicate
even parity.
• CY-carry flag
– If an arithmetic operation results in a carry, the carry flag is set
otherwise it is reset. It also severs as a borrow flag for subtraction.

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 The 8085: CPU Internal Structure

Simplified block diagram

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 Example: Memory Read Operation

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 Cycles and States
– T- State: One subdivision of an operation. A T-
state lasts for one clock period.
• An instruction’s execution length is usually
measured in a number of T-states. (clock
cycles).
– Machine Cycle: The time required to complete one
operation of accessing memory, I/O, or
acknowledging an external request.
• This cycle may consist of 3 to 6 T-states.
– Instruction Cycle: The time required to complete
the execution of an instruction.
• In the 8085, an instruction cycle may consist of 1
to 6 machine cycles.
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• The 8085 executes several types of instructions
with each requiring a different number of
operations of different types. However, the
operations can be grouped into a small set.
• The three main types are:
• Memory Read and Write.
• I/O Read and Write.
• Request Acknowledge.

• These can be further divided into various

operations (machine cycles).
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 Example: Instruction Fetch Operation

▪ All instructions (program steps) are stored in memory.

▪ To run a program, the individual instructions must

be read from the memory in sequence, and executed.

▪ Program counter puts the 16-bit memory address of the

instruction on the address bus
▪ Control unit sends the Memory Read Enable signal to
access the memory
▪ The 8-bit instruction stored in memory is placed on the data
bus and transferred to the instruction decoder
▪ Instruction is decoded and executed

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 Example: Instruction Fetch Operation

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 Example: Instruction Fetch Operation

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 Timing Diagram
Opcode Fetch Cycle
T1 T2 T3 T4

CLX

A15
20H High-Order Memory Address Unspecified
A8
Low-Order
AD7
05H 4FH Opcode
AD0
Memory Address

ALE

IO/M Status IO/M = 0, S0 = 1, S1 = 1 Opcode Fetch

RD

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 Demultiplexing the Bus AD0-AD7

• Address on the high order bus(20H)

remains on bus for 3 clock period.
• However, the lower order address(05H) is
lost after first clock period.
• Address needs to be latched to identify
address after first clock period.

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 Schematic of Latching Low Order
Address Bus
A15 A15

8085
Microprocessor
A8
A8
ALE
Enable
AD7 G
D Q A7

AD0 74LS373
A0

D7

D0

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 Schematic to generate Control Signals
74LS32

IO/M
MEMR
RD

8085
WR MEMW

IOR
74LS04

IOW

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 Timing for Execution of the
Instruction MVI A,32H
M1 Opcode Fetch M2 Memory Read
T1 T2 T3 T4 T1 T2 T3

CLX

A15
20H High-Order Memory Address Unspecified 20H High- Order Memory Address
A8

AD7
00H 3EH Opcode 01H 32H Data
AD0
Low-Order Memory Address Memory Address

ALE

IO/M
Status IO/M = 0, S0 = 1, S1 = 1 Opcode Fetch IO/M = 0, S1 = 1, S0 = 0 Status
S1, S0

RD

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 Addressing Modes
• Various ways of specifying the operands or
various formats for specifying the operands is
called addressing mode
• 8-bit or 16-bit data may be directly given in the
instruction itself
• The address of the memory location, I/O port or
I/O device, where data resides, may be given in
the instruction itself
• In some instructions only one register is specified.
The content of the specified register is one of the
operands. It is understood that the other operand is
in the accumulator.
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• Some instructions specify one or two
registers. The contents of the registers are
the required data.
• In some instructions data is implied. The
most instructions of this type operate on the
content of the accumulator

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 Addressing Modes (8085)

• Implicit addressing
– CMA – Complement the contents of
accumulator
• Immediate addressing
– MVI R, 05H
– ADI 06H
• Direct addressing – The address of the
operand in the instruction - STA 2400H, IN
02H
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• Register addressing
– In register addressing mode the operands are in
the general purpose registers
– MOV A, B
– ADD B
• Register indirect addressing
– Memory location is specified by the contents of
the registers
– LDAX B, STAX D, MOV A,M

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 Instructions of 8085

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 Data Transfer Instructions
Type Example
Between Registers MOV B, D - Copy the contents of
register D into register B
Specific data byte to a register or a MVI B, 32H – Load register B with
memory location the immediate data byte 32H.
Between a memory location and a MOV B, M – From memory location
register specified by HL pair register to
register B
Between an I/O device and the IN 05H – The contents of input port
accumulator designated in the operand(05H) are
read and loaded in accumulator(A)

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MOV: This instruction copies the contents of source
register into destination register.
• MOV Rd,Rs
• MOV M,Rs
• MOV Rd,M
These instructions are 1 byte instructions.
Examples: MOV A,B
MOV B,M
MOV M,A
Flags: No flags are affected
If one of operands is memory location, it is specified
by HL pair register.
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Opcode Operand Byte M- Cycle T-State

MOV Rd, Rs 1 1 4

MOV M, Rs 1 2 7

MOV Rd, M 1 2 7

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MVI R,8 bit data: Store 8 bit data in
destination register or memory. If
destination is memory, it is specified by the
HL pair register.
.Opcode Operand Byte M- Cycle T-State

MVI R, Data 2 2 7
MVI M,Data 2 3 10

No flags are affected.

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 LXI Rp/SP, 16 bit data: Loads 16 bit data in
register pair/stack pointer.
.Opcode Operand Byte M- Cycle T-State

LXI Rp, 3 3 10
Data(16)
LXI SP,Data(16) 3 3 10

•No flags are affected.

•Second byte of instruction specifies the low-order byte
of data and third byte specifies the low-order byte of data
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 STA 16 bit Addr: Content of accumulator is
stored in memory location whose address is
specified by 2nd and 3rd byte of instruction.
.Opcode Operand Byte M- Cycle T-State

STA 16 bit 3 4 13

•No flags are affected.

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LDA 16 bit Addr: Content of memory
location memory location whose address is
specified by 2nd and 3rd byte of instruction,
is loaded in accumulator.
.Opcode Operand Byte M- Cycle T-State

LDA 16 bit 3 4 13

•No flags are affected.

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 STAX Rp: Content of accumulator is copied
into memory location whose address is
specified by register pair(BC or DE).
.Opcode Operand Byte M- Cycle T-State

STAX B/D 1 2 7

•No flags are affected.

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LDAX Rp: Content of memory location
whose address is specified by register
pair(BC or DE), is loaded in accumulator.
.
Opcode Operand Byte M- Cycle T-State

LDAX B/D 1 2 7

•No flags are affected.

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SHLD 16 bit Addr: Content of register L is
stored in memory location whose address is
specified by 2nd and 3rd byte of instruction
and content of register H is stored in next
memory location.
. Opcode Operand Byte M- Cycle T-State

SHLD Addr(16 3 5 16
bit)
•No flags are affected.

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LHLD 16 bit Addr: Content of memory
location memory location whose address is
specified by 2nd and 3rd byte of instruction,
is loaded into register L and content of next
location is copied into register H.
. Opcode Operand Byte M- Cycle T-State

LHLD Addr(16 3 5 16
bit)
•No flags are affected.

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IN 8 bit addr (Port Address):Accept(read)
data byte from an input device and place it
in the accumulator.
OUT 8 bit addr (Port Address): Send(write)
data byte from the accumulator to an output
device.
Opcode Operand Byte M- Cycle T-State
IN Addr(8 bit) 2 3 10
OUT Addr(8 bit) 2 3 10

•No flags are affected.

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XCHG: Exchange the contents of H-L pair
with D-E pair.

.Opcode Operand Byte M- Cycle T-State

XCHG None 1 1 4

•No flags are affected.

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SPHL: Copy the contents of H and L register
into the stack pointer.

.Opcode Operand Byte M- Cycle T-State

SPHL None 1 1 6

•No flags are affected.

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