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Lecture Notes in Electrical Engineering 677
Yue Wang
Lexi Xu
Yufeng Yan
Jiaqi Zou Editors
Signal and
Information
Processing,
Networking and
Computers
Proceedings of the 7th International
Conference on Signal and Information
Processing, Networking and Computers
(ICSINC)
Lecture Notes in Electrical Engineering
Volume 677
Series Editors
Leopoldo Angrisani, Department of Electrical and Information Technologies Engineering, University of Napoli
Federico II, Naples, Italy
Marco Arteaga, Departament de Control y Robótica, Universidad Nacional Autónoma de México, Coyoacán,
Mexico
Bijaya Ketan Panigrahi, Electrical Engineering, Indian Institute of Technology Delhi, New Delhi, Delhi, India
Samarjit Chakraborty, Fakultät für Elektrotechnik und Informationstechnik, TU München, Munich, Germany
Jiming Chen, Zhejiang University, Hangzhou, Zhejiang, China
Shanben Chen, Materials Science and Engineering, Shanghai Jiao Tong University, Shanghai, China
Tan Kay Chen, Department of Electrical and Computer Engineering, National University of Singapore,
Singapore, Singapore
Rüdiger Dillmann, Humanoids and Intelligent Systems Laboratory, Karlsruhe Institute for Technology,
Karlsruhe, Germany
Haibin Duan, Beijing University of Aeronautics and Astronautics, Beijing, China
Gianluigi Ferrari, Università di Parma, Parma, Italy
Manuel Ferre, Centre for Automation and Robotics CAR (UPM-CSIC), Universidad Politécnica de Madrid,
Madrid, Spain
Sandra Hirche, Department of Electrical Engineering and Information Science, Technische Universität
München, Munich, Germany
Faryar Jabbari, Department of Mechanical and Aerospace Engineering, University of California, Irvine, CA,
USA
Limin Jia, State Key Laboratory of Rail Traffic Control and Safety, Beijing Jiaotong University, Beijing, China
Janusz Kacprzyk, Systems Research Institute, Polish Academy of Sciences, Warsaw, Poland
Alaa Khamis, German University in Egypt El Tagamoa El Khames, New Cairo City, Egypt
Torsten Kroeger, Stanford University, Stanford, CA, USA
Qilian Liang, Department of Electrical Engineering, University of Texas at Arlington, Arlington, TX, USA
Ferran Martín, Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, Bellaterra,
Barcelona, Spain
Tan Cher Ming, College of Engineering, Nanyang Technological University, Singapore, Singapore
Wolfgang Minker, Institute of Information Technology, University of Ulm, Ulm, Germany
Pradeep Misra, Department of Electrical Engineering, Wright State University, Dayton, OH, USA
Sebastian Möller, Quality and Usability Laboratory, TU Berlin, Berlin, Germany
Subhas Mukhopadhyay, School of Engineering & Advanced Technology, Massey University,
Palmerston North, Manawatu-Wanganui, New Zealand
Cun-Zheng Ning, Electrical Engineering, Arizona State University, Tempe, AZ, USA
Toyoaki Nishida, Graduate School of Informatics, Kyoto University, Kyoto, Japan
Federica Pascucci, Dipartimento di Ingegneria, Università degli Studi “Roma Tre”, Rome, Italy
Yong Qin, State Key Laboratory of Rail Traffic Control and Safety, Beijing Jiaotong University, Beijing, China
Gan Woon Seng, School of Electrical & Electronic Engineering, Nanyang Technological University,
Singapore, Singapore
Joachim Speidel, Institute of Telecommunications, Universität Stuttgart, Stuttgart, Germany
Germano Veiga, Campus da FEUP, INESC Porto, Porto, Portugal
Haitao Wu, Academy of Opto-electronics, Chinese Academy of Sciences, Beijing, China
Junjie James Zhang, Charlotte, NC, USA
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123
Editors
Yue Wang Lexi Xu
China Academy of Space Technology China Unicom
Beijing, China Beijing, China
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Preface
It is our great honor to welcome you to the 7th International Conference on Signal
and Information Processing, Network and Computers (ICSINC 2020 Spring).
The ICSINC 2020 committee has been monitoring the evolving COVID-19 pan-
demic. We have decided to delay the 2020 edition of this conference from May to
September.
ICSINC 2020 Spring provides a forum for researchers, engineers and industry
experts to discuss recent development, new ideas and breakthrough in signal and
information processing schemes, computer theory, space technologies, big data and
so on.
ICSINC 2020 Spring received 280 papers submitted by authors, and 129 papers
were accepted and included in the final conference proceedings. The accepted
papers will be presented and discussed in 27 regular technical sessions and two
workshops.
On behalf of the ICSINC 2020 committee, we would like to express our sincere
appreciation to the TPC members and reviewers for their tremendous efforts.
Especially, we appreciate all the sponsors for their generous support and advice,
including Springer, China Unicom, HuaCeXinTong. Finally, we would also like to
thank all the authors for their excellent work and cooperation.
Yue Wang
Li Guo
ICSINC 2020 General Chairs
v
Committee Members
General Chairs
Yue Wang China Academy of Space Technology, China
Li Guo Beijing University of Posts
and Telecommunications, China
Publication Chair
Lexi Xu China Unicom Research Institute, China
General Secretaries
Jiaqi Zou Beijing University of Posts
and Telecommunications, China
Yufeng Yan Beijing University of Posts
and Telecommunications, China
vii
viii Committee Members
Sponsors
Springer
China Unicom
HuaCeXinTong
Contents
ix
x Contents
Spacecraft Technology
Research on Quantitative Evaluation of Spacecraft Model Control
Subsystem Product Assurance Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Xu Jingyu, Yu Songbai, Ning Yu, and Cai Junliang
Electrical Power Sizing and Performance Simulation Tools
for Spacecraft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Dongsheng Jiang
The Research on the Application of Design Pattern of Object-
Oriented Software Development Technology in Aerospace
Embedded Software Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Jian Guan, Jianwei Du, and Huiyan Cheng
Experimental Research on Direction Modulation of Plasma Flow
Generated in Helicon Plasma Thruster . . . . . . . . . . . . . . . . . . . . . . . . . 332
Liang Ding, Huiqi Zheng, Yuchuan Peng, Qiongying Ren, and Hua Zhao
Design of Fast Response High-Voltage Power Supply for the
Electrostatic Deflection System in a Low-Energy Particle
Spectrometer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Hao Li, Yuchuan Peng, Lili Ge, Junfeng Wang, Zhong Peng,
Zhenyu Tang, Qinghai Liu, Wei Qin, Tao Li, Qiongying Ren, Hua Zhao,
and Yi Zong
Contents xiii
Communication System
Development of Cislunar Space Integrated
Communication Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
Baobi Xu, Jionghui Li, Shi Liu, and Xiaoguang Li
A Novel Plume Radiation Model for Analyzing Thruster Plume
Impact on IRES Based on Numerical Simulation . . . . . . . . . . . . . . . . . . 723
Jinpeng Wang, Lizhen Wang, Mingyu Xie, and Zhijun Tu
Not All Branches Are Equal: An Improved QSYM Schema
for Binary Vulnerability Mining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
Bo Wu, QinSi Yang, and YuFeng Ma
Contents xvii
Abstract. The integration test of spacecraft attitude and orbit control system
(AOCS) is an important means to confirm whether the design of the system meets
the mission requirements throughout the whole process of system development.
The AOCS based on 1553B bus architecture is gradually applied to Chinese
spacecraft. In this paper, the status of AOCS integration test and the characteristics
of the AOCS based on 1553B bus architecture are analyzed and a satellite-ground
integration test scheme for AOCS based on 1553B bus architecture is proposed.
The scheme of testability and ground environment for four types of integration test
are introduced and the technical features of sensor closed-loop method, actuator
closed-loop method and component RT simulation method are emphasized. The
application of the test scheme for AOCS of the satellite is also given. The test
scheme has the advantages of universality, expansibility, convenience and relia-
bility, which can improve the test efficiency and quality of AOCS significantly.
1 Introduction
The integration test of attitude and orbit control system (AOCS), which includes the
open-loop component test and the closed-loop simulated-flight test [1], can be divided
into system development test, the whole-satellite assembly integration test (AIT) and
shooting range test based on testing phase [2]. According to differences of test items
and test states in the different testing phases, four types of integration test are defined:
the system-level component test, the full-function closed-loop test, the status confir-
mation closed-loop test, and the simulator closed-loop test. The full-function closed-
loop test is a detailed test on functional indicators and/or performance of the system
when all products are assembled. The state confirmation closed-loop test is a simplified
functional test of the system. The simulator closed-loop test aims to perform functional
test on system when some products are not assembled. The integration test scheme of
the AOCS has to meet the requirements of four types of test mentioned above, while
having universality, expansibility, convenience and reliability [3].
© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021
Y. Wang et al. (Eds.): Signal and Information Processing, Networking
and Computers, LNEE 677, pp. 3–11, 2021.
https://doi.org/10.1007/978-981-33-4102-9_1
4 Z. Jiang et al.
The AOCS of current spacecraft is limited by the serial-port based architecture and
customized grounding interface of components. The integration test scheme is mainly
based on the ground testing environment [4]. The testability design on the satellite is
deficient and mainly depends on the design of controller. Characteristics of current
integration test scheme of the AOCS is as follows: (1) Lack of a unified architecture of
test scheme, the test methods of each single unit are customized which leads to poor
universality; (2) The hardware board must be changed when many components are
assembled by the ground environment based on customized interface, which indicates a
deficient expansibility; (3) The test scheme is complicated, the ground environment is
large-sized and inconvenient, e.g. the test scheme of AOCS introduced in [5]. In order
to deal with the situation that the integration test has to be conducted when some
products are not involved, the signal adapter has to be designed with two modes.
Besides, the grounding serial ports, constant current sources, and grounding detection
signals like analog signal must be classified and adjusted; (4) Problems caused by cable
switching introduced by different test methods, long-distance signal crosstalk brought
by customized weak current signals and non-digital signals such as analog signals, and
re-calibration on signals when status of the test changes, present the potential quality
problems and poor reliability.
With the intelligent function expansion and performance improvement on the
AOCS of spacecraft, domestic AOCS in the fields of remote sensing, communication,
and space station has begun to apply the architecture based on the 1553B bus [6]. The
integration, digitization, and intelligentization of units of the AOCS have been greatly
improved, which provides the condition for developing on-board testability design. [7]
introduced the advantages of testability design of the control system based on the
1553B bus architecture. [8] provided design recommendations on system-level testa-
bility that decompose the target of testability design on each unit according to the test
requirements. [9] proposed a new universal 1553B test platform. The domestic research
mentioned above is still in the development stage of the testability design of the on-
board system and there is scarcely any research on the testability design of the system-
level integration test scheme related to the AOCS.
Based on the current test status of the AOCS and the characteristics of the 1553B
bus architecture, this paper conducts the research and design on the integration test
scheme of the AOCS, and proposes an integration test scheme based on satellite-
ground joint design. The technical features of the scheme are also introduced.
The bus topology of the AOCS based on the 1553B bus architecture is shown in Fig. 1.
The controller as the BC terminal of the architecture is the central control computer.
The sensor in RT terminal includes infrared earth sensor, star sensor and gyroscope.
The actuator in RT terminal comprises drive control device, control moment gyro
(CMG) and solar array drive assembly (SADA).
The advantages to the design of system integration test brought by applying the
1553B bus as the internal data transmission interface of the AOCS are as follows:
A Satellite-Ground Integration Test Scheme 5
Fig. 1. The architecture of the AOCS satellite-ground joint integration test scheme
(1) The customized unit grounding interface for data collection can be canceled.
The real-time data of the single unit on the bus can be acquired by applying the MT
function of 1553B bus, which greatly reduces the types and number of satellite-ground
interface signals.
(2) The standard bus communication interface simplifies development of the sim-
ulator when the on-board AOCS is not completely assembled. By using the RT
function of the 1553B bus, multiple RT interface can be configured on the dynamics
computer to simulate various components of the AOCS.
(3) The capability of data transmission is strong. The transmission rate of the 1553
bus reaches 1Mbps, which can meet the data transmission requirement of the AOCS
while transmitting large-capacity data related to the integration test.
and the actuator are applied to provide various test data required for the open-loop
component test or the closed-loop simulated flight test.
The ground testing environment consists of test host computer, main control
computer, and data server. The test host computer aims to complete collection of
actuator signals, transmission of sensor signals, and calculation of attitude and orbit
kinematics and dynamics simulation. The main control computer is responsible for the
management and scheduling of test sequences. Data processing, storage and display are
implemented in the data server. Compared with the traditional test scheme, the test host
computer uses 1553B boards with the features of intelligentization, generalization, and
standardization instead of numerous component simulators, which simplifies the signal
adapter. The test host computer is connected to the 1553B bus as an RT terminal for
implementing data interaction with the products on the satellite. The bus monitor MT
monitors and records the information flow data of the 1553B bus in the system to
facilitate problem analysis. The multiple RT board simulates multiple RT components
based on the bus communication protocol.
Fig. 4. The closed-loop architecture of the system based on the RT-component simulator
The test host computer designs corresponding component simulators based on the
function of different components. The sensor simulator converts the satellite attitude
calculated by the dynamics into its own attitude information and simulates the operating
A Satellite-Ground Integration Test Scheme 9
state of corresponding products. The actuator simulator receives the control instructions
and simulates the real kinematics features of the actuator. The RT address allocation and
communication protocol design of each component simulator is consistent with the on-
board real products. By applying 1553B bus interface, they provide sensor attitude data
required for the closed-loop test and receive control instructions from the actuator.
This method has no influence on the on-board controller. No extra function design
is added. The only operation is to perform the function of normal function modules.
When some products are not assembled, the ground equipment specifies the corre-
sponding RT simulator to work by using soft switches, which has no effort on the
communication of other on-board real products. In this state, only the controller is
necessary for conducting the closed-loop test. This method can implement the system
function test with the minimum component configuration, and complete the component
failure mode test by modifying the parameters of the related simulator online.
5 Application
The test scheme proposed has been applied in the AOCS of an agile maneuver satellite
based on 1553B bus architecture. The configuration of this satellite consists of a control
computer as BC and 25 RT-components, which include infrared sensors, gyroscopes,
star sensors, CMG, SADA and actuator control unit. According to the above test
scheme, the test module has been uniformly designed in the software of the on-board
products. The hardware configuration of the ground testing environment includes: the
test host computer, the main control computer and the data server. In the state con-
firmation closed-loop test, only a portable test host computer is required. Software
configuration is implemented in the test host computer based on the status of the
component. Compared with the traditional test host computer, dynamic signal adapter,
simulator signal adapter, and simulator configuration of a variety of customized
components, the scale of test equipment required is greatly reduced.Some typical test
curves include the attitude of AOCS, sensors and actuators are shown in Fig. 5.
Rolling Angle Pitch Angle Yaw Angle CMG1 CMG2 CMG3 CMG4 CMG5 CMG6
5 0.12
0.08 Low-speed Frame Rate of the CMG
3
0.04
1 0
-1 -0.04 1 2001 4001 6001 8001 10001
1 2001 4001 6001 8001 10001
-3 -0.08
-5 -0.12
The application results present that the scheme designed for the four types of tests is
suitable for various states and stages of the integration test. During the test, the
hardware status between components in the AOCS and ground equipment is consistent.
There is no operation on the status of satellite-ground cable connection during the
status switching, which greatly improves efficiency and reliability of the test compared
with the traditional test scheme. The compliance of functions and performance of the
whole system has been verified.
6 Conclusion
Favorable conditions for solving the deficiency of integration test scheme for the
AOCS of traditional spacecraft has been provided by the advantages of 1553B bus
architecture. A satellite-ground joint integration test scheme for the characteristics of
the AOCS based on the 1553B bus architecture has been proposed in this paper, which
satisfied the requirement of four types of test for the AOCS. The proposal of the scheme
has a great significance in improving the test technology, test quality and test efficiency
of the system. By configuring the signal adapter in the ground integration testing
environment while components of the AOCS can still employ the traditional test
approaches, the proposed test scheme has performed many advantages in various
aspects and a good compatibility. In the future, the further work on testability design of
on-board products based on the intelligent component, and simplification and stan-
dardization of the design on test methods, test cases, and test interpretations can be
conducted by jointly applying the proposed scheme and design approach on system-
level testability proposed in [8]. Finally, the international advanced level on the
capability of integration test in the AOCS can be achieved.
References
1. Peng, C., Yue, L., Jinfeng, H., Yi, G.: Design of universal satellite integrated test system
based on classification management. Modern Defence Technol. 266(04), 157–166 (2018)
2. Li, P., Wang, J.: Development and implementation technology of comprehensive satellite
testing technology[C]. In: The 3rd High-level Forum of National Defense Technology
Industry Test and Development Strategy of Test Technology, (2010)
3. Harry, J.: Integrated systems testing of spacecraft. In: The 37th International Conference on
Environmental Systems(ICES). Chicago: Aviation Industry Development Research (2007)
4. Xiaowei, F., Huamao, W., Yan Jindong, L., Chengzhi, W.Q.: Current situation overview of
spacecraft system level test. Spacecraft Eng. 26(1), 120–126 (2017)
5. Jufeng, D., Li, Y., Yue, W.: OSA-Based testing technology of spacecraft control system.
Aerospace Control Appl. 38(5), 34–37 (2012)
6. Ning, Y., Qi, Z., Rongxiang, C.: Internal bus-based AOCS configuration. Aerospace Control
Appl. 38(2), 30–34 (2012)
7. Haibo, W., Li, Y.: Frame design and verification of DFT Technique for control system of
spacecraft based on 1553B bus architecture. Aerospace Control Appl. 40(2), 26–30 (2014)
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Title: Taikapeili
Nelinäytöksinen satunäytelmä
Author: Larin-Kyösti
Language: Finnish
Nelinäytöksinen satunäytelmä
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Linnan etuhuone.
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