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Behnam Ghavami
Mohsen Raji
Soft Error
Reliability
of VLSI
Circuits
Soft Error Reliability of VLSI Circuits
Behnam Ghavami • Mohsen Raji
Soft Error Reliability of

VLSI Circuits
Behnam Ghavami Mohsen Raji
Shahid Bahonar University of Kerman Shiraz University
Kerman, Iran Shiraz, Iran
ISBN 978-3-030-51609-3 ISBN 978-3-030-51610-9 (eBook)

https://doi.org/10.1007/978-3-030-51610-9
© Springer Nature Switzerland AG 2021

This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of
the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation,
broadcasting, reproduction on microfilms or in any other physical way, and transmission or information
storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology
now known or hereafter developed.
The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication
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The publisher, the authors, and the editors are safe to assume that the advice and information in this book
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This Springer imprint is published by the registered company Springer Nature Switzerland AG
The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland
“I want to thank my father and mother.”
Thank you.
Dedicated to my family, Arezoo and Hiva.
Behnam
“I want to thank my father and mother.”
Thank you.
Dedicated to my family, Zahra and Aala.
Mohsen
Preface
In recent decades, VLSI circuit designers have achieved high-speed circuits with
fewer power requirements by continuously reducing the transistor dimensions.
Besides these benefits, the digital circuits have become more sensitive against envi-
ronmental faults due to several factors such as decreasing the transistor size and the
supply voltage. Hence, the reliability of the VLSI circuits has become an important
issue in recent years. Among these noise sources, radiation-induced soft errors in
commercial nanometer CMOS technologies have become a growing concern.
Nanometer integrated circuits are getting increasingly vulnerable to soft errors mak-
ing the soft error rate (SER) estimation and optimization an important challenge.
Efficient and accurate SER estimation and optimization of the large-scale combina-
tional circuits help the designers to achieve more reliable integrated circuits.
This book will investigate emerging trends in the design of today’s reliable elec-
tronic systems which are applicable to safety-critical applications like automotive
or healthcare electronic systems. The book will introduce software tools for analysis
and mitigation of soft errors in electronic systems. The emphasis is on modeling
approaches and algorithms for analysis and mitigation of soft error issue in nanoscale
CMOS digital circuits and techniques that are the cornerstone of Computer Aided
Design (CAD) of a reliable VLSI circuit.
Kerman, Iran Behnam Ghavami

Shiraz, Iran Mohsen Raji
vii
Acknowledgments
After one decade of researching and teaching in the field of fault-tolerant computing
systems, we decided to write this book. The groups of students from Shahid Bahonar
University of Kerman who developed the algorithms and software packages are
important contributors of this work.
We would like to thank Professor Hossein Pedram for keeping us engaged and
learning. Our special thanks go to our graduated students Amin Sabet, Mohammad
Reza Rohanipour, and Mohammad Eslami who developed the materials for chapters
and helped with the preparation of the book. All this would not have been possible
without their valuable support.
Writing this book is harder than we thought and more rewarding than we could
have ever imagined. None of this would have been possible without our families.
Behnam and Mohsen

April 2020
ix
Contents
1 Introduction: Soft Error Modeling�� 1

1.1 Impacts of Particle Strike on Semiconductor Devices�� 2
1.2 Single-Event Transient Modeling �� 3
1.3 Impact of a Particle Hit on Combinational Circuits�� 3
1.3.1 Electrical Masking�� 4
1.3.2 Logical Masking �� 5
1.3.3 Timing Masking�� 5
References�� 6
2 Soft Error Rate Estimation of VLSI Circuits�� 9
2.1 Introduction�� 9
2.2 Soft Error Rate Estimation Formulation �� 10
2.3 Probabilistic Vulnerability Window�� 12
2.3.1 PVW Definition�� 12
2.3.2 PVW Computation Model�� 13
2.4 Error Probability Computation �� 13
2.4.1 Handling Reconvergent Paths �� 17
2.5 Error Probability Estimation Algorithm�� 18
2.6 Experimental Results�� 20
2.6.1 Reference Model�� 20
2.6.2 Accuracy/Runtime Investigation�� 20
2.7 Conclusions�� 22
References�� 22
3 Process Variation-Aware Soft Error Rate Estimation
Method for Integrated Circuits�� 25
3.1 Introduction�� 25
3.2 Statistical Soft Error Rate Estimation Framework�� 26
3.2.1 Pre-characterization Process �� 27
3.2.2 Level-by-Level Backward Netlist Traversing �� 27
3.2.3 Full-Spectrum Charge Collection-Aware
SER Computation �� 28
xi
xii Contents
3.3 Statistical Vulnerability Window (SVW)�� 29

3.3.1 SVW Parameters�� 29
3.3.2 SVW of POs�� 30
3.3.3 SVW of Internal Circuit Nodes�� 31
3.4 Error Probability Computation �� 32
3.4.1 Mathematical Model �� 33
3.4.2 Reconvergent Paths �� 35
3.4.3 Addressing Reconvergent Path Case�� 38
3.5 Error Probability Estimation Algorithm�� 39
3.6.1 Verification of the SER Estimation Method�� 41
3.7 Conclusion�� 41
References�� 43
4 GPU-Accelerated Soft Error Rate Analysis of Large-Scale
Integrated Circuits�� 45
4.1 Approach Overviews�� 46
4.2 SER Analysis�� 47
4.3 Parallel SER Analysis �� 49
4.3.1 Gate Parallelism�� 49
4.3.2 Parallel Structure�� 50
4.3.3 Parallel SET�� 51
4.4 Simulation �� 52
4.4.1 Preprocessing�� 52
4.4.2 Kernel Function�� 52
4.5 Simulation Results�� 52
References�� 54
5 FPGA Hardware Acceleration of Soft Error Rate Estimation
of Digital Circuits �� 55
5.1 The Introduced Framework�� 56
5.2 SER Estimation Based on Probability Propagation Rules�� 57
5.2.1 Four-Value Signal Probability Modelling �� 58
5.2.2 Fault Injection Modeling�� 60
5.2.3 SER Estimation�� 60
5.3 Hardware Implementation of the Probability Propagation �� 61
5.3.1 Generating Computational Blocks for the Probability
Propagation Model�� 62
5.3.2 Fault Injection �� 63
5.3.3 SER Estimation�� 64
5.4 Efficient Implementation with FPGA �� 65
5.4.1 Area Problem�� 65
5.4.2 Circuit Partitioning�� 66
5.5.1 Resource Utilization�� 70
Contents xiii
5.5.2 Circuit Partitioning Acceleration Results�� 71

References�� 72
6 Soft Error Tolerant Circuit Design Using Partitioning-Based
Gate Sizing�� 75
6.1 Gate Sizing Technique�� 76
6.1.2 Sub-circuit Error Probability Computation�� 79
6.1.3 Gate Resizing�� 83
6.1.4 Sub-circuit Gate Sizing Optimization�� 87
References�� 91
7 Resynthesize Technique for Soft Error-Tolerant Design
of Combinational Circuits �� 93
7.1 Soft Error in Combinational Circuits�� 94
7.2 The Proposed Soft Error-Tolerant Method �� 96
7.2.2 Local Sub-circuit Evaluation�� 98
7.2.3 Sub-circuit Restructuring�� 102
7.2.4 Optimization Algorithm�� 103
References�� 106
Index�� 109
Chapter 1
Introduction: Soft Error Modeling
In recent decades, VLSI circuit designers have achieved high-speed circuits with
fewer power requirements by continuously reducing the sizes of transistors. Besides
these benefits, aggressive technology scaling has led to serious reliability challenges
for nanoscale digital circuits. Various sources that may affect the circuit reliability
can be divided into two groups: permanent faults and transient faults. Permanent
faults are the ones which lead to constant malfunctioning of the circuit. Examples of
sources that lead to permanent faults are hot-carrier injection (HCI) and negative-
bias temperature instability (NBTI) in transistors and electrical migration between
connections. In addition to permanent fault, transient faults can also have a negative
effect on correct functionality of the circuit. Transient faults occur in certain envi-
ronmental conditions and are present in the system for a short time and may cause
an error in the circuit or disappear without causing a problem for the circuit. Among
various sources resulting in transient fault, collisions of high-energy particles emit-
ted by cosmic rays and emission of alpha particles from the circuit package to sensi-
tive areas of a semiconductor have had the greatest negative impact on the reliability
of digital circuits [1].
The transient faults caused by a high-energy particle strike in the combinational
circuits and sequential elements (i.e., memory cells, latches, and flip-flops) are
called single-event transient (SET) and single-event upset (SEU), respectively [1].
In recent years, SET has been one of the most important sources that could affect
the reliability of the combinational circuits. Such a bit-flip of a storage node is
called a single-event upset (SEU). This chapter provides introductions to soft error
issue and soft error modeling procedure.
This chapter is organized as follows. Section 1.1 explains the impacts of particle
strike on semiconductor devices. In Sect. 1.2, we explain the modeling approach of
single-event transient and single-event upset and in Sect. 1.3, we describe the
impacts of particle hit on combinational circuits.
© Springer Nature Switzerland AG 2021 1

B. Ghavami, M. Raji, Soft Error Reliability of VLSI Circuits,
https://doi.org/10.1007/978-3-030-51610-9_1
2 1 Introduction: Soft Error Modeling
1.1 Impacts of Particle Strike on Semiconductor Devices
When high-energy particles strike into a sensitive part of a semiconductor device

(Fig. 1.1a), a dense channel of electrons and holes (called funnels) are formed when
passing through a P and N junction (Fig. 1.1b). Then, a number of these electrons
and holes are recombined together, which is called the charge collection phenome-
non (Fig. 1.1c). This process leads to the production of a current with a very short
duration at the collision site.
The maximum amount of the induced current and the width of the generated SET
depend on the process of collecting the charge after the production of the electron-
hole channel [2]. Factors such as channel density and charge collection velocity
determine the shape of the produced SET. The total charge collection process
depends on the concentration of the substrate; that is, the charge collection will
continue until the density of the generated carriers becomes equal to the impurity of
the substrate. If the impurity of the substrate is low, more carriers will be generated
leading to higher induced current.
The height and width of the induced current pulse depend on the amount of
energy of the striking particle. In other words, it depends on the amount of charge
induced by the high-energy particle. The linear energy transfer (LET) is a parameter
used to show the relationship between the particle energy and the amount of charge
generated in a particular type of material. One LET is the amount of energy that is
lost by a particle during its motion in a unit of material length. The unit of LET is
MeV cm2/mg.
ldiff ldrift Ion track
_ +- +-
_ +- +-
_ _ _ + +-
_ _ _ + +- +-
+_ + _ + + + __ __ + +- +-
_ + _ +- +-
_ +_ +-
+ _+ + + + + +- +-
_ + +
+ + _ + _+ +
+ +- +-
(a) (b) (c)
Fig. 1.1 Overall mechanism of a particle strike into a P and N junction: (a) particle striking
moment, (b) charge collection, (c) redistribution
1.3 Impact of a Particle Hit on Combinational Circuits 3
1.2 Single-Event Transient Modeling
The process of striking the particles to the surface of the circuit and generation of a
single-event transient is illustrated by a current model [3]. After striking the particle
on the silicon, the charge collection phenomenon occurs leading to appearance of a
transient current in the strike point. The generated current from the particle is
approximately modeled by an exponential equation as
Qcoll ìï æ -t ö æ -t ö üï
icoll ( t ) = íexp ç ÷ - exp ç ÷ý (1.1)
t fall - t rise îï è t fall ø è t rise ø þï
where Qcoll is the amount of the induced charge in the semiconductor element caused
by the particle strike. τrise and τfall are, respectively, the rising time and the delay of
the current pulse which are technology dependent. The slope and the width of the
generated pulse depend on the circuit and the environmental parameters such as the
angle of the strike and the amount of impurity in the materials, which can be mod-
eled by changing the timing parameters of Eq. (1.1).
The induced charge caused by a particle hit and, consequently, the generated cur-
rent may provide the necessary charge to change the stored value in a memory cell.
In this case, a single-event upset (SEU) or a soft error will occur. Of course, this
particle can hit a transistor in the combinational part of the circuit leading to another
issue as described in the following.
1.3 Impact of a Particle Hit on Combinational Circuits
Figure 1.2 shows the general process of a particle hit on a sensitive area of an
inverter gate. The particle hit on a PMOS transistor in an OFF state generates a cur-
rent pulse in this transistor. The produced current charges the load capacitor (CL) in
the output node of the inverter gate and then the load stored in the capacitor will be
discharged from the capacitor through the NMOS in the ON state. This process
leads to a transient voltage pulse generation at the output of the circuit. This voltage
pulse is called a single-event transient or briefly SET.
The particle hits on a transistor in a circuit may result in a SET at the output of
the circuit gate. In order to cause a soft error in the circuit, the generated SET has to
be logically propagated along the combinational circuit and eventually reach the
input of a memory element such as latch or flip-flop and be stored in it. During
propagation, the logical, electrical, and timing characteristics of the SET may be
affected preventing the SET to be changed into a soft error. These properties, which
are called masking mechanisms, are decreased in nanoscale technologies. The
details of masking mechanisms are described in the following subsections.
Fig. 1.2 The process of particle strike to an inverter gate and the induced current pulse in its out-
put [4]
Fig. 1.3 An illustrative example of electrical masking effect
1.3.1 Electrical Masking
During transient pulse propagation through a combinational logic circuit, the height
and width of the SET may be attenuated as it passes through the input to the output
of each gate. If the SET height decreases such that it does not actually show a logi-
cal change in its value, it will not be propagated through the gate. Moreover, if the
pulse width decreases such that it does not meet the time requirements of a memory
element, it will not be stored by the memory element. In these cases, it is called that
the SET is electrically masked [5]. The amount of electrical masking that occurs at
each gate is a function of the gate delay as well as the height and width of the SET
[6, 7]. Figure 1.3 shows an example of a SET being attenuated when passing through
a chain of logical gates. The characteristics of the SET decrease with successive
passes through the gates in the logic circuit.
The overall procedure of the technology improvement and decrease in the pipe-
line levels for reducing the clock cycle timing decrease the electrical timing mask-
ing effect, because the circuit depth in each pipeline level will be decreased.
Furthermore, shrinking in size due to consecutive improvement of technology gen-
erations affects the electrical masking effect from two points of view. First, smaller
1.3 Impact of a Particle Hit on Combinational Circuits 5
size leads to decrease in the amount of the critical charge in the circuit which means
that the different parameters of the SET are being reduced. Also, the individual
attenuation of the SET in each gate is decreased since the propagating delay is
reduced due to the technology scaling. So, the electrical masking effect is decreased
and the circuits become more vulnerable against the soft error.
1.3.2 Logical Masking
When a particle strikes the combinational parts of the circuit, the generated transient
pulse may cause a change in latching elements only if there is a sensitized path
between the strike point and the latching element. The existence of the sensitized
path is based on the primary inputs of the circuit. For example, in the circuit shown
in Fig. 1.4, the transient pulse generated in the output of Ga is not propagated to the
output since the other input of the Gb has the logical value of 0, and the output
remains the logical value of 0. So, the SET is masked in this part of the circuit and
does not propagate through the circuit. This process is called logical masking [5].
The amount of logical masking in a circuit depends on the implementing function
of the circuit and is independent from all technology parameters, and as a result
technology improvement does not affect the logical masking.
1.3.3 Timing Masking
Even if a SET is not masked by electrical and logical masking mechanisms, it still
needs to reach the input of the latching element in a specific time interval. This time
interval in which the latching element stores a new value is known as latching win-
dow. It is calculated by summation of the setup and hold time [5]. The pulses reach-
ing to the inputs of the latching elements out of this latching window are masked by
timing masking effect. Figure 1.5 illustrates the different timing masking mecha-
nisms. In this figure, it is assumed that the sequential element of the flip-flop is
Fig. 1.4 An example of logical masking

Tsetup Thold
Clock Pulse
Latching SET
Masked SET
Masked SET
Fig. 1.5 An example of timing masking
triggered by the rising edge of the clock. The waveform on the top of the figure
indicates the clock cycle signal and the dotted lines show the latching window. As
shown in this figure, a transient pulse changes the value of the flip-flop only if it
occurs inside the latching window of the flip-flop.
Continuous technology scaling reduces the timing masking. Decrease in the
critical charge means that the propagating transient pulses have larger widths and
decrease in gate delays means both the clock pulse length and the latching window
are decreased. The combination of these effects increases the probability of reach-
ing a transient pulse to the input of a flip-flop, which means that the timing masking
occurs less.
References
1. R. C. Baumann, “Soft Errors in Advanced Semiconductor Devices—Part I: The

Three Radiation Sources,” IEEE Transactions on Device Material Reliability
(TDMR), Vol. 1, No. 1, pp. 17–22, 2001.
2. M. Zhang, N. R. Shanbhag, “A Soft Error Rate Analysis (SERA) Methodology,”
in Proceedings of the IEEE International Conference on Computer Aided Design
(ICCAD), pp. 111–118, 2004.
3. G. R. Srinivasan, P. C. Murley, H. K. Tang, “Accurate, Predictive Modeling of Soft
Error Rate due to Cosmic Rays and Chip Alpha Radiation,” in Proceedings of IEEE
International Reliability Physic Symposium (IRPS), pp. 12–16, 1994.
References 7
4. M. Fazeli, S. G. Miremadi, H. Asadi and S. N. Ahmadian, “A fast and accurate multi-

cycle soft error rate estimation approach to resilient embedded systems design,”
in 2010 IEEE/IFIP International Conference on Dependable Systems & Networks
(DSN), Chicago, IL, 2010, pp. 131–140.
5. P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, L. Alvisi, “Modeling the Effect
of Technology Trends on Soft-Error Rate of Combinational Logic,” in Proceedings
of International Conference on Dependable Systems and Networks (DSN), pp. 389–
398, 2002.
6. M. Omana, G. Papasso, D. Rossi, C. Metra, “A Model for Transient Fault Propagation
in Combinational Logic,” In Proceedings of IEEE International On-Line Test
Symposium (IOLTS), pp. 111–115, 2003.
7. R. Rajaraman, J. S. Kim, V. Narayanan, Y. Xie, M. J. Irwin, “SEAT-LA: A Soft Error
Analysis Tool for Combinational Logic,” In Proceedings of the International
Conference on VLSI Design, pp. 159–165, 2006.
Chapter 2
Soft Error Rate Estimation of VLSI
Circuits
2.1 Introduction
Soft error rate (SER) is a measurement metric which is used to evaluate the sensitiv-
ity of a digital circuit to SETs. Efficient and accurate SER estimation of the combi-
national circuits helps the designers to achieve more reliable integrated circuits.
Traditional SER estimation techniques can be categorized into two major groups:
dynamic and static approaches. Dynamic approaches are based on fault injection
and logic simulations. Although dynamic methods provide highly accurate SER
estimation results, they are drastically time consuming and are intractable for large
circuits [1–5]. On the other hand, static approaches take advantage of mathematical
modeling or special data structures to model the initial parameters of SETs and also
the SET propagation model in the SER estimation process.
In this chapter, we present a method for soft error rate estimation of the combi-
national circuits based on vulnerability evaluation of the circuit gates to soft errors
[6]. To evaluate the vulnerability of the circuit to SETs, we introduce a concept
called probabilistic vulnerability window (PVW) which considers the impacts of
triple masking factors (i.e., logical, electrical, and timing). In other words, the
parameters of PVW can be considered as a unified inference of various constraints
necessary for an SET to cause soft errors in the circuit when propagating through
the gates on its paths to the primary outputs. Using a computation model, PVWs for
each circuit gate output are calculated based on a level-order backward circuit tra-
versing and meanwhile the SER of the circuit is gradually estimated considering a
mathematical formulation of SER considering the computed PVW parameters. In
order to validate the presented approach, we compare the obtained results with
Monte Carlo-based fault injection (MCFI) simulations. This comparison indicates
that the accuracy of the presented method is in average 2% of the results obtained
by MCFI with four orders of magnitude speedup.
This chapter is organized as follows. Section 2.2 formulates the SER estimation
of a given combinational circuit. In Sect. 2.3, we describe the details of PVW and in
© Springer Nature Switzerland AG 2021 9

B. Ghavami, M. Raji, Soft Error Reliability of VLSI Circuits,
https://doi.org/10.1007/978-3-030-51610-9_2
10 2 Soft Error Rate Estimation of VLSI Circuits
Sect. 2.4, we present the approach for error probability computation. Section 2.5
presents the SER estimation algorithms. In Sect. 2.6, we report the experimental
results for a set of common benchmarks. Finally, Sect. 2.7 concludes this chapter.
2.2 Soft Error Rate Estimation Formulation
Figure 2.1 shows a general view of a combinational circuit including the combina-
tional logic gates, as well as primary inputs (PI) and primary outputs (PO). A SET
may appear in the output of the internal logic gates in addition to the interconnec-
tion between PIs and internal gates. We call each of these places in the circuit as a
circuit node (CN). Circuit node set (CNS) is defined as the set which includes all
CNs. The SET originated at any CNs of CNS may be latched in each element con-
sidered in POs.
Soft error rate of such a combinational circuit (SERc) can be calculated as fol-
lows [4]:
SER c = RPH ⋅ α ⋅ Ac ⋅ P ( SE c ) (2.1)
where RPH is the particle hit rate per unit of area, α is the fraction of effective particle
hits (those resulting in charge generation), Ac is the total silicon area of the circuit,
and P(SEc) is the probability of occurrence of a soft error in the combinational cir-
cuit conditioned on an effective particle hit. Details about the value of RPH ∙ α are
well provided in [4, 7]. Hence, we focus on estimating the probability that a SET at
a given gate G of the circuit will result in a soft error of at least one of the POs.
Based on [6], the probability of SEc can be calculated as
NCNS wmax
1
P ( SE c ) =
N CNS
∑ ∫ P ( E ) ⋅ f ( w ) ⋅ dw
i =1 wmin
i,w (2.2)
Circuit Node
(CN)
SET
D
SET
Q D Q
SET
D
SET
Q D Q
SET
D
SET
Q D Q
G
SET
D
SET
Q D Q
CLR Q CLR Q
CLR Q
CLR Q
CLR Q CLR Q
CLR Q CLR Q
Primary Primary
Inputs (PI’s) Outputs (PO’s)
Fig. 2.1 A general view of a combinational circuit

2.2 Soft Error Rate Estimation Formulation 11
where:
• NCNS is the number of circuit nodes (i.e., circuit gate outputs), and (wmin, wmax) are
the (minimum, maximum) width of SETs in the circuit nodes.
• Ei, w is the event of any PO failing (experience of a soft error) given that the SET
occurs at the output of the CNi with the initial width of w and P(Ei, w) is the prob-
ability of Ei, w.
• f(w) is the probability density function of random variable  ∈ ( wmin ,wmax ) .
The type of function f(w) depends on different factors such as the particles’
energy and the critical charge for circuit transistors [8, 9]. There have been several
works that present different ways to determine f(w) [4, 10]. Hence, in order to cal-
culate the probability of SEc, we focus on calculating the probability of Ei, w (which
will be noted as Ei hereinafter for simplicity).
In its turn, Ei can be defined formally as
N PO
Ei =  Eij (2.3)
i =1
where NPO is the number of POs and Eij is the event of a soft error observed in PO
j due to the SET that occurred in CNi with the initial width of w.
Using the addition law of probability [6], Eq. (2.3) can be written as
 NPO 
P ( Ei ) = P  ∪ Eij 
 j =1 
(2.4)
N OP N PO N PO N PO N PO
 k 
= ∑P Ei ( ) + ∑ ( −1)
j1 k +1
∑ ∑ … ∑ P  ∩ Eijn 
j1 =1 k =2 j1 =1 j2 = j1 +1 jk = jk −1 +1  n =1 
where P
( )
 n =1 Eijn refers to the probability of the event that the occurred SET in
k
the CNi will result in all PO j1 to jk.
( )
P  n =1 Eijn is equal to zero when there is no chain of connected logic gates or
k
logical path from CNi to all PO j1 to jk; otherwise it is not equal to zero. In order to
reduce the complexity of the estimation process, we assume that different primary
outputs of the circuit are independent [3, 11, 12]. So, the overall error probability in
(2.4) can be calculated as
NOP
P ( Ei ) = ∑P Eij1 ( )
j1 =1
(2.5)

( ( )) 
N PO N PO N PO N PO k
+ ∑ ( −1) ∑ ∑ … ∑  1 − ∏ 1 − P Eijn
k +1

k =2 j1 =1 j2 = j1 +1 jk = jk −1 +1  n =1 
Hence, in order to evaluate the SER of the circuit, it is enough to calculate the
( )
error probability of each CNi regarding each PO (i.e., P Eijn ). In the following, we
firstly introduce the details of PVW and then, in Sect. 2.4, we describe how to use
( )
PVW to determine P Eijn .
2.3 Probabilistic Vulnerability Window
In this section, we give a conceptual description of PVW and after that, we present
a computation model which shows how PVWs of different circuit nodes are
determined.
2.3.1 PVW Definition
Considering three masking factors (logical, electrical, and timing), we introduce

PVW which is an inference of the requirements that should be met by an SET in a
given circuit node in order to be latched as a soft error. A PVW of a given circuit
node (CNi) consists of four different parameters, i.e., (OIDw, STw, Ww ( ) , Psen),
01
which are characterized as follows:

• Output ID (OIDw): The identification number of the memory element in which
the soft errors are latched due to the SETs that occur in a given circuit node
• Starting time (STw): This parameter shows the constraint on the starting time
from which the assumed SET in the given circuit node should begin in order to
be latched as a soft error.
• Width pairs ( Ww0 and Ww1 ): This pair of parameters represents the minimum
width of a given SET (with value changes in 0-1-0 and 1-0-1) which is required
for it to be latched as a soft error.
• Sensitization probability (Psen): A probabilistic value which is associated with
PVW. This value shows the probability of the event that a SET originated in the
given CNi finds a logical path to the corresponding output.
Parameters of PVW show the triple constraints which are necessary to be satis-
fied by a SET to be latched as a soft error. Ww0 and Ww1 represent the electrical
masking factor as they show the minimum required value for a SET width to be
latched as a soft error. Regarding the timing masking factor, STw shows the mini-
mum time interval within which the SET should occur so that it reaches the memory
element by the required latching timing window. Psen is related to the logical mask-
ing factor as it shows the probability that a SET is not masked due to the logical
values of the other inputs of the gate propagating it through the logical path from the
circuit gate output to PO. Hence, PVW considers the vulnerability of the circuit
nodes to SET and the resulting soft errors.
2.4 Error Probability Computation 13
2.3.2 PVW Computation Model
In order to calculate the PVWs for all circuit nodes, we firstly initiate the parameters
of the PVW for each PO and then traverse the circuit graph backward and compute
PVW parameters for all other circuit nodes.
Without loss of generality, we assume that, in PO j, there is a flip-flop with setup
time (ts) and hold time (th) and the clock frequency is equal to Tclk (Fig. 2.2a). We
take [0, Tclk] as the interval of observation as we are calculating the occurrence of a
soft error due to the propagation of a SET in the time interval between two active
clock edges (i.e., rising/falling). Considering the timing masking factor, a signal
needs to be stable for an interval from the setup time (ts) before the rising edge of
the clock until the hold time (th) after the rising edge of the clock in order to be
latched in the FF. Considering this fact, Table 2.1 indicates the initiation value
assigned to the parameters of PVW related to PO j and also a justification for our
value assignments.
For the other nodes except POs, we use a computation model which helps us to
determine the parameters of PVWs at those nodes. In Fig. 2.2b, we show an exam-
ple of a circuit in which the output of logical gate related to CNi is connected to the
input in ki of the logical gate with propagation delay tp related to the circuit node
CN i∗ . Given that the parameters of PVWi∗j are determined, Table 2.2 shows how to
calculate the parameter for PVWi j .
2.4 Error Probability Computation
In this section, we describe how to use PVWs to calculate the SER of a circuit by
computing the error probability of each CNi regarding each PO (i.e., P Eijn ). ( )
ts+ th Ww,i
Ww,i*
TClk i
Gi D
SET
Q
PVWi j i*
PVWGi CL R Q OIDw = j in PVWi* j
FFj STw =STw,i* -tp OIDw = j
OIDw = j
STw = Tclk -ts
W 0w = f 0 (Ww,i*,tp) STw =STw,i*
W 0w = ts + th W 1w = f 1 (Ww,i*,tp) W 0w=W 0w,i*
W 1w = ts + th Psen = Psen,i* .pin W 1w=W 1w,i*
Psen = 1 Psen = Psen,i*
(a) PVW initialization (b) General View of PVW Computation
Fig. 2.2 A sample of PVW parameter computation. (a) PVW initialization. (b) General view of
PVW computation
Table 2.1 PVW parameter initiation and justifications

Initiation
Parameter value Justification
OIDw j The circuit node is connected to the PO j
STw Tclk – ts The SET originated at PO j should start (reaches to the switching
threshold of the FF in PO j) before the time Tclk – ts; otherwise it will not
be considered as a valid value by FF in PO j and will be masked through
timing masking factor [10]
ts + th The SET originated at the input of PO j should continue onto Tclk + th
(W 0
w ,Ww1 ) which means that its width should be more than ts + th; otherwise it is
assumed to be masked through timing masking factor [10]. Since the
type of SET (i.e., 0-1-0 or 1-0-1) makes no difference in the latching
process, the initial value is equal for both elements of this pair
Psen 1 There is no gate in the path of occurred SET to the PO; there is certainly
a synthesized path to PO
Considering the definition of Eijn and logical, electrical, and timing masking
factors, we define three events of Eij,ln / Eij,en / Eij,tn as follows: the SET occurred in CNi
to be latched as a soft error in PO j despite the impacts of logical/electrical/timing
masking factors. These events can be formally defined based on the parameters
of PVWs.
In order to be latched at the PO jn, the SET occurring in the CNi should satisfy
the setup time and hold time conditions as it has been assumed that there is a FF in
PO jn. Considering the definition of PVW, this condition implies the necessary con-
ditions for the parameters of the SET at CNi as follows:
• The starting time of SET should be less than the parameter STw.
0 1
(
• The width of the SET at CNi has to be larger than the Ww ,Ww of PVWi jn . )
So, for the starting time ( ts,SETi ) and ending time of transition of SET with width
WSETi in CNi, we have
ts,SETi < STw (2.6)
ts,SETi + WSETi > STw + Ww (2.7)
where Ww represents both Ww0 and Ww1 parameters. Thus, we can express the con-
dition by
ts,SETi ∈ STw + Ww − WSETi ,STw  (2.8)
In addition, for the width of the SET, we have
Ww < WSETi < τ (2.9)

Table 2.2 PVW parameter computation model
2.4
Parameter Propagated value Justification

This parameter is not changed.
PVWi j ⋅ OID w PVWi∗j ⋅ OID w
As the SET in i* has to propagate through a gate g with
PVWi j ⋅ STw PVWi∗j ⋅ STw – t p delay propagation equal to tp, it should start in a time tp
before the time it should start in j.
This model is based on the glitch attenuation model used in
PVWi j ⋅ ( Ww0 ,Ww1 ) (
f x PVWi∗j ⋅ Wwx : ) [1]. x can be either 1 for PVW related to 0-1-0 SETs or 0 for
PVW related to 1-0-1 SETs. If the gate i* has a non-inverting
x
if PVWi∗j ⋅ Wwx > t rf ⋅ 1.25 + ( −1) ⋅ t plh − t phl :
( ) Boolean logic (like AND, OR), the computed result of f 0
Error Probability Computation
and f1 will be assigned to PVWi j ⋅ Ww0 or PVWi j ⋅ Ww1 ,

x
PVWi∗j ⋅ Wwx + ( −1) ⋅ t phl − t plh respectively. Otherwise, if i* is a gate with an inverting
Boolean logic (like NOT, NAND, NOR), the result of
computation of f 0 and f1 will be assigned to PVWi j ⋅ Ww1 or
(
f x PVWi∗j ⋅ Wwx : ) PVWi j ⋅ Ww0 , respectively. trf refers to the rising/falling time
of the gate i* which is obtained by a pre-characterization
x
if PVWi∗j ⋅ Wwx < t rf ⋅ 1.25 + ( −1) ⋅ t plh − t phl :
( ) process. For a 0-1-0 SET (with PVWi j ⋅ Ww0 ) trf equals the
rising time and for a 1-0-1 SET (with PVWi j ⋅ Ww1 ), trf is
equal to the falling time of i*.
∗
( trf ⋅1.25) ( PVWi j ⋅ Wwx + tphl + tplh )
( trf ⋅1.25) + tphl + tplh
This approach is similar to the gate error model used in [13]
PVWi j ⋅ Psen using Boolean difference calculus. Pr(∙) represents the signal
 ∂f  probability function and returns the probability of its
PVWi∗j ⋅ Psen ⋅ Pr  i 
 ∂in k  ∂fi
 i  Boolean argument to be “1” and is the partial
∂in ki
Boolean difference of the Boolean function f of CNi with
respect to a single variable, in ki , returning the condition (on
the rest of the variables) under which function f is sensitive
15
to the input variable in ki .

where τ is the maximum possible width for SETs in a specific technology node [8,
9]. Please note that WSET and τ depend on different parameters especially the operat-
ing environment. In space applications, τ will be higher than in standard commercial
applications because of the presence of highly energetic particles.
More formally, we redefine events Eij,en and Eij,tn in terms of (2.8) and (2.9) as
Eij,ne : Ww < WSETi < τ (2.10)
Eij,nt : ts,SETi ∈ [STw + Ww − WSET ,STw ] (2.11)
Considering the effects of all three masking factors, the events Eij,ln , Eij,en , and
E should occur simultaneously. So, the probability of Eijn can be calculated as
jn
i ,t
the probability of the intersection of these events, i.e.,
( ) (
P Eijn = P Eij,nl ∩ Eij,ne ∩ Eij,nt ) (2.12)
However, as the logical masking depends on the Boolean functions implemented

by the logical gates and the electrical and timing masking factors are dependent on
the propagation delay of the gates, we can conclude that Eij,ln and Eij,ne ∩ Eij,nt are
independent events. Hence, we have
( (
P Eij,nl ∩ Eij,ne ∩ Eij,nt )) = P ( E ) ⋅ P ( E
jn
i,l
jn
i ,e ∩ Eij,nt ) (2.13)
Considering the definition of parameter Psen of PVW, the probability of Eij,ln is

equal to parameter Psen of the corresponding PVW which has been computed in
CNi, i.e.,
( )
P Eij,ln = Psen (2.14)
The probability of the intersection of Eij,en and Eij,tn can be written as
( ) (
P Eij,ne ∩ Eij,nt = P ts,SETi ∈ STw + Ww − WSETi ,STw  ∩ WSETi > Ww )
  
= P  ts,SETi ∈ STw + Ww − WSETi ,STw  ∩  ∪WSETi = WSETi , k   (2.15)
  k 
( ( ) (
= ∑ P ts,SETi ∈ STw + Ww − WSETi ,STw  |WSETi = WSETi , k ⋅ P WSETi = WSETi , k
k
))
where { WSETi , k } is the set of possible SET widths which may occur in CNi.
Similar to [10–12], we assume that ts,SETi is uniformly distributed in the interval
(T1, T1 + Tclk – WSETi , k ) (T1 equals the maximum delay from PIs to CNi). Thus, in the
2.4 Error Probability Computation 17
Sink Node
Source Node G3
G4 G1
G2
Fig. 2.3 An example of a reconvergent path in a circuit
worst case when, for a given SET duration WSET,k, the interval STw + Ww − WSETi ,STw 
lies inside it we have
(
P ts,SETi ∈ STw + Ww − WSETi ,STw  |WSETi = WSETi , k )
WSETi , k − Ww (2.16)
= , Ww < WSETi < τ
Tclk − WSETi , k
( )
Considering (2.12)–(2.16), the value of P Eijn can be evaluated which is the
main part of SER estimation of a combinational circuit as mentioned in Sect. 2.2.
It is notable that this equation calculates a situation in which only one PVW has
been computed to CNi. However, there is a different situation in which more than
one PVW may be propagated to the circuit node. This situation occurs when there
is more than one path from POs to CNi. In other words, there is a reconvergent path
in the circuit. In the following, we extend the proposed model to address the recon-
vergent path case.
2.4.1 Handling Reconvergent Paths
Figure 2.3 shows an example of a circuit with a reconvergent path. We call a circuit
node with a reconvergent fan-out as the source node and the circuit node in which
the logical paths will reach together is called as the sink node.
Considering Fig. 2.3, the PVWs of the corresponding circuit node of G5 are cal-
culated based on the PVWs of the circuit node related to G2, G3, and G4. Hence,
there are at least two PVWs for CNs related to G5. So, the number of PVWs is more
than one in the source nodes of reconvergent paths. We gather all PVWs calculated
for a given source node CNi with the same OID jn in a set called PVWi jn , i.e.,
{
PVWi jn = PVWi ,jkn |k = 1… N RF } (2.17)
where NRF is the number of PVWs in set PVWi jn .

In order to address the reconvergent path case, regarding the event Eijn in source
node CNi, we have NRF events which may result in a soft error in the circuit, i.e., an
event leading to error by propagating SET through k paths (k = 1 to NRF) from CNi
to PO jn. We show these events by Eij,nk . The error probability of CNi related to PO
jn can be computed as
 NRF  NRF
( )
P Eijn = P  ∪Eij,nk  = ∑P Eij,nk ( )
 k =1  k =1
N RF N RF N RF N RF
(2.18)
 m 
+ ∑ ( −1) ∑ ∑ … ∑ P  ∩Ei , kl 
m +1
m =2 k1 =1k2 = k1 +1 km = km −1 +1  l =1 
( )
where the value of P Eij,nk can be computed based on (2.12)–(2.16) using the
parameters of individual PVWs in PVWi jn .
The value of P m
(
E )
can be determined using the similar approach used in
( ) can be calculated as
l =1 i , kl
m
this section. For the general case with m PVWs, P l =1
Ei , kl
 m   m k 
P  ∩Ei ,kl
 l =1
 =  ∏P Ei ,l 
  k =1
( )

 WSETi ,k − ( PVWi ⋅ ETw − PV VWi ⋅ BTw ) 
× ∑
k 
 Tclk − WSETi , k
⋅ P WSETi = WSETi , k ( )  (2.19)

such that ( PVWi ⋅ ETw − PVWi ⋅ BTw ) < WSETi ,k < τ .
where the parameters PVWi ∙ BTw and PVWi ∙ ETw are defined as
PVWi ⋅ BTw = min ( PVWi , k ⋅ STw ) (2.20)

k =1 to m
(
PVWi ⋅ ETw = max PVWi , k ⋅ STw + PVWi , k ⋅ Ww 0 /1
k =1 to m
) (2.21)
2.5 Error Probability Estimation Algorithm
As the major step of SER analysis, the procedure of error probability computation
is shown in Algorithm 2.1. Generally, the soft error rate of a given combinational
circuit is computed by following the steps below:
1. Circuit Graph Construction (CG): All circuit nodes from PO to every reachable
PI are included in a tree while the PO is its root and a subset of PI is its leaves.
This tree is extracted using the backward level-ordered algorithm [14] (line 2).
2.5 Error Probability Estimation Algorithm 19
2. Levelizing: The circuit nodes in the CG of each PO are levelized using the topo-
logical sorting algorithm [14]. Please note that the traditional topological sorting
is performed with a modification on the edge direction of the circuit graph; that
is, if there is an edge (u, v) in the circuit graph, then u appears after v in the list
(line 2).
3. PVW and Error Probability Computation: For the nodes which are directly con-
nected to POs, the PVW set contains one PVW which is determined by the ini-
tialization step using Table 2.1 (line 4). For each circuit node CNi, the estimation
( ) ( ) j
procedure of P Eij (and also P Ei n ) is performed considering the number of
elements of the PVW set (lines 9–13). After calculating the error probability of
the nodes connected to POs, the PVW set of the fan-in gates of the circuit nodes
(i.e., the gates which are connected to the gate) are computed using the proposed
computation model in line 15. This cycle of the estimation procedure of P Eij ( )
and the PVW computation is repeated level by level until all gates in all levels
are visited. So, the error probability of the combinational circuit is gradually
computed based on the error probability of the circuit nodes considering (2.12)–
(2.16). SER of the circuit is finally determined by (2.5), (2.2), and (2.1).
Algorithm 2.1 Error Probability Estimation

1: Input: Gate-level Netlist, Gate Delays (tp, trf, tphl, tplh), FF timings (ts,
th), Tclk
2: Extract the circuit graph (CG) and levelize it
3: For each CN of POs input
4: PVW Initialization // Table 2.1
5: End For
7: For each level
8: For each CNi
9: Compute Ei for one PVW // Section 2.4
10: If N(PVWi) > 1 // more than one PVW
11: Compute Ei for more than one PVW //
Section 2.4.1
12: End If
13: For all fan-in (CNk) of CNi
14: Compute PVW // Table 2.2
15: Add to PVWk
16: End For
17: End For
18: End For
2.6 Experimental Results
In this section, we investigate the efficiency and accuracy of the proposed method
comparing with a Monte Carlo-based fault injection technique as the refer-
ence model.
2.6.1 Reference Model
A Monte Carlo-based fault injection simulation (MCFI) technique is used as a refer-

ence model. In MCFI, SETs with specific initial widths are injected at the output of
random fault sites (i.e., circuit gate outputs) at a random time within the clock
period. During the fault injection, SETs are propagated to FFs at POs using timing-
accurate simulations (i.e., the timing of circuit paths is considered to affect the sig-
nals in the circuit while the SETs are injected and propagated to FFs). MCFI
terminates if the maximum variance of the estimated value becomes 2% while the
confidence level is 99%.
2.6.2 Accuracy/Runtime Investigation
The proposed SER estimation method has been implemented with C++ and applied
to the well-known combinational circuits in ISCAS’85 benchmark suite for 45 nm
BPTM library technology [15]. All simulations have been run on a Linux machine
with a Pentium Core Duo (2.8 GHz) processor and 4 GB RAM. In order to find the
error probability of the circuits using the proposed method, the initial width of SETs
is set to 200 ps while the clock cycle period (Tclk) used is 1000 ps. The setup (ts) and
hold (th) times for the flip-flops at POs are set to 10 ps.
Fig. 2.4 Comparison of the accuracy of the proposed approach with the MCFI technique consid-
ering different Psen thresholds (Psen) for PVW screening
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laws of the country where you are located before using this
eBook.
Title: How to become a scientist

Giving interesting and instructive experiments in
chemistry, mechanics, acoustics and pyrotechnics
Author: Aaron A. Warford
Release date: August 30, 2023 [eBook #71522]
Language: English
Original publication: New York: Frank Tousey, 1900
Credits: Demian Katz, Craig Kirkwood, and the Online

Distributed Proofreading Team at https://www.pgdp.net
(Images courtesy of the Digital Library@Villanova
University.)
*** START OF THE PROJECT GUTENBERG EBOOK HOW TO

BECOME A SCIENTIST ***
Transcriber’s Notes:
The Table of Contents was created by the transcriber and placed in the public
domain.
Additional Transcriber’s Notes are at the end.
CONTENTS
How to Become a
Scientist.
Pneumatic Amusements.
Amusements in
Mechanics.
Arithmetical Amusements.
How to Become a
Chemist.
Acoustics.
Fireworks.
How to Become a Scientist.
GIVING
Interesting and Instructive Experiments

IN
CHEMISTRY,
Mechanics, Acoustics
AND
PYROTECHNICS.
ALSO CONTAINING
MATHEMATICAL PROBLEMS and PUZZLES

BOTH
USEFUL AND AMUSING.
New York:
FRANK TOUSEY, Publisher,
24 Union Square.
Entered according to Act of Congress, in the year 1900, by
FRANK TOUSEY,
in the Office of the Librarian of Congress at Washington, D. C.
How to Become a Scientist.
Chemistry, optics, pneumatics, mechanics, and mathematics, all
contribute their share towards furnishing recreation and sport for the
social gathering, or the family fireside. The magical combinations
and effects of chemistry have furnished an almost infinite variety of
pleasant experiments, which may be performed by our youthful
friends with great success if a little care be taken; and the other
branches of natural science are nearly as replete with interest.
The following repertoire of such tricks and illusions will be found
exceedingly complete, although pains have been taken to select only
the best and most startling of them. A large number are entirely new,
but are described with sufficient clearness to enable any person of
ordinary intelligence to become expert in them, with a little practice.
Chemical Amusements.
Chemistry is one of the most attractive sciences. From the beginning
to the end the student is surprised and delighted with the
developments of the exact discrimination, as well as the power and
capacity, which are displayed in various forms of chemical action.
Dissolve two substances in the same fluid, and then, by evaporation
or otherwise, cause them to reassume a solid form, and each
particle will unite with its own kind, to the entire exclusion of all
others. Thus, if sulphate of copper and carbonate of soda are
dissolved in boiling water, and then the water is evaporated, each
salt will be reformed as before. This phenomenon is the result of one
of the first principles of the science, and as such is passed over
without thought; but it is a wonderful phenomenon, and made of no
account, only by the fact that it is so common and so familiar.
It is by the action of this same principle, “chemical affinity,” that we
produce the curious experiments with
Sympathetic Inks.
By means of these, we may carry on a correspondence which is
beyond the discovery of all not in the secret. With one class of these
inks, the writing becomes visible only when moistened with a
particular solution. Thus, if we write to you with a solution of the
sulphate of iron, the letters are invisible. On the receipt of our letter,
you rub over the sheet a feather or sponge, wet with a solution of
nut-galls, and the letters burst forth into sensible being at once, and
are permanent.
2. If we write with a solution of sugar of lead, and you moisten with a
sponge or pencil, dipped in water impregnated with sulphureted
hydrogen, the letters will appear with metallic brilliancy.
3. If we write with a weak solution of sulphate of copper, and you
apply ammonia, the letters assume a beautiful blue. When the
ammonia evaporates, as it does on exposure to the sun, the writing
disappears, but may be revived again as before.
4. If you write with the oil of vitriol very much diluted, so as to prevent
its destroying the paper, the manuscript will be invisible except when
held to the fire, when the letters will appear black.
5. Write with cobalt dissolved in diluted muriatic acid; the letters will
be invisible when cold, but when warmed they will appear a bluish
green.
We are almost sure that our secrets thus written will not be brought
to the knowledge of a stranger, because he does not know the
solution which was used in writing, and, therefore, does not know
what to apply to bring out the letters.
To Light a Candle Without Touching the Wick.

Let the candle burn until it has a good long snuff; then blow it out
with a sudden puff, a bright wreath of white smoke will curl up from
the hot wick. Now, if a flame be applied to this smoke, even at a
distance of two or three inches from the candle, the flame will run
down the smoke and rekindle the wick in a very fantastic manner. To
perform this experiment nicely, there must be no draught or
“banging” doors while the mystic spell is rising.
Magic Milk.
Lime-water is quite transparent, and clear as common spring water;
but if we breathe or blow into it, the bright liquid becomes opalescent
and as white as milk.
The best way to try this simple experiment is to put some powdered
quicklime into a wine bottle full of cold water; shake them well
together, now and then, for a day; then allow the bottle to remain
quiet till the next day, when the clear lime-water may be poured off
from the sediment. Now fill a wine-glass or tumbler with the lime-
water thus made, and blow through the liquid with a glass tube, a
piece of new tobacco-pipe, or a clean straw, and in the course of a
minute or so—as the magicians say—“the water will be turned into
milk.” By means of this pastime “Wise Men” can ascertain which
young ladies are in love and which young gentlemen are not. With a
shrewd guess they present, as a test, a glass of lime-water to the
one and of pure water to the other, with unerring effect.
The Mimic Vesuvius.

This experiment is a demonstration of the heat and light which are
evolved during chemical combination. The substance phosphorus
has a great affinity for oxygen gas, and wherever it can get it from it
will, especially when aided by the application of heat. To perform this
experiment, put half a drachm of solid phosphorus into a Florence
oil-flask, holding the glass slantingly, that the phosphorus may not
take fire and break the glass; pour upon it a gill and a half of water,
and place the whole over a tea-kettle lamp, or any common lamp
filled with spirits of wine; light the wick, which should be about half an
inch from the flask; and as soon as the water is boiling hot, streams
of fire, resembling sky-rockets, will burst at intervals from the water;
some particles will also adhere to the sides of the glass, immediately
displaying brilliant rays, and thus continue until the water begins to
simmer, when a beautiful imitation of the aurora borealis will
commence and gradually ascend until it collects into a pointed cone
at the mouth of the flask; after a half a minute, blow out the flame of
the lamp, and the apex of fire that was formed at the mouth of the
flask will rush down, forming beautiful illumined clouds of fire, rolling
over each other for some time; and when these disappear, a
splendid hemisphere of stars will present itself. After waiting a
minute or two, light the lamp again, and nearly the same phenomena
will be displayed as at the beginning. Let a repetition of lighting and
blowing out the lamp be made for three or four times, so that the
number of stars may be increased; and after the third or fourth act of
blowing out the lamp, the internal surface of the flask will be dry.
Many of the stars will shoot with great splendor from side to side,
while others will appear and burst at the mouth of the flask. What
liquid remains in the flask will serve for the same experiment three or
four times, without adding any water. Care should be taken, after the
operation is over, to put the flask in a cool and secure place.
The Real Will-o’-the-Wisp.

Into a small retort place about an ounce of strong liquor of potash;
that is, pure potash dissolved in water, together with about a drachm
of phosphorus. Let the neck or beak of the retort dip into a saucer of
water, say half an inch deep; now very gently heat the liquid in the
retort with a spirit-lamp until it boils. In a few minutes the retort will be
filled with a white cloud; then the gas generated will begin to bubble
at the end of the saucer; a minute more, each bubble, as it issues
from the boiling fluid, will spontaneously take fire as it comes into the
air, forming at the same time the philosopher’s ring of phosphoric
acid. Care is required in handling phosphorus; but our young
chemical readers will, we think, not forego this wonderful experiment
for the want of due attention; for, without proper care on their part,
we must give up showing them wonders even greater than these.
The Paper Oracle.

Some amusement may be obtained among young people by writing,
with common ink, a variety of questions, on different bits of paper,
and adding a pertinent reply to each, written with nitro-muriate of
gold. The collection should be suffered to dry, and put aside, until an
opportunity offers for using them. When produced, the answers will
be invisible; desire different persons to select such questions as they
may fancy, and take them home with them; then promise, if they are
placed near the fire during the night, answers will appear written
beneath the questions in the morning; and such will be the fact, if the
paper be put in any dry, warm situation.
The Mimic Gas-House.

This shows a simple way of making illuminating gas, by means of a
tobacco-pipe. Bituminous coal contains a number of chemical
compounds, nearly all of which can, by distillation, be converted into
an illuminating gas; as with this gas nearly all our cities are now
lighted in the dark hours of night. To make it, obtain some coal-dust
(or walnut or butternut meats will answer), and fill the bowl of a pipe
with it; then cement the top over with some clay; place the bowl in
the fire, and soon smoke will be seen issuing from the end of the
stem; when that has ceased coming apply a light and it will burn
brilliantly for several minutes; after it has ceased, take the pipe from
the fire and let it cool, then remove the clay, and a piece of coke will
be found inside: this is the excess of carbon over the hydrogen
contained in the coal, for all the hydrogen will combine with carbon at
a high temperature, and make what are called hydrocarbons—a
series of substances containing both these elemental forms of
matter.
Alum Basket.
Make a small basket, about the size of the hand, of iron wire or split
willow; then take some lamp-cotton, untwist it, and wind it around
every portion of the basket. Then mix alum, in the proportion of one
pound with a quart of water, and boil it until the alum is dissolved.
Pour the solution into a deep pan, and in the liquor suspend the
basket, so that no part of it touch the vessel or be exposed to the air.
Let the whole remain perfectly at rest for twenty-four hours; when, if
you take out the basket, the alum will be found prettily crystallized
over all the limbs of the cottoned frame.
In like manner, a cinder, a piece of coke, the sprig of a plant, or any
other object, suspended in the solution by a thread, will become
covered with beautiful crystals.
If powdered tumeric be added to the hot solution, the crystals will be
of a bright yellow; if litmus be used instead, they will be of a bright
red; logwood will yield them of a purple, and common writing-ink, of
a black tint; or, if sulphate of copper be used instead of alum, the
crystals will be of fine blue.
But the colored alum crystals are much more brittle than those of
pure alum, and the colors fly; the best way of preserving them is to
place them under a glass shade, with a saucer containing water.
This keeps the atmosphere constantly saturated with moisture, the
crystals never become too dry, and their texture and color undergo
but little change.
The Magic Bottle.

This trick, if well managed, is one of the most wonderful that can be
performed in a drawing-room without apparatus; but it requires
dexterity at the conclusion.
The person performing the trick offers to pour from a common wine-
bottle, port-wine, sherry, milk, and champagne, in succession, and in
any order.
To accomplish the trick, you must make solutions of the following
chemicals, and label the bottles with numbers, thus:
No. 1. A mixture of two parts perchloride of iron, and one part
sulphuric acid (vitriol).
No. 2. A strong solution of the sulphocyanate of potash.
No. 3. A strong solution of acetate of lead.
No. 4. A solution of bicarbonate of soda, or potash.
No. 5. A clear solution of gum arabic.
Procure a champagne-bottle, and wash it out well; then pour three
teaspoonfuls of No. 1 into it. As the quantity is very small, it will not
be observed, especially if you are quick in your movements. Pour
some distilled or rain water into a common water-bottle, or jug, and
add a tablespoonful of No. 5 to it; then set it aside, ready for use.
Provide some wine-glasses, of four different patterns, and into one
pattern put one drop of solution No. 2; into another, three drops of
solution No. 2; rinse the third with solution No. 3, and the fourth with
solution No. 4.
Arrange the glasses on a small tray, remembering the solutions that
were poured into each pattern.
Everything being ready, take the champagne bottle that you have
prepared, from two or three others, and holding it up, to show the
company that it is clear and empty; you must desire some person to
hand you the water-bottle or jug, and then fill up the bottle with the
water.
Pour some of the contents of the bottle into an unprepared glass, in
order to show that it is water; then say: “Change to champagne,” and
pour the liquid from the bottle into one of the glasses rinsed with No.
4; then pour into the glass containing three drops of No. 2, and it will
change to port wine; but if poured into the glass rinsed with No. 3, it
will change to milk; and if into the glass with one drop of No. 2, it will
produce sherry.
Be careful in pouring the fluid from the bottle, not to hold it high
above the glasses, but to keep the mouth of it close to the edges,
otherwise persons will observe that it undergoes change of color
after it is poured into them; and, on this account, the glasses should
be held rather high.
As all the solutions used in the above trick are deleterious, they
should not be left about in the way of children, and, of course, the
fluid in the wine-glasses must not even be tasted; but if any of the
company wish to drink the wines you have made, then the tray must
be adroitly exchanged for another with the proper wines placed on it.
The Faded Rose Restored.

Take a rose that is quite faded, and throw some sulphur on a
chafing-dish of hot coals; then hold the rose over the fumes of the
sulphur, and it will become quite white; in this state dip it into water,
put it into a box, or drawer, for three or four hours, and when taken
out it will be quite red again.
The Protean Liquid.

A red liquor, which, when poured into different glasses, will become
yellow, blue, black, and violet, may be thus made: Infuse a few
shavings of logwood in common water, and when the liquor is red,
pour it into a bottle; then take three drinking-glasses, rinse one of
them with strong vinegar, throw into the second a small quantity of
pounded alum, which will not be observed if the glass has been
newly washed, and leave the third without any preparation. If the red
liquor in the bottle be poured into the first glass it will assume a straw
color; if into the second, it will pass gradually from bluish-gray to
black, provided it be stirred with a bit of iron, which has been
privately immersed in good vinegar; in the third glass the red liquor
will assume a violet tint.
The Changeable Ribbon.

Dip a rose-colored ribbon into nitric acid, diluted with eight or ten
parts of water, and as soon as the color disappears, which it will do
in a short time, take out the ribbon and put it into a very weak
alkaline solution, when the alkali will quickly neutralize the acid, and
the color will reappear.
The Chemical Chameleon.

Put a drachm of powdered nitrate of cobalt into a vial, containing an
ounce of the solution of caustic potash, when the decomposition of
the salt, and precipitation of a blue oxide of cobalt will take place.
Cork the vial, and the liquid will assume a blue color, from which it
will pass to a lilac, afterward to a peach tint, and finally to a light red.
Musical Flame.
Fit a good cork into a wine-bottle; burn a hole through the cork with a
round iron skewer, and into it fix a piece of tobacco pipe about eight
inches long. Put into the bottle about two or three ounces of zinc, in
slips, such as the waste cuttings from a zinc-worker; now pour water
on to the zinc until the bottle is more than half full; then add about
three parts of a wine-glassful of sulphuric acid (oil of vitriol); this
causes a rapid effervescence at first, but which subsides to a
moderate and continuous boiling for a lengthened period; as soon as
the boiling is regular, the cork with the pipe through it may be
inserted into the bottle. If a light be placed to the end of the pipe, a
flame will be produced, which will continue to burn so long as there
is any visible action in the bottle. This flame is the ignited hydrogen
gas (water gas), resulting from the decomposition of water by the
acid and zinc, and as such is an exceedingly interesting experiment.
Now, to be musical, procure a glass or metal pipe, about sixteen or
eighteen inches long, and from half to three-quarters of an inch in
diameter; place the tube over the flame, and allow the pipe to be
about three to five inches up the tube, which will act as a kind of high
chimney; it must be held perfectly steady and upright, at a particular
distance up the tube, which varies according to the size of the flame.
A beautiful sound is thus produced, similar to an organ-pipe. This
sound, or “musical flame,” varies in note according to the diameter of
the tube, being deeper or more bass as the tube is increased in size.
By using various-sized tubes, different sounds are thus readily
produced. The true explanation of this singular experiment remains
yet to be solved.
Optical Amusements.
The science of optics affords an infinite variety of amusements,
which cannot fail to instruct the mind, as well as delight the eye. By
the aid of optical instruments we are enabled to lessen the distance
to our visual organs between the globe we inhabit and “the wonders
of the heavens above us;” to watch “the stars in their courses,” and
survey at leisure the magnificence of “comets importing change of
times and states;” to observe the exquisite finish and propriety of
construction which are to be found in the most minute productions of
the earth;—to trace the path of the planet, in its course around the
magnificent orb of day, and to detect the pulsation of the blood, as it
flows through the veins of an insect. These are but a few of the
powers which this science offers to man; to enumerate them all
would require a space equal to the body of our work; neither do we
propose to notice the various instruments and experiments which are
devoted to purposes merely scientific; it being our desire only to call
the attention of our juvenile readers to such things as combine a vast
deal of amusement with much instruction, to inform them as to the
construction of the various popular instruments; to show the manner
of using them, and to explain some of the most attractive
experiments which the science affords. By doing thus much, we
hope to offer a sufficient inducement to extend inquiry much further
than the information which a work of this nature will enable us to
afford.
The Camera Obscura.

This is a very pleasing and instructive optical apparatus, and may be
purchased for a small sum. But it may be easily made by the young
optician. Procure an oblong box, about two feet long, twelve inches
wide, and eight high. In one end of this a tube must be fitted
containing a lens, and be made to slide backward and forward, so as
to suit the focus. Within the box should be a plain mirror, reclining
backward from the tube at an angle of forty-five degrees. At the top
of the box is a square of unpolished glass, upon which, from
beneath, the picture will be thrown, and may be seen by raising the
lid. To use the camera, place the tube with the lens on it opposite to
the object, and having adjusted the focus, the image will be thrown
upon the ground glass, as above stated, where it may be easily
copied by a pencil or in colors.
The Magic Lantern.

The object of this ingenious instrument is to represent, in a dark
room, on a white wall or cloth, a succession of enlarged figures of
remarkable, natural, or grotesque objects. It consists of a tin box,
with a funnel on the top, and a door on one side of it. This funnel, by
being bent, serves the double purpose of letting out the smoke and
keeping in the light. In the middle of the bottom of the box is placed a
movable lamp, which must have two or three good lights, at the
height of the center of the polished tin reflector. In the front of the
box, opposite the reflector, is fixed a tin tube, in which there slides
another tube. The sliding tube has, at its outer extremity, a convex
lens fixed in it, of three inches in diameter. The focus of the smaller
of these lenses may be about five inches. Between the stationary
tube and the lamp, there must be a split or opening to admit of the
passage of glass sliders, mounted in paper or wooden frames, upon
which sliders it is that the miniature figures are painted, which are
intended to be shown upon the wall. The distinctness of the enlarged
figures depends not only upon the goodness of the magnifying glass,
but upon the clearness of the light yielded by the lamp. It may be
purchased ready made of any optician.
To Paint the Glasses.—The slides containing the objects usually
shown in a magic lantern are to be bought of opticians with the
lantern, and can be procured cheaper and better in this way than by
any attempt at manufacturing them. Should, however, the young
optician wish to make a few slides, of objects of particular interest to
himself, he may proceed as follows: Draw on a paper the subject you
desire to paint. Lay it on a table or any flat surface, and place the
glass over it; then draw the outlines with a very fine pencil, in varnish
mixed with black paint, and, when dry, fill up the other parts in their
proper colors. Transparent colors must be used for this purpose,
such as carmine, lake, Prussian blue, verdigris, sulphate of iron,
tincture of Brazil wood, gamboge, etc.; and these must be tempered
with a strong white varnish, to prevent their peeling off. Then shade
them with black, or with bistre, mixed with the same varnish.
To Exhibit the Magic Lantern.—The room for the exhibition ought to
be large, and of an oblong shape. At one end of it suspend a large
sheet, so as to cover the whole of the wall. The company being all
seated, darken the room, and placing the lantern with its tube in the
direction of the sheet, introduce one of the slides into the slit, taking
care to invert the figures; then adjust the focus of the glasses in the
tube, by drawing it in or out, as required, and a perfect
representation of the object will appear.
Effects of the Magic Lantern.—Most extraordinary effects may be
produced by means of the magic lantern; one of the most effective of
which is a tempest at sea.
This is effected by having two slides painted, one with the tempest
as approaching on one side, and continuing in intensity till it reaches
the other. Another slide has ships painted on it, and while the lantern
is in use, that containing the ships is dexterously drawn before the
other, and represents ships in the storm.
The effects of sunrise, moonlight, starlight, etc., may be imitated
also, by means of double sliders; and figures may be introduced
sometimes of fearful proportions.
Heads may be made to nod, faces to laugh; eyes may be made to
roll, teeth to gnash; crocodiles may be made to swallow tigers;
combats may be represented; but one of the most instructive uses of
the slides is to make them illustrative of astronomy, and to show the
ratio of the seasons, the cause of the eclipses, the mountains in the
moon, spots on the sun, and the various motions of the planetary
bodies and their satellites.
The Phantasmagoria.
Between the phantasmagoria and the magic lantern there is this
difference: in common magic lanterns the figures are painted on
transparent glass; consequently the image on the screen is a circle
of light, having figures upon it; but in the phantasmagoria all the
glass is opaque, except the figures, which, being painted in
transparent colors, the light shines through them, and no light can
come upon the screen except that which passes through the figure.
There is no sheet to receive the picture, but the representation is
thrown on a thin screen of silk or muslin, placed between the

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Soft Error Reliability of VLSI Circuits:

Analysis and Mitigation Techniques

Ageing of Integrated Circuits: Causes, Effects and

Long Term Reliability of Nanometer VLSI Systems

Test Generation of Crosstalk Delay Faults in VLSI

Thermal-Aware Testing of Digital VLSI Circuits and

FinFET Devices for VLSI Circuits and Systems 1st

Introduction to error analysis the science of

Safety, Reliability, Human Factors, and Human Error in

Arc Flash Hazard Analysis and Mitigation 2nd Edition J.

Soft Error Reliability of

ISBN 978-3-030-51609-3 ISBN 978-3-030-51610-9 (eBook)

© Springer Nature Switzerland AG 2021

Kerman, Iran Behnam Ghavami

Behnam and Mohsen

1 Introduction: Soft Error Modeling�������������������������������������������������������� 1

3.3 Statistical Vulnerability Window (SVW)������������������������������������������ 29

5.5.2 Circuit Partitioning Acceleration Results������������������������������ 71

© Springer Nature Switzerland AG 2021 1

1.1 Impacts of Particle Strike on Semiconductor Devices

When high-energy particles strike into a sensitive part of a semiconductor device

ldiff ldrift Ion track

1.2 Single-Event Transient Modeling

1.3 Impact of a Particle Hit on Combinational Circuits

Fig. 1.3 An illustrative example of electrical masking effect

1.3.1 Electrical Masking

1.3.2 Logical Masking

1.3.3 Timing Masking

Fig. 1.4 An example of logical masking

Fig. 1.5 An example of timing masking

1. R. C. Baumann, “Soft Errors in Advanced Semiconductor Devices—Part I: The

4. M. Fazeli, S. G. Miremadi, H. Asadi and S. N. Ahmadian, “A fast and accurate multi-­

© Springer Nature Switzerland AG 2021 9

2.2 Soft Error Rate Estimation Formulation

SER c = RPH ⋅ α ⋅ Ac ⋅ P ( SE c ) (2.1)

Fig. 2.1 A general view of a combinational circuit

the CNi will result in all PO j1 to jk.

2.3 Probabilistic Vulnerability Window

2.3.1 PVW Definition

Considering three masking factors (logical, electrical, and timing), we introduce

which are characterized as follows:

2.3.2 PVW Computation Model

2.4 Error Probability Computation

(a) PVW initialization (b) General View of PVW Computation

Table 2.1 PVW parameter initiation and justifications

ts,SETi < STw (2.6)

ts,SETi + WSETi > STw + Ww (2.7)

ts,SETi ∈ STw + Ww − WSETi ,STw  (2.8)

In addition, for the width of the SET, we have

Ww < WSETi < τ (2.9)

Parameter Propagated value Justification

and f1 will be assigned to PVWi j ⋅ Ww0 or PVWi j ⋅ Ww1 ,

to the input variable in ki .

Eij,ne : Ww < WSETi < τ (2.10)

Eij,nt : ts,SETi ∈ [STw + Ww − WSET ,STw ] (2.11)

However, as the logical masking depends on the Boolean functions implemented

Considering the definition of parameter Psen of PVW, the probability of Eij,ln is

The probability of the intersection of Eij,en and Eij,tn can be written as

Kerman, Iran Behnam Ghavami

1 Introduction: Soft Error Modeling�� 1

3.3 Statistical Vulnerability Window (SVW)�� 29

5.5.2 Circuit Partitioning Acceleration Results�� 71

1.1 Impacts of Particle Strike on Semiconductor Devices

1.2 Single-Event Transient Modeling

1.3 Impact of a Particle Hit on Combinational Circuits

1.3.1 Electrical Masking

1.3.2 Logical Masking

1.3.3 Timing Masking

4. M. Fazeli, S. G. Miremadi, H. Asadi and S. N. Ahmadian, “A fast and accurate multi-

2.2 Soft Error Rate Estimation Formulation

2.3 Probabilistic Vulnerability Window

2.3.1 PVW Definition

2.3.2 PVW Computation Model

2.4 Error Probability Computation

2.4.1 Handling Reconvergent Paths

2.5 Error Probability Estimation Algorithm

2.6 Experimental Results

2.6.1 Reference Model

2.6.2 Accuracy/Runtime Investigation