Analytical Switching Loss Modeling Based On Datasheet Parameters For Mosfets in A Half-Bridge

This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2018.2851068, IEEE
Transactions on Power Electronics
Analytical Switching Loss Modelling based on

Datasheet Parameters for MOSFETs in a
Half-Bridge
Daniel Christen, Student Member, IEEE and Jürgen Biela, Senior Member, IEEE
Abstract—Modern wide-bandgap devices, such as SiC or GaN elements in the commutation path in order to accurately
based devices, feature significantly reduced switching losses and determine the characteristic current and voltage waveforms of
the question arises if soft-switching operating modes are still the MOSFET device during the switching transitions. These
beneficial. For most semiconductor devices only limited informa-
tion is available to estimate the switching losses. Especially if a models were further improved by taking the diversion process
wide operating range is desired, excessive measurements have to of the MOSFET internal current during the switching process
be performed to determine the switching losses for arbitrary into account (as e.g. proposed in [14]). There, a current
operating points. Therefore, in this paper a fast calculation through the MOSFET channel (ich ) and one to recharge the
method to determine the switching losses based on the charge parasitic capacitances (Ioss ) are distinguished, where ich is
equivalent approximation of the MOSFET capacitances, relying
only on datasheet parameters, is presented. In addition, the turn- considered to be the origin of the switching losses.
off losses at high switching currents are investigated and an However, the presented models often have a high complex-
analytical expression to estimate the maximum current range for ity and rely on device parameters, which have to be measured
which the MOSFET can be turned-off with negligible switching and are not entirely available in datasheets [15]–[17]. Thus,
losses is proposed. in this paper a model is proposed, which is based only on
Index Terms—Power MOSFET, switching losses, half-bridge datasheet parameters and enables a fast and precise estimation
of MOSFET switching losses in a half-bridge.
I. I NTRODUCTION The proposed model is based on the charge equivalent
representation of the parasitic MOSFET capacitances. On the
Despite the continuously improving semiconductor perfor- one hand, this allows the accurate determination of the voltage
mance, the switching and conduction losses of the semicon- fall and rise times, and on the other hand, it is shown that
ductors are typically still the largest loss contributors. in the considered half-bridge the charge is directly linked to
Especially in case a high switching frequency is required, the energy stored in these capacitances, and thus enables a
the switching losses have not only a significant impact on the precise estimation of the device internal loss energies. The
overall losses but also on the required volume due to their model also includes the parasitic source inductance, takes the
impact on the cooling system. Thus, an accurate calculation current dependency of the transconductance into account to
and modelling of the switching losses is one key to optimally determine the Miller Plateau in an iterative process, and esti-
design converter systems. mates the diode reverse recovery based on a simplified power
With the advance of new wide bandgap devices, which diode model presented in [18]. Based on these considerations,
have relatively low switching losses, also the question arises if a closed analytical expression to determine the maximum
soft-switching operating modes (e.g. triangular current mode current for which the semiconductor can be turned-off with
[1]) are still beneficial at high switching frequencies. This negligible losses (soft-switching) is derived.
is especially relevant for unipolar devices as for example In the following, first the switching transients during turn-
MOSFETs, which this paper focuses on. off and turn-on are step-wise analysed in section II. This
For such designs the conduction losses can be accurately includes the derivation of the underlaying equations for the
determined based on the temperature dependent on-state resis- calculation routine. A summary of the equations used in
tance provided in datasheets and the device current. However, the optimisation routine (flowchart in Fig. 6) as well as the
the switching losses often can be only determined accurately parameter extraction is described and demonstrated for an
by measurements [2]–[4]. To avoid laborious measurements, example MOSFET device in section III. The validation of the
usually analytical approaches based on linearized MOSFET model by electrical measurements is presented in section IV.
models are applied as for example described in [5]. For better Moreover, the effect of the parasitic source inductance and the
understanding the MOSFET switching transients and the effect temperature are briefly discussed.
of the parasitics several experimental studies were conducted
in the past [6]. Based on experimental results, in [7]–[13]
the analytical models have been extended by the parasitic II. M ODELLING OF THE S WITCHING L OSSES
The switching losses in a half-bridge strongly depend on the
The authors are with the Laboratory for High Power Electronic Sys-
tems, ETH Zürich, Physikstrasse 3, 8092 Zürich Switzerland (Email: applied modulation scheme. Basically, two possible switching
daniel christen@alumni.ethz.ch, jbiela@ethz.ch) scenarios can be distinguished.
0885-8993 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2018.2851068, IEEE
Considered device vds during the switching process (duration tsw e.g. given in
Fig. 2) [14]. Z
S1
Esw = ich vds dt (3)
I0 Ld tsw
V0
id For the sake of simplicity, the recharging process of the
igd
S2 parasitic device-internal capacitances is assumed to be lossless.
ids
vgd Cgd ich The current for charging the parasitic capacitances is denoted
ig Rg as Ioss = igd + ids in the following.
vds Furthermore, it is assumed that during the complete switch-
igs Cds
vgs Cgs ing transition the output current I0 is approximately constant
Vg
+ and the gate voltage Vg is ideally set with negligible rise and
- is fall times.
Ls vLs
I0= const.
A. Turn-Off
MOSFET equivalent circuit Turning a MOSFET off under ZVS conditions is often as-
sumed to result in negligible losses. However, with increasing
Fig. 1. Half-bridge switching cell and circuit equivalent of a MOSFET during current amplitudes this losses become significant and must be
the switching process. included in the loss calculation. In the following a step-wise
analysis of the turn-off process is presented to explain the
cause of these losses.
First, the conducting device is turned off and the current is
commutating to the body diode of the opposite device in the
half-bridge which, after its body diode is conducting, can be Considered device
0a
1a
2a
turned on under zero voltage conditions (ZVS).
al
al
al
rv
rv
rv
Second, the semiconductor device is turned off and the vgs
te
te
te
In S1
In
In
current is commutating to its antiparallel body diode (what
Vgs,0 I0
is assumed to be lossless). After a defined interlocking time, V0
guaranteeing that the body diode is conducting the full current Vmil
Vg S2
and the device is turned off, the opposite semiconductor device Vth
t
in the half-bridge is turned on resulting in a hard commutation t=Toff
id ,ich
of the body diode (hard turn-on). 2Qoss id ich
For both scenarios, the linearized MOSFET model depicted I0
2 Ioss
in Fig. 1 is considered. This model includes the parasitic Ich
capacitances of the device (Cds , Cgd , Cgs ) the gate resistor
t
(Rg , including internal and external gate resistors) and the vds
parasitic inductances in the commutation loops (Ls , Ld ). vLd
V0
During the switching transition, the MOSFET device is
operated in saturation. In saturation the MOSFET channel is
modelled as controlled current source ich , which is linked by t
the transconductance gm to the gate source voltage vgs by tsw
Toff
trv tfi
ich = gm (ich )(vgs − Vth ). (1)
The transconductance is a function of the current through

the MOSFET channel ich [19], which can be expressed as id
s
k1 ixch igd ich ids
gm (ich ) = x , (2)
ich − k2
Vmil vgs
The constants x, k1 and k2 , the threshold voltage Vth , and Vg + Vg +
- -
the reverse recovery behaviour of the body diode, are ex- A1 vLs
tracted from the corresponding datasheet as is discussed in I0= const. I0= const.
section III-A. Ioss,S2
With the assumption that the parasitic MOSFET capac-
itances are only lossless energy buffers, the losses in the Fig. 2. Linearized MOSFET characteristics of the gate source voltage vgs ,
device for both scenarios are mainly determined by the current the drain-source voltage vds , and the channel current ich of the MOSFET
through the MOSFET channel ich and the drain source voltage S1 during turning the device off.
In Fig. 2 the characteristic linearized waveforms for turning • Ioss is linked to the gate drain current, igd , by the
off MOSFET S1 are depicted. There, three intervals are Kirchhoff’s law for loop A1 in Fig. 2
distinguished. The losses can be estimated based on ich , vds
Cgd

and the time intervals trv and tf i . −igd = ig = −Ioss (5)
Cgd + Cds
a) Interval 0a: At t = Tof f the gate voltage of S1 is
1
reduced to Vg ≤ 0. Accordingly, a negative voltage is applied = (Vg − Vmil − vLs ) ,
across the gate resistor Rg and the gate source voltage (vgs ) Rg
decreases to the Miller voltage Vmil (saturation region). This assuming that C1gd igd = C1ds ids .
process is assumed to be lossless, since vds and the drain • The gate source voltage vgs = Vmil is linked to ich by
current id are approximately constant. equation (1)
b) Interval 1a: During interval 1a the drain source volt-
ich = I0 − 2Ioss = gm (Vmil − Vth ). (6)
age vds is rising to V0 , the parasitic capacitance of S1 (Coss =
Cgd + Cds ) is charged, and simultaneously the capacitance of In (6) vgs = Vmil and Ioss are assumed to be constant.
•
S2 is discharged. Since the voltages of these capacitances are However, the current in the channel and across the para-
clamped to the applied DC-voltage, their dv/dt have the same sitic source inductance Ls shows a nonlinear behaviour,
absolute value. Therefore, the nonlinear capacitances can be due to the capacitive current divider given by S1 and
considered as parallel connected (Cpar = Coss,1 + Coss,2 ) S2 , such that the voltage drop across Ls additionally
during the voltage transition as shown in Fig. 3. Cpar is has to be taken into account. With increasing voltage
symmetrical with respect to vds . The charge, respectively the across S1 its parasitic capacitance becomes small and
energy required to recharge the parasitic capacitances Cpar is contrariwise the one off S2 becomes large. Therefore,
Z V0 it is assumed that during interval 1 the current through
Epar (V0 ) = v · Cpar (v)dv = Qoss V0 , (4) S1 decreases from I0 to Ich . This introduces a negative
0 voltage drop vLs < 0 across the parasitic stray inductance
whereas Qoss is the voltage dependent charge stored in Coss Ls , which counteracts the applied gate voltage Vg . As a
at the voltage vds = V0 . This circumstance allows to model consequence, the voltage rise time trv is increased. The
the parasitic capacitances of the MOSFET by a single charge average voltage drop across the parasitic inductance vLs
equivalent capacitance value. could be derived by
Z trv
Equation (4) linking the stored charge and the energy 1 dis
content is only valid since Cpar for two identical devices in the vLs = Ls dt (7)
trv 0 dt
half-bridge is symmetrical with respect to vds . The effective 1 1
stored energy in S1 is Eoss,1 < 1/2Qoss V0 = 1/2Epar , and vLs = Ls (is (trv ) − is (0)) = Ls 2Ioss (8)
trv trv
has to be determined with respect to the nonlinear charac-
I2 Qoss
teristic of Coss,1 1 . As indicated in Fig. 2 and Fig. 3, ich |vLs | =2Ls oss with trv = . (9)
Qoss Ioss
is reduced by two times the current required to recharge the
parasitic capacitances Ioss = ids +igd = const during interval Based on (5), (6) and (9), a quadratic equation for Ioss
1.

2Ls 2 2 Cgd
To determine Ioss , first the basic equations describing the 0= Ioss + + Ioss (10)
Qoss Rg gm Rg Cgd + Cds
circuit during that interval have to be considered: 1

I0

+ Vg − Vth −
1 Effective energy stored in S1 : Eoss,1 =
R V0
v · Coss,1 (v)dv
Rg gm
0
results. This equation allows to calculate Ioss for an arbitrary
operating point.
Considered device Determine Ioss is an iterative process since the transcon-
Coss1
ductance gm is depending on ich . As a consequence Ioss ,
+ I0 gm (I0 − 2Ioss ) and Vmil (eq. (6)) have to be determined
V0
- iteratively. In each iteration these values have to be recalcu-
Coss2
lated until the deviation in Ioss is negligible as depicted in the
flowchart in Fig. 6.
Capacitance
Cpar=Coss1║Coss 2 Once Ioss and Vmil are calculated, the drain current id and
ich I0=const the current in the MOSFET channel ich during this interval
Ioss1 Ioss2 can be calculated by
Coss1 Coss1
Coss2 id =I0 − Ioss (11)
Voltage vds V0
a) b) ich =I0 − 2Ioss . (12)
Fig. 3. a) Considered half-bridge topology and the equivalent circuit during The voltage rise time is defined by the time required to charge
the voltage transition. ich is reduced by 2Ioss compared to I0 = const. Coss = Cgd + Cds and thus can be estimated by
c) Parallel connected nonlinear parasitic capacitances of the two (identical)
MOSFET devices. trv = Qoss /Ioss . (13)
c) Ideal Zero Voltage Switching: With equation (12) process of the parasitic capacitances are neglected. However,
follows that an ideal zero voltage switching with a nearly [20]–[22] presented energies up to 20% of the stored energy
lossless turn-off (ZVS) can be achieved if I0 < 2Ioss , since ich Eoss that are potentially lost in SiC devices during this inter-
becomes zero. In that case, the current to charge the parasitic val. Since these losses can only be experimentally determined
capacitances becomes Ioss = 1/2I0 and is not anymore they are neglected here.
depending on the gate configuration.
At the boundary of the ideal zero voltage switching, 2Ioss = B. Scenario 2: Turn-On
I0 , Vmil equals Vth and ich becomes zero. In this case, A similar analysis can be performed when MOSFET S1 is
expression (10) can be simplified and the resulting maximum turned on, while the body diode of S2 is conducting. The
current for which a lossless turn-off is expected is characteristic waveforms are shown in Fig. 4. During the

V0 switching process four intervals are distinguished which are
I0,zvs = − Rg Cgd + ... (14) analysed in the following. For t < Ton , MOSFET S2 is
2Ls
s  turned off (approximately lossless) and its body diode starts
Ls (Cgd + Cds )  conducting.
(Rg Cgd )2 − 8(Vg − Vth )
V0 a) Interval 0b: After the interlocking time, S1 is turned
on at Ton , a positive Vg is applied and the gate source voltage
With increasing gate resistance Rg or source inductance Ls , vgs rises to Vth . During this interval the drain source current
igd and accordingly Ioss decreases. As a consequence I0,zvs is approximately zero. Thus, no impact on the losses in the
is also at a lower current. devices is assumed.
Equation (14) can be used to find the required snubber b) Interval 1b: As soon as vgs reaches the threshold
capacitance (increasing Cds ) to mitigate the switching losses voltage Vth (saturation region), the drain current rises to I0
during the turn-off at high currents2 or to check if the
assumption of negligible turn-off losses is still valid.
Considered device
0b
te l 1b
2b
3b
If I0 is small, relatively long switching intervals result, since
al
al
al
a
rv
rv
rv
rv
the charging current for Coss becomes small. Turning S2 on vgs
te
te
te
In
In
In
In
before the recharging process ends results in a partial hard S1
Vg,on
turn-on as described in [20]. Vmil I0
V0
When current I0 exceeds 2Ioss , ich is increasing, what
results in significant switching losses. Furthermore, the re- S2
Vth
maining current in the channel has to be decreased to zero id ,ich t
ich id
in interval 2a. t=Ton
d) Interval 2a: When the voltage across S1 reaches V0 , Irr 2 Ioss
I0
the body diode of S2 starts conducting. The time tf i (Interval 2Qoss
2a in Fig. 2), in which the remaining current Ich commutates
to the body diode of S2 , is proportional to the gate source t
vds
voltage, which decreases from Vmil to Vth . To find tf i , the vLd
V0
loop consisting of Cgs , Ls , and Rg is considered, whereas Vds,0
vLs (t) = Ls ∂is (t)/∂t ≈ Ls ∂(gm (vgs (t) − Vth ))/∂t. By
solving the partial differential equations tf i can be expressed
as t
tsw

Vth + Vg Ton
tf i = − ln (Cgs Rg + Ls gm ). (15) tri trs tfv
Vmil + Vg
Since the current is decreasing, a voltage drop across the
parasitic inductance Ld is observed, which results in an ich=I0+Ioss,S2+Ioss,S1 id=I0+Ioss,S2
increased vds by
VLd = Ld (I0 − 2Ioss )/tf i . (16)
vgs Vmil
Summing up the loss shares of interval 1a and 2a, the total Vg + Vg +
- -
loss energy in S1 during turn-off is A1 vLs
1 1 I0= const. I0= const.
ET,of f = trv V0 (I0 − 2Ioss ) + tf i (V0 + VLd )(I0 − 2Ioss ).
2 2 Ioss,S2
(17)
There, the forward recovery losses of the diode of S2 are
assumed to be negligible. Also the losses due to the recharging
Fig. 4. The linearized MOSFET characteristics of the gate source voltage vgs ,
2 If
a snubber capacitance is employed, a (partial) hard turn-on has to be the drain-source voltage vds and the channel current id0 when the MOSFET
avoided, since the energy stored in the capacitances can be high and is lost S1 is turned on. Below, the applied equivalent circuit to calculate the switching
during the switching process (below described in Scenario 2: Turn-on). losses is depicted.
ibd gate characteristic of MOSFET S1 . Thus, T1 can be found by

I0 (e.g. numerical) solving (21) for T1
Qrr= Qrs+Qrf
S1 Coss1 dibd dibd I0
qe (T1 ) = 0 = qm (T1 ) + Tm(I0 − T1 ) with = (22)
trr dt dt tri
I0
trs trf V0 Knowing T1 , the values Irr , Qrs and trs (see Fig. 5 a) can
t
ibd
be determined by
0 Qrs Qrf Coss2
-Irr e-(t-T1)/τ
rr trs =T1 − T0 (23)
-Irr
I0
T0 T1 T2 Body diode of S2 Irr =trs (24)
a) b)
tri
1
Fig. 5. a) Characteristic current waveform during the reverse recovery effect Qrs = trs Irr (25)
of the body diode of S2 . b) Equivalent circuit when the body diode of S2 is 2
conducting. Notice that Coss is connected in parallel to the body diode. Current I0 is the current in the diode during the conducting
state and T0 is the time when the current through S2 crosses
proportional to vgs (see Fig. 4 Interval 1b). The current rise zero. The above described equations can be used to extract
time tri is calculated analogue to the turn-off (see Fig. 4 b the diode parameters from a datasheet as is demonstrated in
loop A1 ) by section III-A.
For an arbitrary operating point the additional loss energies
I0 in MOSFET S1 due to the reverse recovery effect are Ers
tri = − ln 1 − (Cgs Rg + Ls gm ). (18)
gm (Vg − Vth ) for the reverse conducting phase and Erf for the recovery
Due to the rising current, also a voltage across the parasitic phase. They are determined based on the time integral of the
inductance vLd = Ld I0 /tri is observed and vds decreases to respective current and the voltage.
Vds,0 . Contrary to the turn-off discussed above, Ld reduces the Ers =Qrs Vds,0 (26)
switching losses. For the sake of simplicity, here a small Ld Z T2
is assumed, such that the voltage drop on vds has no influence Erf = −ibd (t)vds (t)dt
on the predetermined voltage dependent charge equivalent T1
τrr
capacitances. =Irr Vds,0 tf v − τrr + τrr e−tf v /τrr (27)
c) Interval 2b and Diode Reverse Recovery Model: tf v
When id reaches I0 , the current increases further (see Fig. 4 The loss energy in the body diode of S2 are similarly calcu-
Interval 2b) due to the reverse recovery effect of the body lated by
diode of S2 .
Err,S2 = ED,of f,S2
To estimate the time duration during which the body diode
τrr
is reverse conducting trs , a model for a power diode derived = Irr Vds,0 τrr − (τrr + tf v )e−tf v /τrr
in [18], [23]–[25] is applied, which is briefly summarized in tf v
the following. + τrr Irr V0 e−tf v /τrr . (28)
Within this model, the characteristic diode current waveform
d) Interval 3b: As soon as the body diode of S2 blocks,
(see Fig. 5 a)) can be calculated based on three characteristic
the voltage across S1 decreases. Analogue equations as for
values of the diode: the drift region transit time Tm , the
interval 1a of the turn-off of MOSFET S1 can be applied to
effective carrier life time τc and the time constant τrr during
determine Vmil and Ioss (which becomes negative) whereas
the recovery phase trf . The diode current ibd during this
the underlying quadratic equation is
interval is
2Ls 2 2 Cgd
I0 − didtbd t = tIri0 t t < T1
(
0=− Ioss + + Ioss (29)
ibd (t) = t−T1 (19) Qoss Rg gm Rg Cgd +Cds
−Irr e− τrr t ≥ T1

1 I0
+ Vg −Vth −
To determine Irr and Qrr for an arbitrary operating point Rg gm
the analytical equations (20) and (21) describing the lumped As described above, this is a iterative process where Ioss ,
charge model of a diode [18] has to be solved. gm and Vmil have to be adapted in each iteration step. To
qe − qm calculate the drain and the channel current, id and ich , during
ibd (t) = (20) this interval also expressions (11) and (12) can be applied.
Tm
dibd Notice that during this interval the channel current is increased
qm (t) = τc T0 + τc − t − τc e−t/τc t < T1 (21) by 2|Ioss | due to the charging current required to charge Coss
dt
of S2 (assuming I0 = const) and due to the device internal
There qe represents the injected minority charge carriers
discharging process of S1 .
established by the diode current and qm represents the internal
The resulting fall time of the drain-source voltage of S1 is
available charge carriers. Charge qe gets zero at T1 [18], when
approximately
the diode becomes reverse blocking. This current is assumed Qoss
to be linearly decreasing, whereas the slope is defined by the tf v = − (30)
Ioss
Summarizing, the loss energy when MOSFET S1 is turned SiC MOSFET C2M0080120D (1200V, 80mΩ, Wolfspeed) is
on is considered, which is operated at V0 =600 V and I0 is varied
1 1 in the range of [0 A...40 A] at a junction temperature of 25 ◦C.
ET,on = tri Vds,0 I0 + tf v (I0 − 2Ioss )Vds,0 +
2 2
trs Vds,0 I0 + Erf + Ers (31) A. Step 1: Parameter Extraction
III. A PPLICATION OF THE SWITCHING LOSS MODEL The main parameters of the device have to be extracted from
the datasheet, what is briefly explained in the following.
In the following, the flowchart in Fig. 6 for applying the 1) MOSFET Parameters: To evaluate the switching losses,
model in calculation routine (e.g. in MATLAB) is discussed, the MOSFET model in Fig. 1 is used. The parasitic MOSFET
where the used equations are indicated. As example the capacitances are linearized by their charge equivalent value.
From the voltage dependent input, output and reverse transfer
Operating conditions & characteristics I0,off V0,off V0,on I0,on
capacitance (Coss , Ciss , Crss ) the charge equivalent capaci-
► Switching frequency: f tances are determined with
s vS1
► Turn-off: I
0,off
, V0,off iS1 Z V0
► Turn-on: I , V t 1
0,on 0,on Cν,q,eq = Cν (vds )dvds with ν = oss, iss, rss (32)
V0 0
Device selection & specification / Parameter extraction
Semiconductor device (extract from datasheet) For the considered example device the resulting capacitances
► Charge equivalent parasitic capacitances: C , C , C are
ds gs gd
► Transconductance: g (i ) → Fit with (3.43)
m ch
► Reverse recovery characteristic: Q , I , di /dt→ τ , τ , T .
rr rr d rr c m Cgs = Ciss − Crss = 1080 pF (33)
Gate drive specifications: Vg,on, Vg,off , R*g,on, R*g,off
*
including device internal gate resistance
Cds = Coss − Crss = 130 pF (34)
Estimation of parasitic capacitances: Ls, Ld Cgd = Crss = 14.5 pF (35)
Number of paralleled devices: nsemi
and the stored charge Qoss is 86.56 nC.
Switching loss calculation (for each device and each switching action) As mentioned above, the transconductance is a function of
Turn-off: Turn-on: ich .
Determine: Determine: (Interval 1b)
► Current rise time t (18)
► Transconductance g
m
ri ich =k1 (vgs − Vth )x + k2 with (36)
► Voltage reduction due to
► Charging current I >0
oss
stray inductance VLd=LdI0 /tri
s
Starting
k1 ixch
value
gm=f (I0) (37)

Ioss,new=I0;
gm (ich ) = x , (37)
Reverse recovery (Interval 2b) ich − k2
► Determine T (22)
Ioss,old=Ioss,new
∆Ioss>∆Ioss,max
1
► Reverse conducting time
The resulting constants from the datasheet shown in Fig. 7,
(10):→ Ioss,new trs (23) are found by a curve fit and for this example x = 3.80, k1 =
(37): gm=f (I0-2Ioss,new) ► Reverse current peak I (24)
∆Ioss=|Ioss,new-Ioss,old| rr 0.1319, k2 = −0.076 for the corresponding Vth = 4.5 V.
Ioss=Ioss,new Determine: (Interval 3b)
2) Body Diode Reverse Recovery Parameters: The estima-
► Transconductance g
m
tion of the diode reverse recovery losses is rather challeng-
Determine: (Interval 1a) ► Charging current I <0 ing. Often only a single measurement point is given in the
oss
► Miller voltage V (1)
∆Ioss>∆Ioss,max Starting
gm=f (I0) (37) datasheet, which usually does not correspond to the inves-
value
mil
► Voltage rise time t (13) Ioss,new=I0;
rv
► Channel current I <I
tigated operating conditions. For the considered device the
ch 0
provided values are the reverse recovery charge Qrr =192 nC,
Ioss,old=Ioss,new
Determine: (Interval 2a) (29):→ Ioss,new the reverse recovery time trr =32 ns and the reverse recovery
► Current fall time t (15) (37): gm=f (I0-2Ioss,new)
fi
► Overvoltage due to L (16) ∆Ioss=|Ioss,new-Ioss,old|
d
Ioss=Ioss,new 40
Calculate turn-off loss energy
Tj=150°C
Drain-source current, ids (A)
►E (17)
T,off Determination of: (Interval 3b)
30
► Miller voltage V (1)
mil
► Voltage fall time t (30)
rv
Tj=25°C
► Channel current I >I
ch 0
20
Tj=-55°C
Calculate turn-on loss energies
Vth=4.5V
►E (31) transistor
T,on 10
►E (28) body diode
D,off
ich=k1 ∙ (vgs-Vth)x + k2
Switching losses (for each device) 0
►P = fs ∙ (ET,on+ED,off+EToff) → Psw =nsemi ∙ (Psw,S1+Psw,S1) 0 2 4 6 8 10 12 14
sw,Si Gate-source voltage, vgs (V)
Fig. 7. Current dependency on the gate source voltage given in the datasheet
Fig. 6. Flowchart for calculating the turn-on and turn-off losses of MOSFETs of the C2M0080120D device, which is used to determine x, k1 , k2 and the
in a half-bridge. corresponding Vth .
peak current Irr = 10 A at a voltage of V0 = 800 V, a forward TABLE I

current of I0 =20 A and a current slope of didtbd = −2400 A/µs. PARAMETERS FOR THE S I C MOSFET C2M0080120D, 20 A, 600 V
Notice that in the applied model, the body diode and the
Turn-off Turn-on
parasitic capacitances are considered separately. Since Qrr
Interval 1a/b gm 1.02 S gm 3.02 S
often includes both charges, the datasheet value has to be Ioss 8.33 A tri 10.7 ns
corrected to Q?rr = Qrr − Qoss =88 nC. Ich 3.32 A VLd 37.35 V
To determine Tm , τc and τrr , which describe the diode Vmil 7.46 V
reverse recovery behaviour, first Qrf has to be estimated. trv 10.5 ns
Interval 2a/b tf i 3.5 ns trs 4.6 ns
2
Irr Irr 8.6 A
Qrf = − (38) Q?rr
2 dibd /dt Interval 3b - gm 4.1 S
- Ioss −6.06 A
The time constant τrr can be determined by integrating ibd - Ich 32.16 A
for the interval T1 < t < T2 (see Fig. 5) resulting in: - Vmil 12.16 V
Qrf - tf v 14.44 ns
τrr = (39) Losses (device internal) ET,of f 14.1 µJ ET,on 274 µJ
Irr Stored energy Eoss,S1 18.9 µJ Eoss,S1 18.9 µJ
The effective carrier life time τc can be found by numeri-
cally solving [23]
IV. M EASUREMENT R ESULTS
dibd
Irr,dat = · (τc − τrr ) 1 − e−T1 /τc . (40) The theoretical derivations of the previous sections have
dt dat
been experimentally validated. Additionally, the influence of
According to [18] the drift region transition time Tm is the temperature and the influence of the source inductance are
linked to τc and τrr by discussed.
1 1 1
= − . (41)
τrr τc Tm A. Measurement Setup
For the considered device, the diode behaviour is character- To validate the model, the switching losses of different SiC
ized by Tm = 18.6 ns, τrr = 8.6 ns and τc = 16 ns. MOSFETs have been measured with the test setup depicted
3) Estimation of the parasitic inductances: The parasitic
in Fig. 9. The designed test-circuit consists of a symmetric
inductances Ls and Ld are strongly dependent on the design of
the PCB and the arrangement of the components as well as the
internal bonding of the die. Usually the parasitic inductances Top side
Screw connector for
introduced by the loops in the commutation path as well as in

the connection of the gate drive are minimized to achieve a
ouput inductor
high performance. Therefore, the considered source inductance

values caused by the package (here TO-247) are assumed to
be approximately 4 nH ([6], [26] and [27]).
B. Example Calculation
Based on the extracted parameters, the turn-on and turn-
off losses in the half-bridge can be calculated. Additionally
the configuration of the gate drive is required, which is here
Vg = −5 V/ + 20 V and Rg = Rg,ext + Rg,int = 2.5 Ω + Current sensor MOSFET devices Input voltage
(www.izm.fraunhofer.de) vonnectors
4.6 Ω. The characteristic values of the different time intervals
are summarized in Table I. The loss energies for the intervals Bottom side
during the switching process are depicted in Fig. 8 for different
currents.
C2M0080120D / 600V
140 800
Vg,off : -5V Vg,on : 20V
120 Rg,off: 2.5Ω 700 Rg,on: 2.5Ω
Turn-on loss energy (µJ)
600
Turn-off loss energy (µJ)
100
(incl. reverse recovery)
Eoff
Ideal ZVS limit
500 Eon
80
Energy in interval 2a
400
60 Energy in interval 3b
300
40
Eoss 200
Energy in interval 2b
20 100
DC-link capacitors Voltage measurements points
Energy in interval 1a Energy in interval 1b
0 0
4 8 12 16 20 24 28 32 4 8 12 16 20 24 28 32
a) Drain current (A) b) Drain current (A) Fig. 9. Test half-bridge for the switching loss measurement consisting of a
half-bridge, the gate-drive circuit and the dc-link capacitors. The load inductor
is externally connected.
Fig. 8. Distribution of the loss energies on the different intervals during a)
the turn-off and b) the turn-on for the C2M0080120D at 600 V.
700 35
half-bridge with configurable gate-drive voltages, whereas the
device under test (DUT) is the low-side MOSFET. To evaluate
Drain-source voltage (V)
600 30
500 vds the switching losses, a double pulse test has been performed
25
Drain current (A)

and the drain-source voltage as well as the source current of
400 20
the DUT have been measured.
300 15
The drain-source voltage is measured directly at the cor-
200 10
responding MOSFETs pin with a high voltage probe (Lecroy
Eoff= 38µJ
100 5
id PPE6kV, 6 kV). The drain current is measured at the source pin
0 0 of the DUT with the high bandwidth rogowski coil presented
-100 -5 in [28] in combination with a low voltage probe (Lecroy
a) 0 10 20 30 40 50 60 70
time (ns) PP008-1). The DC-link consists of three film capacitors and
700 35
provide a total capacitance of 76 µF. In addition, ceramic
600 30
capacitors close to the half-bridge are insert to reduce the
Drain-source voltage (V)
500 Eon= 241µJ commutation inductance. The 150 µH load inductor is realized
25
Drain current (A)

with two series connected cable reels. All switching loss
400 20
id energies have been measured with the same laboratory test
300 15
setup by an integration of id and vds as shown in Fig. 10.
200 10
100 5
vds B. Switching Loss Measurements
0 0
-100 -5 The loss model was evaluated for the two SiC de-
b) 0 10 20 30 40 50 60 70
time (ns)
vices, C2M0080120D (Wolfspeed, see Fig. 11) and the
SCH2080KEC (Rohm Fig. 12) for different operating points.
Fig. 10. a) Turn-off and b) turn-on characteristic waveforms of the For both devices in the half-bridge, the turn-on loss energies
C2M0080120D. The gate voltages are Vg,on /Vg,of f =20 V/−5 V and an are more than four times higher than the turn-off loss energies.
external gate resistance of 2.5 Ω is applied. The average error ē with respect to the measurement points is
below 10%. However, the model underestimates the switching
C2M0080120D SCH2080KEC
800 1800
Vg,on : 20V Vg,on : 18V 800V
700 Rg,on: 2.5Ω 800V 1600 Rg,on: 0Ω ē=4.8%
ē=4.5% Measured
Measured 1400
600 Calculated
Calculated
1200 600V
500 600V ē=3.5%
ē=4.0% 1000
400 400V
400V 800
ē=4.3%
300 ē=4.6% 600
200
400
100 200
0 0
a) 4 8 12 16 20 24 28 32 a) 4 8 12 16 20 24 28 32
Drain current (A) Drain current (A)
140 400
Vg,off : -5V Vg,on : 0V
Rg,off: 2.5Ω 800V
120 350 Rg,off: 0Ω
Measured 800V ē=7.9%
Measured
Calculated ē=7.3%
100 300 Calculated

600V
600V ē=5.6%
80 250
ē=7.6%
400V
60 200 ē=3.9%
400V
ē=8.2%
40 150
20 50
0 0
b) 4 8 12 16 20 24 28 32 b) 4 8 12 16 20 24 28 32
Drain current (A) Drain current (A)
Fig. 11. a) Turn-on and b) turn-off switching loss energies of the Fig. 12. a) Turn-on and b) turn-off switching loss energies of the
C2M0080120D at a device temperature of 25 ◦C. The estimated Ls is 4 nH. SCH2080KEC at a device temperature of 25 ◦C. The estimated Ls is 4 nH.
The average error with respect to the measurement points is indicated by ē. The average error with respect to the measurement points is indicated by ē.
C2M0080120D SCH2080KEC C2M0080120D

1000 1800 800
Vg,on : 20V 125°C Vg,on : 18V Vg,on : 20V
900 Rg,on: 2.5Ω 1600 Rg,on: 0Ω 700 Rg,off: 2.5Ω
800 25°C 25°C measured Ls=5nH
1400

600
125°C 125°C calculated

700
calculated 1200 calculated Ls=4nH
600 500
1000
500 25°C 400
800 Ls=2nH
400 300
600
300
Temperature increase 200
200 400
100 200 100
0 0 0
a) 4 8 12 16 20 24 28 32 c) 4 8 12 16 20 24 28 32 a) 4 8 12 16 20 24 28 32
Drain current (A) Drain current (A) Drain current (A)
140 400 140

Vg,off : -5V Vg,off : 0V Vg,off : -5V
Rg,off: 2.5Ω Rg,off: 0Ω Rg,off: 2.5Ω Ls=5nH
120 350 120
25°C 25°C measured
calculated

100 125°C 300 125°C 100

calculated calculated Ls=4nH
80 250 80
60 200 60
Ls=2nH
40 150 40
Temperature increase
20 50 20
0 0 0
b) 4 8 12 16 20 24 28 32 d) 4 8 12 16 20 24 28 32 b) 4 8 12 16 20 24 28 32
Drain current (A) Drain current (A) Drain current (A)
Fig. 13. Temperature dependency of the switching losses at V0 =800 V: C2M0080120D a) turn-on Fig. 14. Influence of the parasitic inductance
and b) turn-off, SCH2080KEC c) turn-on and d) turn-off. on the switching losses at V0 =800 V for the
C2M0080120D device during a) the turn-on and
b) the turn-off.
losses during the turn-off at low currents where the estimation V. C ONCLUSION
error is above 20%. This mainly results from the non-ideal
recharging process of the parasitic capacitances [20]–[22]. In In this paper, a simple model to estimate the switching
the turn-off loss measurements it also can been seen that losses of MOSFETs in a half-bridge based on datasheet pa-
the loss energies for high currents are increasing less than rameters is presented and validated by measurements. During
the calculated loss energies. The reason is that the remaining the switching transient, the MOSFET is modelled by its
current at the beginning of interval 2a (see Fig. 2, section II) charge equivalent parasitic capacitances and the stored charge
is a linearized value in the model and that the current value is directly linked to the energy in the parasitic capacitances
at this time instant strongly depends on the exact recharging of the MOSFETs in a half-bridge. This allows the accurate
process of the parasitic capacitances, what is neglected in this calculation of the voltage fall and rise times and furthermore
simplified approach and needs further investigations. enables a simple estimation of the device internal loss energies
Furthermore, the temperature dependency of the switching due to the recharging process.
losses for both devices (see Fig. 13) differs a lot. For the Moreover, the model takes the reverse recovery of the body
C2M0080120D especially the turn-on losses strongly increase, diode as well as the effect of the source inductance into ac-
while for the SCH2080KEC the switching losses are nearly count. During turn-off, the charge of the parasitic capacitances
temperature independent. The increased losses mainly result reduces the MOSFET current/switching loss energies and
from the increased reverse recovery charge, whereas this effect during turn-on the current in the device and accordingly the
is mitigated for the SCH2080KEC, which includes an addi- loss energy are increased. As a consequence for the considered
tional antiparallel schottky diode. However, the information to devices the turn-on loss energies are more than four times
accurately model the temperature dependency is often limited higher than the turn-off loss energies.
or missing in datasheets, why this effect is not included in the In this paper also, an analytical expression to determine the
proposed model. ideal ZVS current range, where a nearly lossless turn-off of
Finally, the value of the source inductance must be defined. the MOSFET devices can be achieved, is presented.
In [26] and [27] the value has been estimated to be in the range Since the model relies on datasheet parameters only, limi-
of 2 nH to 5 nH for the TO-247 housing. As can be seen in tations of the model are observed due to the available infor-
Fig. 14, the impact of the source inductance on the switching mation about the device as well as the knowledge about the
losses is quite significant since it counteracts the gate-voltage. investigated half-bridge layout. This especially includes the
As a consequence, the commutation times increase and more temperature dependencies and the diode characteristics.
losses are generated. The MOSFET body diode is assumed to have a similar
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Analytical Switching Loss Modeling Based On Datasheet Parameters For Mosfets in A Half-Bridge

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Analytical Switching Loss Modeling Based On Datasheet Parameters For Mosfets in A Half-Bridge

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This article has been accepted for publication in a future issue of this journal, but has not been

Analytical Switching Loss Modelling based on

The transconductance is a function of the current through

ibd gate characteristic of MOSFET S1 . Thus, T1 can be found by

gm=f (I0) (37)

peak current Irr = 10 A at a voltage of V0 = 800 V, a forward TABLE I

introduced by the loops in the commutation path as well as in

high performance. Therefore, the considered source inductance

Drain current (A)

Drain current (A)

100 300 Calculated

C2M0080120D SCH2080KEC C2M0080120D

Turn-on loss energy (µJ)

Turn-on loss energy (µJ)

125°C 125°C calculated

140 400 140

Turn-off loss energy (µJ)

100 125°C 300 125°C 100

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