04 MachFlipFlop - Edit

BÀI THỰC HÀNH SỐ 4
MẠCH CHỐT VÀ MẠCH FLIP FLOP
4.1. Mục tiêu

Sau khi hoàn thành bài thí nghiệm này, SV có thể:
Xây dựng và kiểm tra chốt D có gọng từ bốn cổng NAND và cổng
NOT;
Kiểm tra flip-flop D và khảo sát một số mạch ứng dụng cho cả chốt
và flipflop;
Kiểm tra các cấu hình khác nhau cho một J-K flip-flop, bao gồm cả
không đồng bộ và đồng bộ các yếu tố đầu vào;
Quan sát các đặc điểm phân chia tần số trong chế độ chuyển đổi;
Đo độ trễ lan truyền của flip-flop J-K.
4.2. Câu hỏi chuẩn bị
1/ Mạch chốt RS (NAND): kí hiệu; bảng trạng thái; phương trình.
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2/ Mạch chốt RS (NOR): kí hiệu; bảng trạng thái; phương trình.

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3/ Mạch chốt D : kí hiệu; bảng trạng thái; phương trình.
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4/ Mạch flip-flop RS : kí hiệu; bảng trạng thái; phương trình.

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5/ Mạch flip-flop D : kí hiệu; bảng trạng thái; phương trình.

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6/ Mạch flip-flop J-K : kí hiệu; bảng trạng thái; phương trình.

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7/ Mạch flip-flop T : kí hiệu; bảng trạng thái; phương trình.
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8/ Mạch flip-flop D được tạo từ flip-flop J-K.

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4.3. Trang thiết bị thực hành
IC 7400; IC 7474; IC 7493; IC 7486; IC 7476; IC 74139; IC 7408;
LED; DIP; R 330 Ω; R 1 kΩ; Test board.
KIT thực tập Kỹ thuật số.
Dao động ký; VOM.
Máy tính có phần mềm Proteus.
4.4. Tóm tắt lý thuyết
Thí nghiệm này giới thiệu hai loại flip-flop cơ bản trong mạch tuần
tự.
4.4.1. IC Flip Flop 74LS74
Sơ đồ chân – ký hiệu và bảng chức năng của IC flip-flop D.
Hình 4.1: Sơ đồ chân-ký hiệu và bảng chức năng IC 74LS74.

4.4.2. IC Flip Flop 74LS76
Sơ đồ chân – ký hiệu và bảng chức năng của IC flip-flop J-K.
Hình 4.2: Sơ đồ chân - ký hiệu và bảng chức năng IC 74LS76.
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4.5. Các bước thực tập
4.5.1. Mạch flip-flop D.
Xây dựng mạch thử nghiệm trong hình 4.3. Kết nối CLK qua mạch
trễ. Mục đích của trễ là cho phép thời gian thiết lập cho đầu vào D.
Hình 4.3: Mạch thiết lập thời gian trễ cho flip-flop D.
Hình 4.4: Mạch ứng dụng của một flip-flop D..
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4.5.2. Mạch flip-flop J-K
J-K flip-flop là loại linh hoạt nhất trong các loại flip-flop. Tất cả các
ứng dụng cho mạch tuần tự có thể được thực hiện với flip-flop D hoặc
flip-flop J-K.
Hình 4.5: Mạch kiểm tra flip-flop J-K không có CLK.
Hình 4.6: Mạch Mạch kiểm tra flip-flop J-K có CLK.
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Hình 4.7: Mạch ứng dụng flip-flop J-K.
Hình 4.8: Mạch ứng dụng của flip-flop J-K làm mạch đếm.
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4.6. Báo cáo thực tập
4.6.1. Giải thích mạch trong hình 4.3
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4.7. Bài tập

1. Hãy vẽ kí hiệu và bảng trạng thái hoạt động FF D của IC 74LS175.
2. Hãy vẽ kí hiệu và bảng trạng thái hoạt động FF JK của IC 74LS112.
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3. Hãy vẽ mạch ứng dụng chống dội nút nhấn dùng mạch chốt.
21

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BÀI THỰC HÀNH SỐ 4

MẠCH CHỐT VÀ MẠCH FLIP FLOP

4.1. Mục tiêu

2/ Mạch chốt RS (NOR): kí hiệu; bảng trạng thái; phương trình.

4/ Mạch flip-flop RS : kí hiệu; bảng trạng thái; phương trình.

5/ Mạch flip-flop D : kí hiệu; bảng trạng thái; phương trình.

6/ Mạch flip-flop J-K : kí hiệu; bảng trạng thái; phương trình.

7/ Mạch flip-flop T : kí hiệu; bảng trạng thái; phương trình.

8/ Mạch flip-flop D được tạo từ flip-flop J-K.

Hình 4.1: Sơ đồ chân-ký hiệu và bảng chức năng IC 74LS74.

Hình 4.2: Sơ đồ chân - ký hiệu và bảng chức năng IC 74LS76.

Hình 4.4: Mạch ứng dụng của một flip-flop D..

Hình 4.5: Mạch kiểm tra flip-flop J-K không có CLK.

Hình 4.6: Mạch Mạch kiểm tra flip-flop J-K có CLK.

4.6.2. Giải thích mạch trong hình 4.4

4.6.3. Giải thích mạch trong hình 4.5

4.6.4. Giải thích mạch trong hình 4.6

4.6.5. Giải thích mạch trong hình 4.7

4.6.6. Giải thích mạch trong hình 4.8

4.7. Bài tập

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