TL28L92 (80xxx mode)

8
BUS BUFFER
CHANNEL B
(AS ABOVE)
D0 to D7
OPERATION
CONTROL
ADDRESS
DECODE
R/W CONTROL
RESET
I/M
open or connect
to V
CC
for 80xxx
A0 to A3
CEN
WRN
RDN
4
INTERRUPT
CONTROL
IMR
ISR
GP
TIMING
BAUD RATE
GENERATOR
CLOCK
SELECTORS
COUNTER/
TIMER
XTAL
OSCILLATOR
CSRA
CSRB
ACR
CTL
CTU
INTRN
X2
X1/CLK
I
N
T
E
R
N
A
L

D
A
T
A

B
U
S
CHANNEL A
16-BYTE
TRANSMIT FIFO
TRANSMIT
SHIFT REGISTER
16-BYTE
RECEIVE FIFO
WATCHDOG
TIMER
TxDA
RxDA
RxDB
RECEIVE
SHIFT REGISTER
MRA0, 1, 2
CRA
SRA
INPUT PORT
CHANGE-OF-
STATE
DETECTORS (4)
ACR
IPCR
IP0 to IP6
7
TxDB
OUTPUT PORT
FUNCTION
SELECT LOGIC
OPR
OPCR
OP0 to OP7
8
t
i
m
i
n
g
c
o
n
t
r
o
l









TL28L92 (68xxx mode)
8
BUS BUFFER
CHANNEL B
(AS ABOVE)
D0 to D7
OPERATION
CONTROL
ADDRESS
DECODE
R/W CONTROL
RESETN
I/M
ground for
68xxx mode
A0 to A3
CEN
IACKN
R/WN
4
INTERRUPT
CONTROL
IMR
ISR
GP
TIMING
BAUD RATE
GENERATOR
CLOCK
SELECTORS
COUNTER/
TIMER
XTAL
OSCILLATOR
CSRA
CSRB
ACR
CTL
CTU
INTRN
X2
X1/CLK
I
N
T
E
R
N
A
L

D
A
T
A

B
U
S
CHANNEL A
16-BYTE
TRANSMIT FIFO
TRANSMIT
SHIFT REGISTER
16-BYTE
RECEIVE FIFO
WATCHDOG
TIMER
TxDA
RxDA
RxDB
RECEIVE
SHIFT REGISTER
MRA0, 1, 2, 3
CRA
SRA
INPUT PORT
CHANGE-OF-
STATE
DETECTORS (4)
ACR
IPCR
IP0 to IP5
6
TxDB
OUTPUT PORT
FUNCTION
SELECT LOGIC
OPR
OPCR
OP0 to OP7
8
t
i
m
i
n
g
c
o
n
t
r
o
l
DACKN









TL28L92FR
(80xxxmode)
A CEN
IP RESET
WR X2
RD X1/CLK
RxD RxDA
TxD TxDA
OP OP0
OP OP2
OP OP4
OP OP6
I/ N.C.
D
A
2
D
I
P
1
D
A
1
D
I
P
3
G
N
A
0
G
N
V
C
C
I
N
T
R
V
C
C
D
I
P
4
D
I
P
5
D
I
P
6
D
I
P
2
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
TL28L92FR
(68xxxmode)
A CEN
IP RESETN
R/W X2
DACK X1/CLK
RxD RxDA
TxD TxDA
OP OP0
OP OP2
OP OP4
OP OP6
I/ N.C.
D
A
2
D
I
P
1
D
A
1
D
I
P
3
G
N
A
0
G
N
V
C
C
I
N
T
R
V
C
C
D
I
P
4
D
I
P
5
D
I
A
C
K
N
D
I
P
2
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4




TL28L92RGZ
(80xxxmode)
N.C.
OP5
OP7
OP6
OP OP4
OP OP2
TxD OP0
I/ TxDA
N.C RxDA
RxD X1/CLK
RD X2
WR RESET
IP CEN
A N.C.
N
.
C
.
D
1
D
3
D
5
D
7
G
N
D
I
N
T
R
N
D
6
D
4
D
2
D
0
N
.
C
.
A
2
I
P
1
A
1
I
P
3
A
0
N
.
C
.
V
C
C
I
P
4
I
P
5
I
P
6
I
P
2
N
.
C
.
12
11
10
9
8
7
6
5
4
3
2
1
25
26
27
28
29
30
31
32
33
34
35
36
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
terminal1
indexarea
TL28L92RGZ
(68xxxmode)
N.C.
OP5
OP7
OP6
OP OP4
OP OP2
TxD OP0
I/ TxDA
N.C RxDA
RxD X1/CLK
DACK X2
R/W RESETN
IP CEN
A N.C.
N
.
C
.
D
1
D
3
D
5
D
7
G
N
D
I
N
T
R
N
D
6
D
4
D
2
D
0
N
.
C
.
A
2
I
P
1
A
1
I
P
3
A
0
N
.
C
.
V
C
C
I
P
4
I
P
5
I
A
C
K
N
I
P
2
N
.
C
.
12
11
10
9
8
7
6
5
4
3
2
1
25
26
27
28
29
30
31
32
33
34
35
36
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
terminal1
indexarea

counter/timer input clock
2 16 (desired baud rate) X X
n =

counter/timerclockfrequency
n
216(desiredbaudrate)
=

0
40 80
001aae302
40
60
0
30pF 12pF
230pF 125pF 100pF
(1)
(2)
t
(ns)
DD
20
120
160 200 240
C (pF)
L
(1)V =3.3V; Tamb=25 C
(2)
CC

V =5.0V; Tamb=25 C
Buscycletimes:
80xxxmode:t +t =70nsforV =5vor40nsforV =3.3V+riseandfalltimeofcontrolsignals.
68XXXmode:t +t +1cycleoftheX1clockfor=70nsforV =5V+riseandfalltimeofcontrolsignals.
CC
DD RWD CC CC
CSC DAT CC

A0 to A3
CEN
RDN
D0 to D7
(read)
WDN
D0 to D7
(write)
valid
valid not valid float float
t
AS
t
CS
t
CS
t
AH
t
RW
t
DD
t
DF
t
RWD
t
RWD
t
DH
t
DS












a.Input pins.
b.Output pins.
t
PS
t
PH
RDN
IP0 to IP6
WRN
OP0 to OP6 old data new data
t
PD
The test for open-drain outputs is intended to guarantee switching of the output transistor.
Measurement of this response is referenced from the midpoint of the switching signal, V
M
, to a
point 0.2V above V
OL
. This point represents noise margin that assures true switching has
occurred. Beyond this level, the effects of external circuitry and test environment are
pronounced and can greatly affect the resultant measurement.
(1)IRQN or OP3toOP7 when used as interrupt outputs.
WRN
RDN
V
M
interrupt output
(1)
V
OL
+ 0.5 V
V
OL
t
IR
V
M
V
OL
+ 0.5 V
V
OL
interrupt output
(1)
t
IR








X1/CLK
C/T clock
RxC
TxC
t
t
t
t
CLK
CTC
RX
TX
t
t
t
t
CLK
CTC
RX
TX
CLK
V
CC
Resistorrequired
for TTL input
470 W
X1
X2
(mustbeleftopen)
3pF
parasiticcapacitance
X1
C1
C2
3pF
parasiticcapacitance
X2
SC28L92
2pF
4pF
50k
to
100k
W
W
toUART circuit
001aae314
C1=C2~24pFforC =13.5pF.Fortheoscillatorfeedbackloop,thecapacitorsC1andC2areinseries.
C1andC2shouldbechosenaccordingtothecrystalmanufacturersspecification.
C1andC2valueswillincludeanyparasiticcapacitanceofthewiringandX1,X2pins.
Packagecapacitanceapproximately4pF.
L












(1) Timing shown for MR1[7] = 1.
(2) Shown for OPCR[4] = 1 and MR[6] = 0.
D1 D2 D8 D9 D10 D11 D12 D13
RDN
D1 D2 D3 D10
OPR[0] = 1
RTS
(1)
(OP0)
OVERRUN
(SR) reset by command
status data status data
D11 will be lost
due to overrun
status data status data
RxRDY/
FFULL
(OP5)
(2)
FFULL
(CR)
RxRDY
(SR)
receiver
enabled
D12, D13 will be lost
due to receiver disable
RxD
status data
ADD#2
status data
TxD ADD#1
MR1[4:3] = 11
MR1[2] = 1
1
bit 9
D0 0
bit 9
ADD#2 1
ADD#1
MR1[2] = 0
D0
MR1[2] = 1
ADD#2
ADD#11 D0 0 ADD#2 1
bit 9
0 0
bit 9
MR1[4:3] = 11
D0
RDN/WRN
ADD#1
RxRDY
(SR)
receiver
enabled
peripheral station:
bit 9 bit 9 bit 9
RxD
WRN
TxRDY
(SR)
transmitter
enabled
bit 9
master station:







001aae320
INTRN
DACKN
125pF
+5 V
I=2.4mA
D0toD7
TxDA/TxDB
OP0toOP7
125pF
I=2.4mA V
OL
returnto V
CC
fora0level
I=400 A V returntoV fora1level
OH SS





PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
TL28L92FR ACTIVE QFP FR 44 96 TBD CU SN Level-3-220C-168 HR
TL28L92FRR PREVIEW QFP FR 44 TBD Call TI Call TI
TL28L92IFR ACTIVE QFP FR 44 96 TBD CU SN Level-3-220C-168 HR
TL28L92IFRR PREVIEW QFP FR 44 TBD Call TI Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Apr-2009
Addendum-Page 1