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Az5a75 01F
Az5a75 01F
Applications
Mobile phones
Handheld portable applications 1
Computer interfaces protection
Microprocessors protection
Serial and parallel ports protection
Control signal lines protection
Power lines on PCB protection
Latch-up protection 2
Description
DFN0603P2Y (Bottom View)
AZ5A75-01F is a design which includes one (0.6mm x 0.3mm x 0.3mm)
bi-directional ESD rated clamping cell to protect
one power line, or one control line, or one
low-speed data line in an electronic system. The
AZ5A75-01F has been specifically designed to
protect sensitive components which are
connected to power and control lines from
over-voltage damage and latch-up caused by
Electrostatic Discharging (ESD), Electrical Fast
Transients (EFT), and Cable Discharge Event
(CDE).
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Reverse Stand-Off
VRWM T=25 oC. -5 5 V
Voltage
Reverse Leakage
ILeak VRWM = ±5V, T=25 oC. 100 nA
Current
Reverse Breakdown
VBV IBV = 1mA, T=25 oC. 5.6 9 V
Voltage
Channel Input
CIN VR = 0V, f = 1MHz, T=25 oC. 5.5 7 pF
Capacitance
Note 1: ESD Clamping Voltage was measured by Transmission Line Pulsing (TLP) System.
TLP conditions: Z0= 50Ω, tp= 100ns, tr= 1ns.
Typical Characteristics
7 Pin 1 to Pin 2
2
f = 1MHz, T = 25℃
Input Capacitance (pF)
0
-5 -4 -3 -2 -1 0 1 2 3 4 5
Input Voltage (V)
Application Information
The AZ5A75-01F is designed to protect one line In order to obtain enough suppression of ESD
against system ESD/EFT/Cable Discharge induced transient, a good circuit board is critical.
pulses by clamping it to an acceptable reference. Thus, the following guidelines are recommended:
It provides bi-directional protection. Minimize the path length between the
protected lines and the AZ5A75-01F.
The usage of the AZ5A75-01F is shown in Fig. 1. Place the AZ5A75-01F near the input
Protected line, such as data line, control line, or terminals or connectors to restrict transient
power line, is connected at pin 1. The pin 2 is coupling.
connected to a ground plane on the board. In The ESD current return path to ground
order to minimize parasitic inductance in the should be kept as short as possible.
board traces, all path lengths connected to the Use ground planes whenever possible.
pins of AZ5A75-01F should be kept as short as NEVER route critical signals near board
possible. edges and near the lines which the ESD
transient easily injects to.
AZ5A75-01F
AZ5A75-01F
Fig. 1
Fig. 2 shows another simplified example of using low-speed data line, and power line from ESD
AZ5A75-01F to protect the control line, transient stress.
AZ5A75-01F
AZ5A75-01F
AZ5A75-01F
Fig. 2
E
0.65
(Unit: mm)
TOP VIEW
Notes:
This LAND LAYOUT is for reference
purposes only. Please consult your
A
manufacturing partners to ensure your
A1 company’s PCB design guidelines are met.
SIDE VIEW
D1 D2
45o MARKING CODE
0.05
0.05
E1 E2
F
BOTTOM VIEW
K = Device Code
Millimeters
SYMBOL
MIN. NOM. MAX.
Part Number Marking Code
D 0.55 0.60 0.65
E 0.25 0.30 0.35
AZ5A75-01F.R7G
A 0.28 0.30 0.32 K
(Green Part)
A1 0.00 0.02 0.05
D1 0.13 0.18 0.23 Note. Green means Pb-free, RoHS, and
D2 0.14 0.19 0.24 Halogen free compliant.
E1/E2 0.20 0.25 0.30
F 0.35
Ordering Information
PN# Material Type Reel size MOQ MOQ/internal box MOQ/carton
AZ5A75-01F.R7G Green T/R 7 inch 12,000/reel 4 reels= 48,000/box 6 boxes =288,000/carton
Revision History
Revision Modification Description
Revision 2017/03/24 Preliminary Release.
Revision 2018/03/19 Formal Release.