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CSA Final with answers
7CG0BL
https://quizlet.com/_cz2owq
2 A5B8:
2. Controls the operation of the computer and performs its data
processing functions:
o Main memory
• CPU
o I/O
o CPU
o System interconnection
3. What provides storage internal to the CPU?
o Registers
o Arithmetic and logic unit • Registers
o CPU interconnection
o Control unit
4. ENIAC stands for:
o Electronical Numerical Integrator And Computer
o Electronic Numerical Integration Analogue Computer • Electronic Numerical Integrator And Computer
o Electronic Numerical Integrator And Computer
o Electronic Numerical Interaction And Calcuation
6. How the central termination point for data channels, the CPU,
and memory is called. It schedules access to the memory from
the CPU and data channels, allowing these devices to act inde-
pendently.
o Transistor • Multiplexor
o Multiplexor
o Integrated circuit
o Resistors
o Capacitors
. Expand the abbreviation VLSI
o Very-large-scale integration
o Very-little-scale integration • Very-large-scale integration
o Very-large-scale interactions
o Very-large-scale integrator
8. Which technique allows to processor simultaneously work on
multiple instructions?
o Branch prediction
• Pipelining
o Data flow analysis
o Pipelining
o Speculative execution
9. Using this technique processor looks ahead in the instruction
code fetched from memory and predicts which groups of instruc-
tions are likely to be processed next.
o Branch prediction • Branch prediction
o Pipelining
10. Which technique helps to processor investigates which in-
structions are dependent on each other's results, or data, to create
an optimized schedule of instructions
o Branch prediction • Data flow analysis
o Pipelining
11. This technique enables the processor to keep its execution
engines as busy as possible by executing instructions that are
likely to be needed.
o Branch prediction • Speculative execution
o Pipelining
12. The world's first general-purpose microprocessor. It was used
in the first personal computer, the Altair.
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2 A5B8:
o 8070
o 8080
• 8080
o 8086
o 8090
13. Which of the following laws deals with the potential speedup
of a program using multiple processors compared to a single
processor.
o Moor's Law • Amdahl's law
o Little's Law
o Murphy's law
o Amdahl's law
15. The processor responds by suspending operation of the cur-
rent program, branching off to a program to service that partic-
ular I/O device, known as _________________, and resuming
the original execution after the device is serviced. Which of the
following will be the missing word: • interrupt handler
o interrupt handler
o interrupt cycle
o disabled interrupt
o interrupt request
16. What is the data line?
o provide a path for moving data among system modules
o is used to designate the source or destination of the data on the
data bus • provide a path for moving data among system modules
o is used to control the access to and the use of the data and
address lines
o indicates that a module needs to gain control of the bus
17. What is used to manage the access to and the use of the data
and address lines?
o address bus
o control lines • control lines
o memory write
o bus grant
o address lines
18. Bus lines can be separated into two generic types:
o Dedicated
o Centralized
o Distributed • Dedicated / • Multiplexed
o Multiplexed
o Synchronous
o Asynchronous
19. PCI stands for:
o Power Control Interface
o Peripheral component interconnect • Peripheral component interconnect
o Property Casualty Insurers
o Programmable Communications Interface
20. The methods of accessing units of data:
o Sequential access
o Pseudo access
o Direct access • Sequential access / • Direct access / • Associative access / •
o Indirect access Random access
o Single access
o Random access
o Associative access
22. What kind of memory type stores data using virtual addresses:
o Logical
• Virtual
o Virtual
o Peripheral
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o Main
o Buffer
23. Amdahl's law:
o Speed up= 1/(1 + f ) * f/N
o Speed up= 1/(1 - f ) * f/N
• Speed up= 1/(1 - f ) + f/N
o Speed up= 1/(1 - f ) - f/N
o Speed up= 1/(1 - f ) + f/N
o Speed up= 1/(1 + f ) + f/N
24. AMAT stands for:
o Average memory access time
o Automatic Message Accounting Transmitter • Average memory access time
o Asymptotic Mean Acquisition Time
o Absolute memory access time
25. _____________ is a special purpose system that is used to
perform one or few dedicated functions.
o Distributed systems
o Embedded systems • Embedded systems
o Ultra-Large-Scale Systems
o Centralized systems
o Ubiquitous systems
28. How many generations semiconductor memory has been
13
through, since 1970? (please write number)
29. MIC stands for:
o mini integrated core
o many integrated core
• many integrated core
o main integrated core
o many interaction core
o main interaction core
30. Clock Frequency of SDRAM is equal to:
o 200
o 600
• 166
o 300
o 166
o 156
31. An instruction pipeline increases the performance of a proces-
sor by overlapping the processing of several different instructions.
How many stages it is consist of:
o6
•5
o3
o5
o7
o4
33. _____________ is the amount of time it takes the program to
perform in seconds
o Elapsed time
o Overall time • Execution time
o Estimate time
o Execution time
o Process time
34. How many number systems are exist?
o4
o3
•4
o2
o1
o5
35. Basic memory elements hold only two states: Zero / One
o True • True
o False
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2 A5B8:
36. Which of the following is the right result for this operation:
11001+110001=
o 10101010
o 10101110 • 01001010
o 01001010
o 01100110
o 10001010
37. Convert decimal 230 to the binary:
o 011000110
o 011100110 • 011100110
o 101100110
o 011100110
38. Convert binary 1100111 to decimal:
o 103
o 100
• 103
o 95
o 130
o 110
39. A single, self-contained transistor is called ________.
o integrated circuit
o microchip
• discrete component
o discrete component
o single transistor
o small-scale integration
40. GPU stands for:
o graphical processing unit
o graphical performing units • graphics processing units
o graphics processing units
o graphics processing utility
41. What measures the ability of a computer to complete a single
task?
o Clock rate
o Speed metric • Speed metric
o Clock speed
o Clock cycle
o Execution speed
42. Convert hexadecimal value: DAD to decimal:
o 3500
o 3501
• 3501
o 4501
o 4500
o 3503
43. Convert decimal value: 877 to hexadecimal:
o 36D
o 38A
• 36D
o 36B
o 38C
o 36A
44. How we call the thing that is connects major computer com-
ponents (processor, memory, I/O)?
o System connector
• System bus
o System controllers
o System bus
o System interconnector
46. Which of the following is the result of the binary multiplication:
100010*100101=
o 11011101010 • 10011101010
o 10111101010
o 10010001010
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o 10010101010
o 10011101010
47. Convert the binary value: 111011 to decimal
o 59
o 58
• 59
o 56
o 60
o 69
48. DRAM stands for:
o Direct random access memory
o Dynamic random accessible memory
• Dynamic random access memory
o Dynamical random access memory
o Dynamic random access memory
o Discrete random access memory
49. How is called the permanent physical defect when the memory
cell or cells affected cannot reliably store data but become stuck
at 0 or 1 or switch erratically between 0 and 1?
o Soft error
• Hard failure
o Hard error
o Hard failure
o Soft failure
o Epic failure
50. How is called a random, nondestructive event that alters the
contents of one or more memory cells without damaging the
memory?
o Soft error
• Soft error
o Hard error
o Hard failure
o Soft failure
o Epic failure
51. Choose the feature(s) of first generation computer architecture
o Magnetic core memory
o Semiconductor memory
• Vacuum tubes / • Assembly language
o Machine code
o Vacuum tubes
o Assembly language
52. Choose the feature(s) of third generation computer architec-
ture
o Object-Oriented programming
o Floating point arithmetic • Timesharing / • Use of cache memory
o Graphics
o Timesharing
o Use of cache memory
53. Choose the feature(s) of second generation computer archi-
tecture
o High level languages
o Transistors • High level languages / • Transistors
o 2 Kb memory, 10 KIPS
o 2 Mb memory, 5 MIPS
o Different types of supported instructions
54. Choose the feature(s) of fourth generation computer architec-
ture
o Wide spread use of data communications • Object-Oriented programming
o Use of cache memory • Wide spread use of data communications
o Smallest in size • Smallest in size
o Use of drum memory or magnetic core memory
o Object-Oriented programming
55. How many generations of computer architecture are there?
o4
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2 A5B8:
o3
o2
•4
o1
o5
56. Choose the years of the first generation computer architecture
o 1958-1964
o 1964-1974
• 1945-1958
o 1974-present
o 1945-1964
o 1945-1958
57. Choose the years of the second generation computer archi-
tecture
o 1945-1958
o 1964-1974 • 1958-1964
o 1974-present
o 1945-1964
o 1958-1964
58. In 1976 Apple II computer model was released
o True • False
o False
59. IBM System/360 Model 91 was introduced in 1966
o True • True
o False
60. Choose two types of models for a computing machine
o Harvard architecture
o Von Neumann architecture • Harvard architecture / • Von Neumann architecture
o Oxford architecture
o Stanford architecture
61. How many number systems are there?
o1
o2 •4
o3
o4
62. How a binary digit is called?
o byte
o digit • bit
o kilobyte
o bit
63. Four bits make octal digit
o True • False
o False
64. Three bits make hexadecimal digit
o True • False
o False
65. Octal and hexadecimal numbers are hard on use and conver-
sion
• False
o True
o False
66. Which digits are used in octal number system?
o 0-7
o 0 and 1 • 0-7
o 0-9
o All digits
67. What does CPI stand for?
o Cycles Per Instruction
o Clocks Per Instruction • Cycles Per Instruction
o Cycles Per Interface
o Clocks Per Interface
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2 A5B8:
68. What is time elapsed to program execution?
o CPU Time
o User time + OS Time • CPU Time + I/O waiting & Other programs
o I/O waiting & Other programs
o CPU Time + I/O waiting & Other programs
69. The execution time of a program clearly depends on the
number of instructions
• False
o True
o False
70. The more clock rate of processor, the faster is processor
o True • False
o False
71. CPU Time = I * CPI / R. Which parameter requires special
profiling software?
o Cycles Per instruction
• Numbers of instructions
o Clock Rate
o Numbers of instructions
o Execution time
72. Select the correct interpretation(s) of Amdahl's Law
o is used to compare computers' performance
• is used to find the maximum expected improvement
o is used calculate the execution time of a program
• it means that it is the algorithm that decides the speedup not the
o is used to find the maximum expected improvement
number of processors
o it means that it is the algorithm that decides the speedup not the
number of processors
73. Into how many parts a program (or algorithm) which can be
parallelized can be split up?
o3
•2
o4
o5
o2
74. The time interval is called a clock rate
o True • False
o False
75. What does LRU stand for?
o Least Right Used
o Last Recently User • Least Recently Used
o Last Recently Used
o Least Recently Used
76. Static RAM has a reduced power consumption, and a large
storage capacity
• False
o True
o False
77. How a memory unit accessed by contents is called?
o Associative Memory
o Content Addressable Memory • Associative Memory
o Auxiliary Memory • Content Addressable Memory
o Cache Memory
o Virtual Memory
78. Choose the access method(s)
o Parallel Access
• Random Access
o Indirect Access
• Direct Access
o Random Access
• Sequential Access
o Direct Access
o Sequential Access
79. ROM is the place in a computer where the operating system,
application programs, and data in current use are kept.
• False
o True
o False
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2 A5B8:
80. In which cache memory mapping technique any block from
main memory can be placed anywhere in the cache?
o Associative Mapping • Associative Mapping
o Set Associative Mapping
o Direct Mapping
81. In LRU replacement algorithm, the block that is in the cache
longest is replaced
• False
o True
o False
82. In which cache memory mapping technique any memory block
is mapped to exactly one block in the cache?
o Direct Mapping • Direct Mapping
o Set Associative Mapping
o Associative Mapping
83. In which cache memory mapping technique any memory block
mapped to subset of cache locations?
o Set Associative Mapping • Set Associative Mapping
o Direct Mapping
o Associative Mapping
84. Which type of memory accessed via the input/output chan-
nels?
o Main Memory
• Auxiliary Memory
o Cache Memory
• Secondary Memory
o Virtual Memory
o Auxiliary Memory
o Secondary Memory
85. Which type of memory stores frequently used data?
o Main Memory
o Virtual Memory
• Cache Memory
o Auxiliary Memory
o Secondary Memory
o Cache Memory
86. Choose the right formula for AMAT
o AMAT = Hit time + Miss rate + Miss penalty
o AMAT = Hit time * Miss rate + Miss penalty • AMAT = Hit time + Miss rate * Miss penalty
o AMAT = Hit time * Miss rate * Miss penalty
o AMAT = Hit time + Miss rate * Miss penalty
87. Choose the definition for compulsory misses
o Occurs if the cache cannot contain all the blocks needed during
execution of a program • The very first access to a block cannot be in the cache
o Occurs if the block placement strategy is not fully associative
o The very first access to a block cannot be in the cache
88. Choose the definition for capacity misses
o Occurs if the cache cannot contain all the blocks needed during
• Occurs if the cache cannot contain all the blocks needed during
execution of a program
89. Choose the definition for conflict misses
o Occurs if the cache cannot contain all the blocks needed during • Occurs if the block placement strategy is not fully associative
90. Select cache optimizations to reduce miss penalty
o Multilevel Caches
• Multilevel Caches
o Giving Reads Priority over Writes
• Giving Reads Priority over Writes
o Way Prediction
o Higher associativity
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2 A5B8:
91. Select cache optimizations to increase the Cache Bandwidth
o Nonblocking Caches
• Nonblocking Caches
o Multibanked Caches
• Multibanked Caches
o Pipelined Cache Access
• Pipelined Cache Access
o Multilevel Caches
o Small and Simple First-Level Caches
92. In virtual memory, memory can be used efficiently because a
section of program always loaded
• False
o True
o False
93. The advantage of virtual memory is that it takes less time to
switch between applications because of additional memory
• False
o True
o False
94. Choose basic cache optimizations
o Compiler-Controlled Prefetching
o Nonblocking Caches • Multilevel Caches
o Small and Simple First-Level Caches • Avoiding Address Translation during Cache Indexing
o Multilevel Caches
o Avoiding Address Translation during Cache Indexing
95. Choose advanced cache optimizations
o Giving Reads Priority over Writes
• Hardware Prefetching of Instructions and Data
o Larger Cache Size
• Merging Write Buffer
o Hardware Prefetching of Instructions and Data
• Critical Word First and Early Restart
o Merging Write Buffer
o Critical Word First and Early Restart
96. Select cache optimizations to reduce hit time (both basic and
advanced)
o Avoiding Address Translation during Cache Indexing • Avoiding Address Translation during Cache Indexing
o Small and Simple First-Level Caches • Small and Simple First-Level Caches
o Way Prediction • Way Prediction
o Compiler Optimizations
o Compiler-Controlled Prefetching
97. Physical address used by program, and which OS must trans-
late into virtual address
• False
o True
o False
98. Process of instruction execution is divided into two or more
steps, called
o pipelining
• pipe stages
o pipe stages
• pipe segments
o pipe segments
o instruction execution
o pipeline hazard
99. Pipelining can only be implemented on hardware
o True • False
o False
100. Choose hazard for the following definition: different instruc-
tions in different stages (or the same stage) conflicting for the
same resource
• Structural
o Structural
o Data
o Control
101. Choose hazard for the following definition: an instruction
cannot continue because it needs a value that has not yet been
generated by an earlier instruction
• Data
o Data
o Structural
o Control
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102. Choose hazard for the following definition: fetch cannot con-
tinue because it does not know the outcome of an earlier branch
- special case of a data hazard
• Control
o Control
o Structural
o Data
103. A technique used in advanced microprocessors where the
microprocessor begins executing a first instruction before the
second has been completed is called pipelining • False
o True
o False
104. Stage in which the instruction is fetched from memory and
placed in the instruction register called
o Memory read/write
o Instruction Decode • Instruction Fetch
o Execution
o Write Back
o Instruction Fetch
105. Which stage is responsible for storing and loading values to
and from memory?
o Instruction Fetch
o Memory read/write • Memory read/write
o Instruction Decode
o Execution
o Write Back
106. How the stage in which the results of the operation are written
to the destination register is called?
o Instruction Fetch
o Write Back • Write Back
o Execution
o Memory read/write
107. In execution stage identification of the operation is performed
o True • False
o False
108. Choose data dependences
o Read-After-Read • Read-After-Write
o Read-After-Write • Write-After-Write
o Write-After-Write • Write-After-Read
o Write-After-Read
109. Halting the flow of instructions until the required result is
ready to be used is called
o waiting
• stalling
o delaying
o halting
o stalling
110. A common measure of performance for a processor is the
rate at which instructions are executed, called
o CPI
• MIPS
o Clock Rate
o MFLOPS
o MIPS
111. Floating point performance is expressed as
o CPI
o FLOPS • MFLOPS
o MIPS
o MFLOPS
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2 A5B8:
112. Choose the key characteristics of computer memory systems
o Stalling
• Location
o Unit of Transfer
• Unit of Transfer
o Hazards
• Access Method
o Location
o Access Method
o Capacity
• Capacity
o Performance
• Performance
o Organization
• Organization
o Instruction Fetch
• Physical Type
o Physical Type
• Physical Characteristics
o Physical Characteristics
• Access Method
o Access Method
• Unit of Transfer
o Unit of Transfer
• Performance
o Performance
115. Word is the "natural" unit of organization of memory
o True • True
o False
116. The "natural" unit of organization of memory is called block
o True • False
o False
117. After implementing embedded systems, you can easily use
them for another purposes
• False
o True
o False
118. Digital circuits are inflexible and slower, because they are
technology dependent
• False
o True
o False
119. When using microprocessor based systems, it is enough to
update the software
• True
o True
o False
120. For random-access memory, the time it takes to perform a
read or write operation is called
o Clock Rate • Access Time
o CPI • Latency
o Access Time
o Latency
121. The rate at which data can be transferred into or out of a
memory unit is called
o Transfer time
o Transfer Rate • Transfer Rate
o MIPS
o FLOPS
o MFLOPS
122. The particular block is currently being stored is called tag
o True • True
o False
123. How many elements of cache design are there?
o2
o5
•7
o4
o6
o7
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2 A5B8:
124. Choose the element(s) of cache design
o Tag
o Latency • Mapping Function
o AMAT • Replacement Algorithm
o Mapping Function • Number of Caches
o Replacement Algorithm
o Number of Caches
125. Choose the element(s) of cache design
o Tag
o Latency • Cache Size
o AMAT • Line Size
o Cache Size • Number of Caches
o Line Size
o Number of Caches
126. There are three types of cache addresses
o True • False
o False
127. There are two types of mapping functions
o True • False
o False
128. We can find needed block in associatively mapped cache by
its block address
• False
o True
o False
129. How many access methods are there?
o3
o2
•3
o4
o5
o6
130. Choose the type(s) of auxiliary memory
o Flash Memory
o Optical Disk • Flash Memory
o Hard Drive • Optical Disk
o SSD
o RAM
131. How many performance factors are there
o5
o4
•5
o3
o2
o6
132. Choose the performance factor(s)
o Cache Size
o Line Size
• Instruction Count
o Instruction Count
• Number of Processor Cycles
o Number of Processor Cycles
o Mapping function
o Latency
133. Choose the performance factor(s)
o Cache Size
• Instruction Count
o Line Size
• Number of Processor Cycles
o Instruction Count
• Number of memory references
o Number of Processor Cycles
o Number of memory references
134. Choose the system attribute(s) by which the performance
factors are influenced
o Cache size
o Unit of Transfer
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2 A5B8:
o Compiler Technology • Compiler Technology
o Processor Implementation • Processor Implementation
o Cache and memory hierarchy • Cache and memory hierarchy
135. How many physical characteristics of disk systems are there?
o4
o5
•5
o2
o3
o6
136. Choose the physical characteristic(s) of disk systems
o Head Mechanism
• Head Mechanism
o Platters
• Platters
o Disk Size
• Sides
o Sides
o Disk system implementstion
137. Choose the physical characteristic(s) of disk systems
o Disk system implementstion
• Head Mechanism
o Disk Size
• Head Motion
o Head Mechanism
• Disk Portability
o Head Motion
o Disk Portability
138. What does RAID stand for?
o Random Array of Independent Disks
o Redundant Array of Independent Disks • Redundant Array of Independent Disks
o Redundant Array of Interoperable Disks
o Random Access to Independent Disks
139. The RAID scheme consists of 7 levels
o True • True
o False
140. Choose the components of SSD
o Controller
• Controller
o Addressing
• Addressing
o Data buffer/cache
• Data buffer/cache
o Data size
o Memory hierarchy
141. SSD is over 10 times faster than the spinning disks in HDD
o True • True
o False
142. SSDs are susceptible to mechanical wear
o True • False
o False
143. SSDs are more susceptible to physical shock and vibration
o True • False
o False
144. SSD stands for
o Solid State Drive
o Solid State Driver • Solid State Drive
o Speed State Drive
o Speed State Driver
145. Choose the component of SSD for the following definition:
provides SSD device level interfacing and firmware execution
o Controller
o Addressing • Controller
o Data buffer/cache
o Error correction
o Flash memory components
Logic for error detection and correction
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o Error Correction
o Addressing
o Data buffer/cache • Error Correction
o Controller
o Flash memory components
Individual NAND flash chips
o Flash Memory Components
o Addressing • Flash Memory Components
o Data buffer/cache
o Controller
o Error Correction
Logic that performs the selection function across the flash mem-
ory components
o Addressing
• Addressing
o Data buffer/cache
o Controller
o Error Correction
High speed RAM memory components used for speed matching
and to increased data throughput
o Data buffer/cache
• Data buffer/cache
o Addressing
o Controller
o Error Correction
150. The basic element of a semiconductor memory is the mem-
ory cell
• True
o True
o False
151. How external nonvolatile memory is called?
o Secondary memory
o Main memory • Secondary memory
o Cache memory
o Virtual memory
152. What is included into physical type characteristic of computer
memory systems?
o Semiconductor
• Semiconductor
o Magnetic
• Magnetic
o Word
o Access Time
o Number of bytes
153. What is included into performance characteristic of computer
memory systems?
o Access time
• Access time
o Cycle Time
• Cycle Time
o Transfer Rate
• Transfer Rate
o Word
o Number of bytes
o Number of words
154. What does IDE stand for? • Integrated Development Environment
155. Choose the characteristics of CISC processors

o large number of instructions • large number of instructions
o support many addressing modes • support many addressing modes
o more elaborate way of accessing data • more elaborate way of accessing data
o less number of instructions
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o instructions are of fixed length
o few addressing modes
156. Choose the characteristics of RISC processors
o less number of instructions
o large number of instructions • less number of instructions
o instructions are of fixed length • instructions are of fixed length
o support many addressing modes • few addressing modes
o more elaborate way of accessing data
o few addressing modes
157. Choose the characteristics of Von Neumann architecture
o one memory for data and program
o CPU provides address to get data or instructions
• one memory for data and program
o data and instructions must have the same width
• CPU provides address to get data or instructions
o separate busses, can be accessed simultaneously
• data and instructions must have the same width
o separated buses allow one instruction to execute while the next
instruction is fetched
o data and instructions mustn't have the same width
158. Choose the characteristics of Harvard architecture
o separate program and data memories
o separated buses allow one instruction to execute while the next • separate program and data memories
instruction is fetched • separated buses allow one instruction to execute while the next
o data and instructions mustn't have the same width instruction is fetched
o one memory for data and program • data and instructions mustn't have the same width
o CPU provides address to get data or instruction
o data and instructions must have the same width
159. Which of the following architectures differs by memory ac-
cessing?
o Von Neumann • Von Neumann
o Harvard • Harvard
o Complex Instruction Set Computers
o Reduced Instruction Set Computers
160. Choose the correct answer for the following characteristics:
1. Depend mainly on its peripherals 2. Used for a few dedicated
functions 3. Usually used as a part of a larger system • Microcontroller
o Microcontroller
o General purpose microprocessor
161. Choose the correct syntax of assembly statements
o name operation operand(s) comments
o operation name operand(s) comments • name operation operand(s) comments
o operation operand(s) name comments
o comments name operation operand(s)
162. The assembler translates names into memory addresses
o True • True
o False
163. Name field of assembly statement is not case sensitive
o True • True
o False
164. Choose the legal name(s) in assembly
o @variable_name
• @variable_name
o variable?
• variable?
o variable&name
o variable name o 1variable
165. In two-operand instruction, the first operand is source and the
second operand is destination
• False
o True
o False
• False
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166. An instruction may have one or more operands
o True
o False
167. In assembly language you can express data only in binary
and decimal
• False
o True
o False
168. You should use a radix symbol in order to differentiate be-
tween binary, octal or hexadecimal
• True
o True
o False
169. Which symbol you should use to leave the variable uninitial-
ized
o?
•?
o!
o@
o$
170. In assembly language, you can skip the name of variable
o True • True
o False
171. Choose the correct syntax of variable declaration in assembly
o variable_name type initial_value
o type variable_name initial_vaule • variable_name type initial_value
o variable_name type initial_value
o type initial_value variable_name
173. Choose the definition of code segment in assembly
o Contains a program's instructions
• Contains a program's instructions
o A block of memory to store a stack
o All variable definitions
174. Choose the definition of data segment in assembly
• All variable definitions
175. Choose the definition of stack segment in assembly
• A block of memory to store a stack
176. There is no memory allocated for constants in assembly
language
• True
o True
o False
177. Which keyword you should use in order to define a constant
in assembly language
o EQU
o DD • EQU
o CONST
o EQ
o DW
178. In assembly statement name and comment are mandatory
o True • False
o False
179. How many deadlock recovery algorithms are there?
o4
o3
•4
o2
o5
o1
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180. There are 3 approaches of deadlock avoidance
o True • False
o False
181. There are 2 policies of deadlock prevention
o True • True
o False
182. Choose the correct approach for the following definition
"involves recognizing when deadlock has occurred, and trying to
recover"
• Deadlock detection and recovery
o Deadlock detection and recovery
o Deadlock avoidance
o Deadlock prevention
183. Choose the correct approach for the following definition "in-
volves making dynamic choices that guarantee prevention"
o Deadlock avoidance • Deadlock avoidance
184. Choose the correct approach for the following definition
"adopting a static policy that disallows one of the four conditions
above"
• Deadlock prevention
o Deadlock avoidance
185. There are 4 approaches of dealing with deadlock
o True • False
o False
186. Choose the correct answer for the following definition "A
closed chain of processes exists, such that each process is
blocked waiting for a resource held by another process in the set"
o Circular wait • Circular wait
o Mutual exclusion
o No preemption
o Hold and wait
187. Choose the correct answer for the following definition: "No
process can be forced to release a resource"
o No preemption
• No preemption
o Mutual exclusion
o Hold and wait
o Circular wait
188. Choose the correct answer for the following definition "A
process may hold some resources while waiting for others"
o Hold and wait
• Hold and wait
o Mutual exclusion
o Circular wait
o No pre-emption
189. Choose the correct answer for the following definition "Only
one process may use a resource at one time"
o Mutual exclusion
• Mutual exclusion
o Circular wait
o No preemption
o Hold and wait
190. How many policy conditions for deadlock to be possible are
there?
o3
o4 •3
o2
o5
o1
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191. What is the deadlock?
o Permanent blocking of a set of processes that either compete
for global resources or communicate with each other
o Interleaving of processes in time to give the appearance of
simultaneous execution • Permanent blocking of a set of processes that either compete for
o When one process is inside a critical section of code, oth- global resources or communicate with each other
er processes must be prevented from entering that section o
Processes "communicate" via global counters that are initialized
to a positive integer and that can be accessed only through two
atomic operations
192. Deadlock occurs when each process in the set is blocked
awaiting an event that can be triggered only by another blocked
process in the set • True
o True
o False
193. In which of the following approaches there is no shared data?
o Message passing
o Mutual exclusion • Message passing
o Monitors
o Semaphores
194. Choose the correct answer for the following definition "Syn-
chronization between processes is defined by the blocking policy
attached to the sending and receiving of messages"
o Message passing • Message passing
o Mutual exclusion
o Monitors
o Semaphores
195. Monitors are similar to classes in java and has methods and
fields
• True
o True
o False
196. In atomic operations semSignal(x) and semWait(x), what is
the 'x'?
o The number of processes that can execute critical section
• The number of processes that can execute critical section
o The number of processes
o The number of monitors
o No correct answer
197. When using semaphores, processes communicate using
messages
• False
o True
o False
198. We can implement mutex through the OS or using program-
ming languages
• True
o True
o False
199. How many approaches of mutex implementation are there?
o3
o4
•3
o2
o5
o1
200. Choose the correct answer for the following definition "When
one process is inside a critical section of code, other processes
must be prevented from entering that section"
o Mutual exclusion
• Mutual exclusion
o Semaphores
o Monitors
o Message passing
o Critical section
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201. In concurrency optimal allocation of resources is difficult
o True • True
o False
202. In concurrency, locating programming errors can't be difficult,
because the contexts in which errors occur cannot always be
reproduced easily • False
o True
o False
203. In concurrency, sharing global resources safely is difficult
o True • True
o False
204. Concurrency offers genuine simultaneous execution
o True • False
o False
205. Parallelism is interleaving of processes in time to give the
appearance of simultaneous execution
• False
o True
o False
206. Choose the correct answer for the following definition "mul-
tiple processes on multiple systems"
o Distributed processing • Distributed processing
o Multiprogramming
o Multiprocessing
tiple processes on a system with multiple processors"
o Multiprocessing • Multiprocessing
o Multiprogramming
o Distributed processing
tiple processes on a system with a single processor"
o Multiprogramming • Multiprogramming
o Multiprocessing
o Distributed processing
209. How many categories of process management are there?
o3
o2
•3
o4
o5
o1
210. Operations performed by a processor, such as fetching an
instruction, decoding the instruction, performing an arithmetic
operation, and so on, are governed by:
o a system clock
• a system clock
o a system processor
o a clock processor
o a processor
o a clock
211. Typically all operations performed by a processor begin with
the:
o pulse of the clock
o pulse of the processor • pulse of the clock
o it begins by itself
o both of clock and processor pulse
o none of the above
212. The time between pulses called?

o Cycle time • Cycle time
o Clock speed
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o Clock rate
o Clock cycle
213. A processor is driven by a clock with a constant frequency f
or, equivalently, a constant cycle time t, where t = 1/f:
o Instruction execution rate
o Instruction execution cycle • Instruction execution rate
o Instruction execution time
o Instruction execution period
o None of the above
214. Measures such as MIPS and MFLOPS have proven ade-
quate to evaluating the performance of processors.
• False
o False
o True
215. ENIAC stands for:
o Electronic Numerical Integrator and Computer
o Electronic Nuclear Integrator and Computer
• Electronic Numerical Integrator and Computer
o Encapsulation Numerical Integrator and Commerce
o Encapsulation Numerical Integrator and Computer
o Electronic Numerical Integer and Computer
216. Contains a word to be stored in memory or sent to the I/O
unit, or is used to receive a word from memory or from the I/O unit
o Memory buffer register (MBR)
o Memory address register (MAR) • Memory buffer register (MBR)
o Instruction register (IR)
o Instruction buffer register (IBR)
o Program counter (PC)
217. Specifies the address in memory of the word to be written
from or read into the MBR
o Memory address register (MAR)
o Memory buffer register (MBR) • Memory address register (MAR)
218. Contains the 8-bit opcode instruction being executed
o Memory buffer register (MBR)
• Instruction register (IR)
219. Employed to hold temporarily the right-hand instruction from
a word in memory
o Memory buffer register (MBR) • Instruction buffer register (IBR)
220. Contains the address of the next instruction pair to be fetched
from memory
o Memory buffer register (MBR) • Program counter (PC)
221. The use of the _______ defines the second generation of

computers.
o Transistor • Transistor
o Vacuum tube
o Small and medium-scale integration
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o Large-scale integration
222. The use of the _______ defines the first generation of com-
puters.
o Vacuum tube
o Transistor • Vacuum tube
223. The use of the _______ defines the third generation of
computers.
o Transistor • Small and medium-scale integration
o Vacuum tube
224. RAID stands for
o Redundant Array Independent Disk
o Random Access Integral Disk
• Redundant Array Independent Disk
o Redundant Access Integral Disk
o Random Array Independent Disk
o Redundant Access Independent Disk
225. The basic element of a semiconductor memory is:
o Memory cell
o Cache memory
• Memory cell
o RAM
o DRAM
o None of the above
226. A state in which data requested for processing by a compo-
nent or application is found in the cache memory
o Cache hit
o Cache miss • Cache hit
o Cache set
o Cache overwrites
o Cache access time
227. For random-access memory, this is the time it takes to per-
form a read or write operation
o Access time
o Memory cycle time • Access time
o Transfer rate
o Performance
o All of the above
228. Memory is organized into units of data, called records; access
must be made in a specific linear sequence
o Sequential access
o Word • Sequential access
o Addressable units
o Unit of transfer
o Direct access
229. The "natural" unit of organization of memory
o Word
o Sequential access
• Word
o Addressable units
o Unit of transfer
o Direct access
230. Moore's law: "The cost of a chip has remained virtually
unchanged during this period of rapid growth in density. This
• False
means that the cost of computer logic and memory circuitry has
increasing at a dramatic rate"
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o False
o True
231. Moore's law: "Because logic and memory elements are
placed closer together on more densely packed chips, the elec-
trical path length is shortened, decreasing operating speed" • False
o False
o True
232. Moore's law: "The computer becomes smaller, making it more
convenient to place in a variety of environments"
• True
o True
o False
233. Moore's law: "There is a reduction in power and cooling
requirements"
• True
o True
o False
234. Moore's law: "The interconnections on the integrated circuit
are much more reliable than solder connections. With less circuitry
on each chip, there are fewer interchip connections" • True
o True
o False
235. Processor can simultaneously work on multiple instructions.
How this technique called?
o Pipelining
o Branch prediction • Pipelining
o None of the above
236. The L2 cache is slower and typically larger than the L1 cache,
and the L3 cache is slower and typically larger than the L2 cache
• True
o True
o False
237. The L2 cache is faster and typically larger than the L1 cache,
and the L3 cache is slower and typically larger than the L2 cache
• False
o False
o True
1. What is a Latency:
o is time for a single access - Main memory latency is usually >>
than processor cycle time
o is the number of accesses per unit time - If m instructions are • is time for a single access - Main memory latency is usually >>
loads/stores, 1 + m memory accesses per instruction, CPI = 1 than processor cycle time
requires at least 1 + m memory accesses per cycle
o is amount of data that can be in flight at the same time (Little's
Law)
2. What occurs at Instruction fetches when we speak about Com-
mon And Predictable Memory Reference Patterns?
o n loop iterations • n loop iterations
o subroutine call
o vector access
3. What occurs at Stack access when we speak about Common
And Predictable Memory Reference Patterns?
o subroutine call • subroutine call
o n loop iterations
o vector access
4. What occurs at Data access when we speak about Common
And Predictable Memory Reference Patterns?
o subroutine call • vector access
o n loop iterations
o vector access
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5. Cache HIT:
o No Write Allocate, Write Allocate • Write Through, Write Back
o Write Through, Write Back
6. Cache MISS:
o No Write Allocate, Write Allocate • No Write Allocate, Write Allocate
o Write Through, Write Back
7. Average Memory Access Time is equal:
o Hit Time * ( Miss Rate + Miss Penalty )
o Hit Time - ( Miss Rate + Miss Penalty ) • Hit Time + ( Miss Rate * Miss Penalty )
o Hit Time / ( Miss Rate - Miss Penalty )
o Hit Time + ( Miss Rate * Miss Penalty )
8. Compulsory -
o cache is too small to hold all data needed by program, occur
even under perfect replacement policy (loop over 5 cache lines)
• first-reference to a block, occur even with infinite cache
o first-reference to a block, occur even with infinite cache
o misses that occur because of collisions due to less than full
associativity (loop over 3 cache lines)
9. Capacity -
even under perfect replacement policy (loop over 5 cache lines) • cache is too small to hold all data needed by program, occur even
o misses that occur because of collisions due to less than full under perfect replacement policy (loop over 5 cache lines)
associativity (loop over 3 cache lines)
10. Conflict -
o misses that occur because of collisions due to less than full • first-reference to a block, occur even with infinite cache (NOT
associativity (loop over 3 cache lines) CORRECT!!!)
even under perfect replacement policy (loop over 5 cache lines)
11. Algorithm for Cache HIT:
o Processor issues load request to cache -> Replace victim block
in cache with new block -> return copy of data from cache
• Processor issues load request to cache -> Compare request
o Processor issues load request to cache -> Read block of data
address to cache tags and see if there is a match -> return copy
from main memory -> return copy of data from cache
of data from cache
o Processor issues load request to cache -> Compare request
address to cache tags and see if there is a match -> return copy
of data from cache
12. Algorithm for Cache MISS:
• Processor issues load request to cache -> Compare request
address to cache tags and see if there is a match -> Read block
o Processor issues load request to cache -> Compare request
of data from main memory -> Replace victim block in cache with
address to cache tags and see if there is a match -> Read block
new block -> return copy of data from cache
of data from main memory -> Replace victim block in cache with
o Processor issues load request to cache -> Read block of data
new block -> return copy of data from cache
from main memory -> return copy of data from cache
o Processor issues load request to cache -> Replace victim block
in cache with new block -> return copy of data from cache
13. The formula of "Iron Law" of Processor Performance:
o time/program = instruction/program * (cycles/instruction)*
time/cycle
• time/program = instruction/program * (cycles/instruction) *
o time/program = instruction/program * (cycles/instruction) +
time/cycle
time/cycle
o time/program = instruction/program + (cycles/instruction) *
time/cycle
14. Structural Hazard:

o An instruction in the pipeline needs a resource being used by
• An instruction in the pipeline needs a resource being used by
another instruction in the pipeline
o An instruction depends on a data value produced by an earlier
instruction
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o Whether or not an instruction should be executed depends on a
control decision made by an earlier instruction
15. Data Hazard:
o An instruction depends on a data value produced by an earlier
instruction
• An instruction depends on a data value produced by an earlier
o An instruction in the pipeline needs a resource being used by
instruction
o Whether or not an instruction should be executed depends on a
control decision made by an earlier instruction
17. What is a Bandwidth:
o a is the number of accesses per unit time - If m instructions are
loads/stores, 1 + m memory accesses per instruction, CPI
• a is the number of accesses per unit time - If m instructions are
= 1 requires at least 1 + m memory accesses per cycle
o is time for a single access - Main memory latency is usually >>
than processor cycle time
Law)
18. What is a Bandwidth-Delay Product:
Law)
o is time for a single access - Main memory latency is usually >> • is amount of data that can be in flight at the same time (Little's
than processor cycle time Law)
o is the number of accesses per unit time - If m instructions are
19. What is Computer Architecture?
o is the design of the abstraction/implementation layers that allow
us to execute information processing applications efficiently using
manufacturing technologies
• is the design of the abstraction/implementation layers that allow
o is a group of computer systems and other computing hardware
us to execute information processing applications efficiently using
devices that are linked together through communication channels
manufacturing technologies
to facilitate communication and resource-sharing among a wide
range of users
o the programs used to direct the operation of a computer, as well
as documentation giving instructions on how to use them
20. Least Recently Used (LRU):
o cache state must be updated on every access
• cache state must be updated on every access
o Used in highly associative caches
o FIFO with exception for most recently used block(s)
21. Cache Hit -
o Write Through - write both cache and memory, generally higher
traffic but simpler to design • Write Through - write both cache and memory, generally higher
o write cache only, memory is written when evicted, dirty bit per traffic but simpler to design
block avoids unnecessary write backs, more complicated
o No Write Allocate - only write to main memory
22. Reduce Miss Rate: Large Cache Size. Empirical Rule of
Thumb:
o If cache size is doubled, miss rate usually drops by about 2
• If cache size is doubled, miss rate usually drops by about 2
o Direct-mapped cache of size N has about the same miss rate
as a two-way set- associative cache of size N/2
o None of them
23. Reduce Miss Rate: High Associativity. Empirical Rule of
Thumb:
o Direct-mapped cache of size N has about the same miss rate • Direct-mapped cache of size N has about the same miss rate as
as a two-way set- associative cache of size N/2 a two-way set- associative cache of size N/2
o If cache size is doubled, miss rate usually drops by about 2
o None of them
24. Exploit temporal locality:
o by remembering the contents of recently accessed locations
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o by fetching blocks of data around recently accessed locations
• by remembering the contents of recently accessed locations
o None of them
25. Exploit spatial locality:
o by fetching blocks of data around recently accessed locations
• by fetching blocks of data around recently accessed locations
o by remembering the contents of recently accessed locations
o None of them
28. What is the access time?
o Time between when a read is requested and when the desired
word arrives
• Time between when a read is requested and when the desired
o The minimum time between requests to memory.
word arrives
o Describes the technology inside the memory chips and those
innovative, internal organizations
o None of them
29. What is the cycle time?
o The minimum time between requests to memory.
o Time between when a read is requested and when the desired
• The minimum time between requests to memory.
word arrives
o The maximum time between requests to memory.
o None of them
32. What does DDR stands for?
o Double data rate
o Dual data rate • Double data rate
o Double data reaction
o None of them
33. What is kernel process?
o Provide at least two modes, indicating whether the running
process is a user process or an operating system process
o Provide at least five modes, indicating whether the running • Provide at least two modes, indicating whether the running
process is a user process or an operating system process process is a user process or an operating system process
o Provide a portion of the processor state that a user process can
use but not write
o None of them
34. If we talk about storage systems an interaction or transaction
with a computer is divided for first what is an "System response
time" - ?:
o The time between when the user enters the command and the • The time between when the user enters the command and the
complete response is displayed complete response is displayed
o The time for the user to enter the command
o The time from the reception of the response until the user begins
to enter the next command
with a computer is divided for first what is an "Think time" - ?:
• The time from the reception of the response until the user begins
o The time between when the user enters the command and the
complete response is displayed
36. Little's Law and a series of definitions lead to several useful
equations for "Time server" - :
o Average time to service a task; average service rate is 1/Time
• Average time to service a task; average service rate is 1/Time
server traditionally represented by the symbol ¼ in many queuing
server traditionally represented by the symbol ¼
in many queuing
texts
texts
o Average time per task in the queue
o Average time/task in the system, or the response time, which is
the sum of Time queue and Time server
equations for "Time queue" - :
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in many queuing
texts
• Average time per task in the queue
equations for "Time system" - :
the sum of Time queue and Time server • Average time/task in the system, or the response time, which is
o Average time to service a task; average service rate is 1/Time the sum of Time queue and Time server
texts
What is the description(s) of Transistors?
A. A semiconductor device used to amplify electronic signals and
electrical power.
A. A semiconductor device used to amplify electronic signals and
B. A semiconductor device used to switch electronic signals and
electrical power.
electrical power.
B. A semiconductor device used to switch electronic signals and
C. A semiconductor device used to amplify or switch electronic
electrical power.
signals and electrical power.
C. A semiconductor device used to amplify or switch electronic
D. A semiconductor device used to reduce or switch electronic
E. A semiconductor device used to reduce or combine electronic
equations for "Length server" - :
• Average number of tasks in service
o Average number of tasks in service
o Average length of queue
equations for "Length queue" -:
• Average length of queue
41. How many issue queue used in Centralized Superscalar 2 and
Exceptions?
o4
•1
o3
o2
o1
42. How many issue queue used in Distributed Superscalar 2 and
Exceptions:
o4
•2
o3
o1
o2
43. How many instructions used in Distributed Superscalar 2 and
Exceptions?
o4
•2
o3
o2
o1
44. Which of the following formula is true about Issue Queue for
"Instruction Ready":
o Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no
structural hazards
o Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no • Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no
structural hazards structural hazards
structural hazards
structural hazards
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45. What is a ARF:
o Architectural Register File
o Architecture Relocation File • Architectural Register File
o Architecture Reload File
o Architectural Read File
46. What is a ROB?
o Reorder Buffer
o Read Only Buffer • Reorder Buffer
o Reload Buffer
o Recall Buffer
47. What is a FSB?
o Finished Store Buffer
o Finished Stack Buffer • Finished Store Buffer
o Finished Stall Buffer
o Finished Star Buffer
48. What is a PRF?
o Physical Register File
o Pending Register File • Physical Register File
o Pipeline Register File
o Pure Register File
49. What is a SB?
o Scoreboard
o Scorebased • Scoreboard
o Scaleboard
o Scalebit
50. How many stages used in Superscalar (Pipeline)?
o5
o4 •5
o6
o7
51. What is about Superscalar means "F-D-X-M-W"?
o Fetch, Decode, Execute, Memory, Writeback
o Fetch, Decode, Instruct, Map, Write • Fetch, Decode, Execute, Memory, Writeback
o Fetch, Decode, Excite, Memory, Write
o Fetch, Decode, Except, Map, Writeback
52. Speculating on Exceptions "Prediction mechanism" is -
• Exceptions are rare, so simply predicting no exceptions is very
accurate
o Exceptions detected at end of instruction execution pipeline, • Exceptions are rare, so simply predicting no exceptions is very
special hardware for various exception types accurate
o Only write architectural state at commit point, so can throw away
partially executed instructions after exception
o None of them
53. Speculating on Exceptions "Check prediction mechanism" is -
o Exceptions detected at end of instruction execution pipeline,
special hardware for various exception types
• Exceptions detected at end of instruction execution pipeline,
o Exceptions are rare, so simply predicting no exceptions is very
special hardware for various exception types
accurate
o The way in which an object is accessed by a subject
o None of them
54. Speculating on Exceptions "Recovery mechanism" is -
o Only write architectural state at commit point, so can throw away
• Only write architectural state at commit point, so can throw away
o Exceptions are rare, so simply predicting no exceptions is very
accurate
o An entity capable of accessing objects
o None of them
55. What is a RT?
o Rename Table
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o Recall Table
o Relocate Table • Rename Table
o Remove Table
56. What is a FL?
o Free List
o Free Last • Free List
o Free Leg
o Free Launch
57. What is an IQ?
o Issue Queue
o Internal Queue • Issue Queue
o Interrupt Queue
o Instruction Queue
58. At VLIW "Superscalar Control Logic Scaling" which parame-
ters are used?
o Width and Lifetime
• Width and Lifetime
o Width and Height
o Time and Cycle
o Length and Addition
59. Out-of-Order Control Complexity MIPS R10000 which element
is in Control Logic?
o Register name
• Register name
o Instruction cache
o Data tags
o Data cache
60. Out-of-Order Control Complexity MIPS R10000 which element
is not in Control Logic?
o Integer Datapath
• Integer Datapath
o CLK
o Free List
o Address Queue
61. What is "VLIW"?
o Very Long Instruction Word
o Very Less Interpreter Word • Very Long Instruction Word
o Very Light Internal Word
o Very Low Invalid Word
62. At VLIW by "performance and loop iteration" which time is
longer?
• Loop Unrolled
o Loop Unrolled
o Software Pipelined
63. At VLIW by "performance and loop iteration" which time is
shorter?
• Software Pipelined
o Software Pipelined
o Loop Unrolled
64. At VLIW Speculative Execution, which of this solution is true
about problem: Branches restrict compiler code motion?
• Speculative operations that don't cause exceptions
o Speculative operations that don't cause exceptions
o Hardware to check pointer hazards
65. Speculative Execution, which of this solution is true about
problem: Possible memory hazards limit code scheduling:
• Hardware to check pointer hazards
o Hardware to check pointer hazards
66. What is an ALAT? :
o Advanced Load Address Table
o Allocated Link Address Table • Advanced Load Address Table
o Allowing List Address Table
o Addition Long Accessibility Table
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67. At VLIW Multi-Way Branches, which of this solution is true
about problem: Long instructions provide few opportunities for
branches: • Allow one instruction to branch multiple directions
o Allow one instruction to branch multiple directions
68. What is a Compulsory?
• first-reference to a block, occur even with infinite cache
even under perfect replacement policy
associativity
69. What is a Capacity?
even under perfect replacement policy • cache is too small to hold all data needed by program, occur even
o first-reference to a block, occur even with infinite cache under perfect replacement policy
associativity
70. What is a Conflict?
associativity • misses that occur because of collisions due to less than full
o first-reference to a block, occur even with infinite cache associativity
even under perfect replacement policy
71. In Multilevel Caches "Local miss rate" equals =
o misses in cache / accesses to cache
• misses in cache / accesses to cache
o misses in cache / CPU memory accesses
o misses in cache / number of instructions
72. In Multilevel Caches "Global miss rate" equals =
• misses in cache / CPU memory accesses
73. In Multilevel Caches "Misses per instruction" equals =
• misses in cache / number of instructions
74. Non-Blocking Cache Timeline for "Blocking Cache" the se-
quence is - ?
o CPU time-Cache Miss-Miss Penalty-CPU time
o CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU • CPU time-Cache Miss-Miss Penalty-CPU time
time
o CPU time->Cache Miss->Miss->Stall on use->Miss Penal-
ty->CPU time
75. Non-Blocking Cache Timeline for "Hit Under Miss" the se-
quence is -?
o CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU
• CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU
time
time
ty->CPU time
76. Non-Blocking Cache Timeline for "Miss Under Miss" the se-
quence is -?
• CPU time->Cache Miss->Miss->Stall on use->Miss Penal-
ty->Miss Penalty->CPU time
ty->Miss Penalty->CPU time
o CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU
time
77. What does mean MSHR?
o Miss Status Handling Register • Miss Status Handling Register
o Map Status Handling Reload
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o Mips Status Hardware Register
o Memory Status Handling Register
78. What does MAF?
o Miss Address File
• Miss Address File
o Map Address File
o Memory Address File
79. At Critical Word First for Miss Penalty chose correct sequence
of Basic Blocking Cache "Order of fill":
• 0,1,2,3,4,5,6,7
o 0,1,2,3,4,5,6,7
o 3,4,5,6,7,0,1,2
80. At Critical Word First for Miss Penalty chose correct sequence
of Blocking Cache with Critical Word first "Order of fill":
• 3,4,5,6,7,0,1,2
o 3,4,5,6,7,0,1,2
o 0,1,2,3,4,5,6,7
81. Storage Systems, "Larger block size to reduce miss rate" -
o The simplest way to reduce the miss rate is to take advantage
of spatial locality and increase the block size • The simplest way to reduce the miss rate is to take advantage of
o The obvious way to reduce capacity misses is to increase cache spatial locality and increase the block size
capacity
o Obviously, increasing associativity reduces conflict misses
82. Storage Systems, "Bigger caches to reduce miss rate" -
o The obvious way to reduce capacity misses is to increase cache
capacity • The obvious way to reduce capacity misses is to increase cache
o Obviously, increasing associativity reduces conflict misses capacity
of spatial locality and increase the block size
83. Storage Systems, "Higher associativity to reduce miss rate" -
o Obviously, increasing associativity reduces conflict misses
o The obvious way to reduce capacity misses is to increase cache
• Obviously, increasing associativity reduces conflict misses
capacity
of spatial locality and increase the block size
84. In Non-Blocking Caches what does mean "Critical Word First"?
o Request the missed word first from memory and send it to
the processor as soon as it arrives; let the processor continue • Request the missed word first from memory and send it to
execution while filling the rest of the words in the block the processor as soon as it arrives; let the processor continue
o Fetch the words in normal order, but as soon as the requested execution while filling the rest of the words in the block
word of the block arrives, send it to the processor and let the
processor continue execution
85. In Non-Blocking Caches what does mean "Early restart"?
o Fetch the words in normal order, but as soon as the requested
word of the block arrives, send it to the processor and let the • Fetch the words in normal order, but as soon as the requested
processor continue execution word of the block arrives, send it to the processor and let the
o Request the missed word first from memory and send it to processor continue execution
the processor as soon as it arrives; let the processor continue
execution while filling the rest of the words in the block
86. A virus classification by target includes the following cate-
gories, What is a File infector?
o Infects files that the operating system or shell consider to be
• Infects files that the operating system or shell consider to be
executable
executable
o A typical approach is as follows
o The key is stored with the virus
o Far more sophisticated techniques are possible
87. What is a RAID 0?
o It has no redundancy and is sometimes nicknamed JBOD, for
• It has no redundancy and is sometimes nicknamed JBOD, for
"just a bunch of disks," although the data may be striped across
"just a bunch of disks," although the data may be striped across
the disks in the array
o Also called mirroring or shadowing, there are two copies of every
piece of data
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o This organization was inspired by applying memory-style error
correcting codes to disks
piece of data
o It has no redundancy and is sometimes nicknamed JBOD, for • Also called mirroring or shadowing, there are two copies of every
"just a bunch of disks," although the data may be striped across piece of data
o It has no redundancy and is sometimes nicknamed JBOD, for • This organization was inspired by applying memory-style error
"just a bunch of disks," although the data may be striped across correcting codes to disks
piece of data
o Since the higher-level disk interfaces understand the health of
a disk, it's easy to figure out which disk failed • Since the higher-level disk interfaces understand the health of a
o Many applications are dominated by small accesses disk, it's easy to figure out which disk failed
piece of data
o Many applications are dominated by small accesses
o Since the higher-level disk interfaces understand the health of
• Many applications are dominated by small accesses
a disk, it's easy to figure out which disk failed
piece of data
92. At storage systems Gray and Siewiorek classify faults what
does mean "Hardware faults"? :
o Devices that fail, such as perhaps due to an alpha particle hitting • Devices that fail, such as perhaps due to an alpha particle hitting
a memory cell a memory cell
o Faults in software (usually) and hardware design (occasionally)
o Mistakes by operations and maintenance personnel
does mean "Design faults"? :
• Faults in software (usually) and hardware design (occasionally)
o Devices that fail, such as perhaps due to an alpha particle hitting
a memory cell
does mean "Operation faults"? :
• Mistakes by operations and maintenance personnel
a memory cell
does mean "Environmental faults"? :
o Fire, flood, earthquake, power failure, and sabotage
• Fire, flood, earthquake, power failure, and sabotage
a memory cell
with a computer is divided for first what is an "Entry time" - ? :
o The time for the user to enter the command • The time for the user to enter the command
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with a computer is divided for first what is an "System response
time" - ?:
o The time between when the user enters the command and the • The time between when the user enters the command and the
complete response is displayed complete response is displayed
with a computer is divided for first what is an "Think time" - ?:
equations for "Time server" - :
• Average time to service a task; average service rate is 1/Time
in many queuing
texts
texts
equations for "Time queue" - :
• Average time per task in the queue
texts
equations for "Time system" - :
the sum of Time queue and Time server • Average time/task in the system, or the response time, which is
o Average time to service a task; average service rate is 1/Time the sum of Time queue and Time server
texts
equations for "Length server" - :
• Average number of tasks in service
equations for "Length queue" -:
• Average length of queue
104. How many size of Cache L1 is true approximately? :
o 8 KB
• 8 KB
o 256 KB
o 2 MB
o 256 KB
• 256 KB
o 4 KB
o 32 MB
o 3 MB
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o 256 MB
• 3 MB
o 256 KB
107. How many main levels of Cache Memory?
o3
o2 •3
o6
o8
108. What is a "Synchronization" in Cache Memory?
o Execution in the OS that is neither idle nor in synchronization
access • Execution or waiting for synchronization variables
o Execution in user code
o Execution or waiting for synchronization variables
109. What is a "Kernel" in Cache Memory?
• Execution in the OS that is neither idle nor in synchronization
access
access
access
access
access
access
114. Network performance depends of what?
o performance of swithes and transmission system
o performance of switches • performance of swithes and transmission system
o performance of transmission system
o has no dependensies
115. The time between the start and the completion of an event
,such as milliseconds for a disk access is...
o latency
• latency
o bandwidth
o throughput
o performance
116. Total amount of work done in a given time ,such as
megabytes per second for disk transfer...
o bandwidth
• bandwidth
o latency
o throughput
o performance
117. Learning curve itself is best measured by change in...

o yeld • yeld
o bytes
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o bits
o seconds
118. Products that are sold by multiple vendors in large volumes
and are essentialy identical
o commodities
• commodities
o boxes
o folders
o files
119. Integrated circuit processes are charecterized by the
o feature size
o permanent size n • feature size
o compex size
o fixed size
120. For CMOS chips, the traditional dominant energy consump-
tion has been in switching transistors, called ____
o dynamic power
• dynamic power
o physical energy
o constant supply
o simple battery
121. Manufacturing costs that decrease over time are ____
o the learning curve
o the cycled line • the learning curve
o the regular option
o the final loop
122. Volume is a ________ key factor in determining cost.
o second
o first • second
o fifth
o third
123. The most companies spend only ____________ of their
income on R&D, which includes all engineering.
o 4% to 12%
• 4% to 12%
o 15% to 30%
o 1% to 17%
o 30% to 48%
124. Systems alternate between two states of service with respect
to an SLA:
o 1. Service accomplishment, where the service is delivered as
specified
2. Service interruption, where the delivered service is different
from the SLA
o 1. Service accomplishment, where the service is not delivered
as specified • 1. Service accomplishment, where the service is delivered as
2. Service interruption, where the delivered service is different specified
from the SLA 2. Service interruption, where the delivered service is different
o 1. Service accomplishment, where the service is not delivered from the SLA
as specified
2. Service interruption, where the delivered service is not different
from the SLA
o 1. Service accomplishment, where the service is delivered as
specified
2. Service interruption, where the delivered service is not different
from the SLA
125. Desktop benchmarks divide into __ broad classes:
o two
o three • two
o four
o five
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126. What MTTF means:
o mean time to failure
o mean time to feauture • mean time to failure
o mean this to failure
o my transfers to failure
127. A widely held rule of thumb is that a program spends __ of
its execution time in only __ of the code.
o 90% 10%
• 90% 10%
o 50% 50%
o 70% 30%
o 89% 11%
128. (Performance for entire task using the enhancement when
possible) / (Performance for entire task without using the en-
hancement) is equals to:
o Speedup • Speedup
o Efficiency
o Probability
o Ration
129. Which of the following descriptions corresponds to static
power?
o Grows proportionally to the transistor count (whether or not the
transistors are switching)
• Grows proportionally to the transistor count (whether or not the
o Proportional to the product of the number of switching transistors
and the switching rate Probability
and the switching rate
o All of the above
130. Which of the following descriptions corresponds to dynamic
power?
and the switching rate • Proportional to the product of the number of switching transistors
o Grows proportionally to the transistor count (whether or not the and the switching rate
o Certainly a design concern
o None of the above
131. Which of the written below is NOT increase power consump-
tion?
o Increasing multithreading
• Increasing multithreading
o Increasing performance
o Increasing multiple cores
o Increasing multithreading
132. Growing performance gap between peak and sustained per-
formance translates to increasing energy per unit of performance,
when:
o The number of transistors switching will be proportional to the
peak issue rate, and the performance is proportional to the sus-
• The number of transistors switching will be proportional to the
tained rate
peak issue rate, and the performance is proportional to the sus-
o The number of transistors switching will be proportionalto the
tained rate
sustained rate, and the performance is proportionalto the peak
issue rate
o The number of transistors switching will be proportional to the
sustained rate
o The performance is proportional to the peak issue rate
133. If we want to sustain four instructions per clock
o We must fetch more, issue more, and initiate execution on more
than four instructions
• We must fetch more, issue more, and initiate execution on more
o We must fetch less, issue more, and initiate execution on more
than four instructions
than two instructions
o We must fetch more, issue less, and initiate execution on more
than three instructions
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o We must fetch more, issue more, and initiate execution on less
than five instructions
134. If speculation were perfect, it could save power, since it
would reduce the execution time and save _____________, while
adding some additional overhead to implement
o Static power • Static power
o Dynamic power
o Processing rate
o Processor state
135. When speculation is not perfect, it rapidly becomes energy
inefficient, since it requires additional ___________ both for the
incorrect speculation and for the resetting of the processor state
o Dynamic power • Dynamic power
o Static power
o Processing rate
o Processor state
136. Which of these concepts is NOT illustrated case study by
Wen-mei W. Hwu and John W. Sias
o Achievable ILP with software resource constraints
• Achievable ILP with software resource constraints
o Limited ILP due to software dependences
o Achievable ILP with hardware resource constraints
o Variability of ILP due to software and hardware interaction
137. What is a hash table?
o Popular data structure for organizing a large collection of data
items so that one can quickly answer questions
o Popular data structure for updating large collections, so that one • Popular data structure for organizing a large collection of data
can hardly answer questions items so that one can quickly answer questions
o Popular tables for organizing a large collection of data structure
o Popular data structure for deletingsmall collections of data items
so that one can hardly answer questions
138. Which of these is NOT characteristics of recent highperfor-
mance microprocessors?
o Color
• Color
o Power
o Functional unit capability
o Clock rate
139. How this process called: "Operations execute as soon as their
operands are available"
o data flow execution
• data flow execution
o instruction execution
o data control execution
o instruction field execution
140. For what the reorder buffer is used :
o To pass results among instructions that may be speculated.
o To pass parameters through instructions that may be speculated
• To pass results among instructions that may be speculated.
o To get additional registers in the same way as the reservation
stations
o To control registers
141. How many fields contains the entry in the ROB:
o4
o5 •4
o6
o3
142. Choose correct fields of entry in the ROB:
• the instruction type, the destination field, the value field, and the
ready field • the instruction type, the destination field, the value field, and the
o the source type, the destination field, the value field, and the ready field
ready field
o the program type, the ready field, the parameter field, the des-
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tination field
o the instruction type, the destination field, and the ready field
143. Choose the steps of instruction execution:
o issue, execute, write result, commit
o execution, commit, rollback • issue, execute, write result, commit
o issue, execute, override, exit
o begin, write, interrupt, commit
144. Which one is not the major flavor of Multiple-issue proces-
sors:
o statistically superscalar processors
• statistically superscalar processors
o dynamically scheduled superscalar processors
o statically scheduled superscalar processors
o VLIW (very long instruction word) processors
145. Which Multiple-issue processors has not the hardware haz-
ard detection:
o EPIC
• EPIC
o Superscalar(dynamic)
o Superscalar(static)
o Superscalar(speculative)
146. Examples of EPIC:
o Itanium
o Pentium 4, MIPS R12K, IBM, Power5 • Itanium
o MIPS and ARM
o TI C6x
147. Examples of superscalar(static):
o MIPS and ARM
o Pentium 4, MIPS R12K, IBM, Power5 • MIPS and ARM
o Itanium
o TI C6x
148. Examples of superscalar(dynamic) :
o None at the present
o Pentium 4, MIPS R12K, IBM, Power5 • None at the present
o MIPS and ARM
o TI C6x
149. Examples of VLIW/LIW:
o TI C6x
o MIPS and ARM • TI C6x
o Itanium
o Pentium 4, MIPS R12K, IBM, Power5
square[i][j] what is a miss rate 12.5%
square[j][i] number of writes that miss 64
square[i][j] number of writes that hit 224
square[j][i] number of writes that hit and miss 256
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CSA Final with answers

155. Choose the characteristics of CISC processors

212. The time between pulses called?

221. The use of the _______ defines the second generation of

14. Structural Hazard:

117. Learning curve itself is best measured by change in...

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