ANALOG CIRCUITS: CURRENT MODE APPROACH

VOLTAGE MODE CIRCUITS:

* PAST
* PRESENT
* FUTURE

CURRENT MODE CIRCUITS

* The class of circuits whose function depends mainly on the use of current signals and
which can be designed and understood certainly at a basic level, using methods in which VOLTAGE need
not be consider at all.

* Such types of circuits are often called CURRENT MODE CIRCUITS

WHY CURRENT MODE CRCUITS?

* It is rapidly superceding traditional approach based on voltage mode

* It provides attractive and elegant solution for many circuit and system problems.

Key Performance features:

™ Inherently wide bandwidth

™ Wide dynamic range
™ Simpler structure
™ Easy cascadibility
™ Transistor is useful up to fT

TRANSLINEAR CIRCUIT:
*TL(Translinear Loop)
*TN(Translinear Network)
*TL: Circuits involving one or more closed loops of junctions of BJT(Emitter-Base).
*TN: Circuits which do not involve any closed loops of junctions of BJT.

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 TN Circuit TL Circuit

TRANSLNEAR CIRCUIT DESIGN PRINCIPLE:

* Introduced by B. Gilbert in 1972.

* This is a principle and technique for the design & processing of analog circuits & systems based on
current mode approach.

PRINCIPLE:

*Let there is a closed loop having:

* n- pn junctions
* junctions are forward biased by some means
*VFK (junction voltage), K=1, 2, ……..n

Hence, ∑ VFK = 0 ……………………….. (1)

Practically junctions here will usually represent Base-Emitter junctions of BJT :

* Hence, VFK = VBEK
* Collector current = ICK

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As, IC = IS exp(VBE/ VT),

Where VT = KT/q=thermal voltage

So, VBE = VT ln(IC / IS) …………….(2)

Eqn. (1) can be written as

K n I CK

¦VT ln 
K 1
I SK
0...............(3)

„ ISK : different for different junctions

„ : it includes the possibility of

* different area(junction)

* different type(NPN or PNP)

„ Assume VT equal for all the junctions.

„ Then equ.(3) becomes

K n I CK
= 0 = ln(1)
ln  
I SK
K 1

K n I CK
or, 
K 1
I SK
=1 ………………………………(4)

„ For any practical circuit IC/IS >>1

„ Hence to satisfy eqn.(4), conditions to be satisfied:

* Even number of junctions in a TL Loop

* Equal no. of CW & CCW facing junctions

„ Note that, if NPN & PNP junctions are mixed then:

* they should appear in “opposing pair”

* since there IS may have significantly different temp. coefficient

Let us assume:
* all the devices are SAME TYPE

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& * may have different Emitter Area(IS)
The eqn.(4) may be written as

I CK I CK

    ........................(5)
CW
I SK
CCW
I SK

• As IS ∞ Emitter area

• Hence it a good TL practice to represent Area of Emitter by unit of “e”, 2e, 3e………ne.

• Hence ISK=AK JSK

• Where, AK = Emitter Area

JSK = Saturation Current Density

I CK I CK
Eqn.(5) can be written as
 
CW
AK
CCW
AK

„ As ICK/AK=Emitter current density=J

„ Hence,

J J
CW CCW

STATEMENT OF TRANSLINEAR PRINCIPLE :

In a closed loop containing an even number of FORWARD biased junctions, arranged so that there
are an equal number of clockwise-facing(CW) and counter clockwise-facing(CCW) polarities. Then
the product of the current densities in the clockwise direction(CW) is equal to the product of
current densities(CCW) in the counter clockwise directions.

VECTOR DIFFERENCE CIRCUIT:

*Two TL Loops: Loop-1 & Loop-2

* Transistors Q2 & Q3 forms Current Mirror
* Hence, IC2 = IC3 ……………………………..(1)
* Applying TLP at Loop-2, we get,
IC4/2 x IC5/2 = IC1 IC2 ………………………...(2)
(CW) (CCW)

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Here,
IC2 = Iy + IC1 ………………………………(3)
& IC1 = Ix - IC3 = Ix - IC2 ……….…….......(4)
From (3) & (4)
IC2 = (Iy + Ix)/2 ………………………....(5)
From eqns.(4) & (5), we get
IC2 IC1= (Ix2 - Iy2 )/4

From eqn.(2) we get,

IC4 IC5 = Iw2 = 4 IC1 IC2 [since, IC4 = IC5 = Iw]

So, Iw= √ (Ix2 - Iy2 ) : Vector Difference

Limitations:

• Ix : Must be Uniploar

Iy :May be bipolar, but ȁ‫ܫ‬௒ ȁ ≤ ȁ‫ܫ‬௑ ȁ

DIODE BRIDGE :

Apply TLP:
(1-x)Ib[Ic+(1-x)Ib] [CW] = xIb(Ia+xIb)[CCW]

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Solving above eqn. we get,

x=(Ic+ Ib)/(Ia+2Ib +Ic)

Let, Ia=1ma
Ib=2ma
Ic=3ma

If correct then,

I1 I3 = I2 I4

Practically also found,

LHS=RHS

2.8125 ma2= 2.8125 ma2

Hence the result is correct

TL ONE QUADRANT SQUARER/DIVIDER :

* It can function as both:

* Squarer
* Divider
* Here output current =IW= IX2/ Iy
* One quadrant because both IX & Iy : Unipolar

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 I1 I 2 I3 I 4
I1 I2 Ix
I x2 I y Iw
I x2
Iw
Iy

ABSOLUTE VALUE CIRCUITS:

SQUARE ROOTING & GEOMETRIC MEAN:

IW= √ IX Iy

Square Root: One input is fixed

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 Geometric Mean: Both the inputs are variable

VECTOR MAGNITUDE CIRCUIT:

Iw= √ (Ix2 + Iy2 )

* If Ix=0, then Iw= √ Iy2 = ‫ ׀‬Iy‫׀‬
* Hence it can also function as ABSOLUTE VALUE CIRCUIT

CURRENT MODE FOUR QUADRANT CMOS ANALOG MULTIPLIER WITH LOW

POWER

ƒ What is Four Quadrant Analog Multiplier.

Signals VX and VY having any polarity

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ƒ Multiplier Circuit:

Fig.1 Proposed current-mode analog multiplier circuit

ƒ Output is:
‫ܫ‬ை௨௧ ൌ ‫ܫ‬ோ௜௚௛௧ െ ‫ܫ‬௅௘௙௧

ƒ Principle used  2 2
a b  a b 4ab

ƒ Uses two squarer & one subtractor (Cascode current mirror).

ƒ IX and IY input currents.

ƒ For MOS Transistor operated in saturation. 

‫ܫ‬஽ௌ ൌ ሺୋୗ െ ୲ ሻଶ (1)

ூ
ܸீௌ ൌ ܸ௧ ൅ ට ವೄ
௄
(2) 
‫ ܭ‬ൌ ͲǤͷߤ଴ ‫ܥ‬ை௑ ሺܹ Τ‫ܮ‬ሻ

ƒ Ileft & Iright are squared output of (IX - IY) & (IX + IY)

ƒ From loop A : ܸீௌସ ൅ ܸீௌହ ൌ ܸீௌ଺ ൅ ܸீௌ଻ (3)

Assume M4-M7 are biased in saturation and matched.

Then

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 IDS4 = IDS5 = IB

Hence, Using (2) & (3) :

ඥ‫ܫ‬஽ௌସ ൅ ඥ‫ܫ‬஽ௌହ ൌ  ඥ‫ܫ‬஽ௌ଺ ൅  ඥ‫ܫ‬஽ௌ଻  (4)

Fig.1 shows, 
‫ܫ‬஽ௌ଻ ൌ ‫ܫ‬஽ௌ଺ ൅ ሺ‫ܫ‬௑ െ ‫ܫ‬௒ ሻ

From (4) We get , ʹඥ‫ܫ‬஻ ൌ  ඥ‫ܫ‬஽ௌ଺ ൅  ඥ‫ܫ‬஽ௌ଻ 

ඥ‫ܫ‬஽ௌ଺ ൌ ʹඥ‫ܫ‬஻ െ  ඥ‫ܫ‬஽ௌ଻

‫ܫ‬஽ௌ଺ ൌ Ͷ‫ܫ‬஻  ൅ ‫ܫ‬஽ௌ଻ െ Ͷඥ‫ܫ‬஻ ‫ܫ‬஽ௌ଻ 

‫ܫ‬஽ௌ଻ െ ሺ‫ܫ‬௑ െ ‫ܫ‬௒ ሻ ൌ Ͷ‫ܫ‬஻ ൅ ‫ܫ‬஽ௌ଻ െ Ͷඥ‫ܫ‬஻ ‫ܫ‬஽ௌ଻

Ͷඥ‫ܫ‬஻ ‫ܫ‬஽ௌ଻ ൌ Ͷ‫ܫ‬஻ ൅ ሺ‫ܫ‬௑ െ ‫ܫ‬௒ ሻ

ሾͶ‫ܫ‬஻ ൅ ሺ‫ܫ‬௑ െ ‫ܫ‬௒ ሻሿଶ

‫ܫ‬஽ௌ଻ ൌ ሺͷሻ
ͳ͸‫ܫ‬஻

Similarly,

ሾସூಳ ିሺூ೉ ିூೊ ሻሿమ

‫ܫ‬஽ௌ଺ ൌ (6)
ଵ଺ூಳ

From Fig.1, We also find that, 

‫ܫ‬௅௘௙௧ ൌ ‫ܫ‬஽ௌ଺ ൅ ‫ܫ‬஽ௌ଻

ሺ‫ܫ‬௑ െ ‫ܫ‬௒ ሻଶ
ൌ ൅ ʹ‫ܫ‬஻ ሺ͹ሻ
ͺ‫ܫ‬஻

Similarly, 
‫ܫ‬ோ௜௚௛௧ ൌ ‫ܫ‬஽ௌଵଷ ൅ ‫ܫ‬஽ௌଵସ

ሺ‫ܫ‬௑ ൅ ‫ܫ‬௒ ሻଶ
ൌ ൅ ʹ‫ܫ‬஻ ሺͺሻ
ͺ‫ܫ‬஻

So, 
‫ܫ‬ை௨௧ ൌ ‫ܫ‬ோ௜௚௛௧ െ ‫ܫ‬௅௘௙௧

ࡵࢄ ࡵࢅ
ࡵࡻ࢛࢚ ൌ ሺͻሻ
૛ࡵ࡮

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 Observation:

ƒ It functions as multiplier.

ƒ It also functions as divider.

ƒ Insensitive to device parameters (K) & Vt .

ƒ Gain can be varied by IB.

Input Range :
ƒ Input range is restricted by saturation condition of all MOS transistors. (Loop A & Loop B).

ƒ Eqn. (6) is obtained by considering transistors of Loop A in saturation.

ʹඥ‫ܫ‬஻ ൒  ඥ‫ܫ‬஽ௌ଺ ൅  ඥ‫ܫ‬஽ௌ଻ (10)

Assume, IX - IY = X IB , putting it in eqn.(10). We get

ȁͶ‫ܫ‬஻ ൅ ܺ‫ܫ‬஻ ȁ  ൅  ȁͶ‫ܫ‬஻  െ ܺ‫ܫ‬஻ ȁ

ʹඥ‫ܫ‬஻   ൒   ሺͳͳሻ
Ͷඥ‫ܫ‬஻

Solution of inequality (11) gives ,

ȁܺȁ  ൑ Ͷ

Input range of the multiplier is

ȁ‫ܫ‬௑ െ ‫ܫ‬௒ ȁ  ൑ Ͷ‫ܫ‬஻

Similarly 
ȁ‫ܫ‬௑ ൅ ‫ܫ‬௒ ȁ ൑ Ͷ‫ܫ‬஻ ǡ ‫ܫ‬஻ ൐ Ͳ

So, it shows that any polarity of IX and IY is permitted. Hence it is FOUR- QUADRANT
MULTIPLIER. Here ,

ȁ‫ܫ‬௑ ȁ ൌ ȁ‫ܫ‬௒ ȁ  ൑ ʹ‫ܫ‬஻

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 Fig.2. Input range of the proposed multiplier for IB = 5μA

Fig.3. Simulated dc transfer characteristic for IB=5μA

Simulation Result :

Fig.4. The transient response of the proposed multiplier in 1MHz

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 Fig.5. Frequency response of the proposed multiplier

Fig.6. Relation between THD and the input signal IX

Current Mode Building Blocks

CURRENT CONVEYORS :
¾ Introduction.
¾ Classification of Current Conveyors.
¾ Other Current mode building blocks.
¾ Op-amp based Conveyor.
¾ Circuits & Principle of operation of CC.

INTRODUCTION :
What is Current Conveyor:
¾ It is normally three-five terminal circuit.
¾ When CC is used with other electronic elements, it can perform many useful Analog Signal
Processing Functions.

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