Fontys Enginering Quartus Manual R10 190911 Laz

Cyclone V number: 5CSEMA5F31C6
Fontys Engineering Quartus Prime manual
Latest version info:

Author : Lazaroms,Joachim J.M.
Version : R10 190829
Fontys Enginering Quartus manual R10 190911 laz.docx Page 1 of 55

Table of Content
1 Project (create/opening/editing) .................................................................................................... 4
1.1 Create an empty project .......................................................................................................... 4
1.2 Create a Simple project from scratch ...................................................................................... 9
1.2.1 Create a schematic view .................................................................................................. 9
1.2.2 Creating a symbol for a block form VHDL ..................................................................... 11
1.2.3 Using the generated symbol in a block/schematic file ................................................. 13
1.2.4 Generate/update the schematic file into a VHDL file. .................................................. 14
1.3 Create a More complex project from scratches .................................................................... 16
1.3.1 Creating a multi-block project ....................................................................................... 17
1.3.2 Create a new symbol from VHDL (and_block) .............................................................. 17
1.3.3 Create a new block from VHDL (or_block) .................................................................... 19
1.3.4 Create a new block from VHDL (sel_block) ................................................................... 19
1.4 Open an existing project ........................................................................................................ 22
1.5 Edit an existing project .......................................................................................................... 22
1.6 View the hardware result of your VHDL code (RTL viewer) .................................................. 25
2 Simulation...................................................................................................................................... 26
2.1 Create an expectation to compare your result ...................................................................... 26
2.2 Start the simulator ................................................................................................................. 27
2.3 Control the simulator/generate a simulation ........................................................................ 32
2.3.1 Add all the signals (you need them all for this tutorial) ................................................ 32
2.3.2 Change the height ......................................................................................................... 32
2.3.3 Change the order ........................................................................................................... 33
2.3.4 Adding dividers .............................................................................................................. 33
2.3.5 Prepare a DO file ........................................................................................................... 35
2.3.6 Execute the DO file ........................................................................................................ 36
2.4 Some tips to hand in your reports. ........................................................................................ 40
3 Use the board ................................................................................................................................ 41
3.1 Prepare your project for the board (assignment editor) ....................................................... 41
3.2 Uploading the SOF file (Soft programming) ........................................................................... 43
3.3 Creating a JIC file (for hard programming) ............................................................................ 48
3.4 Upload the JIC file(Hard Programming) ................................................................................. 49
4 Common error/mistakes ............................................................................................................... 50
4.1 VHDL....................................................................................................................................... 50
4.2 Schematic ............................................................................................................................... 50
4.3 ModelSim ............................................................................................................................... 50
Appendix A: Useful links/resources....................................................................................................... 51
Appendix B: VHDL syntax and examples: .............................................................................................. 52
Appendix C: VHDL Reserved Words ...................................................................................................... 54

Version history
Version Date Author Change
R01 28-06-2017 Joachim Lazaroms Creation of document
R02 12-07-2017 Tanushree Roy Adding chapter 1.1
R03 24-07-2017 Tanushree Roy Adapting to review 1 and adding chapters 1.2 and 1.3
R04 29-07-2017 Tanushree Roy Adapting to review 2 and adding chapter 1.4, 1.5 and 2
R05 09-08-2017 Joachim Lazaroms Ch 1 & 2 visual update. Error fix in VHDL template (end
process). Change ModelSim print steps. Added RTL viewer.
R06 15-08-2017 Tanushree Roy Adapting to reviews in over-all file and starting chapter 3
R07 23-08-2017 Joachim Lazaroms Finalize chapter 1 and 2. Make change to pin assignment
method. Adding links to appendix A: links
R08 26-08-2017 Tanushree Roy Changing time diagram and adding common mistakes
R09 28-08-2017 Joachim Lazaroms Final touch to all the content for publication
R10 11-09-2019 Meike Janssen, Updates pictures to Quartus 17, update picture that
Joachim Lazaroms everything is sourced from one project.
R11

1 Project (create/opening/editing)
1.1 Create an empty project
a) To start Altera Quartus Prime click on the Quartus Prime 17.0 icon or use Windows Start to
select Quartus Prime 17.0.
The result should look like the window below.

b) Use File New project Wizard (or click on the New Project Wizard icon) to create a new
project.
c) You now will get different windows. Do as in the demo below. The first window is the
Introduction window. Click here on Next.
d) In the next window select a directory and a name for your project and click Next.
For this and future projects make sure you apply a good file structure (see above), so files belonging
to a certain project are all within the right folder belonging to that project.
Follow the same rule for naming all assignments for all classes.
<sub code><semester><quarter>_<name of assignment><number of the assignment>_<small description>
Example: DD11_Ass1_projectname

e) In the Project Type window click on Next
f) In the Add Files window you can select and add files to your project. We start from the
scratch, hence just click on Next.

g) In the Family & Device Settings window choose for 5CSEMA5F31C6 and click next.
h) In the EDA Tool Settings window, you can add customary tools to the environment.
ModelSim-Altera is defined already. So, click next. (If not make sure it matches below)

i) In the Summary window, you will get a summary of your project. Click Finish.
j) Your final window will look like the one below:

1.2 Design a Simple project from scratch
Symbol:
and_block
Figure 1 simple project symbol
Function:
The above block returns a high when both the inputs are high. This operation is called AND.
Make sure you have created a project as described in 1.1 Create an empty project
1.2.1 Create a schematic view
a) To do this go to File and choose for New. A new window will appear.

b) In this New window choose Block Diagram/ Schematic File and click on OK.
c) This is how the empty block diagram/schematic file looks.
d) Click Save As, so this schematic file will have the name of the project.

1.2.2 Creating a symbol for a block form VHDL

a) Open a new VHDL file
b) Copy the VHDL template (from N@tschool) and adapt it to the your block. It should look like
this.
Entity name
c) Save your VHDL file and name it and_block.

The entity name and the name of your VHDL file should be the same, otherwise the software
will give you errors later.

d) Create a symbol from your code by following the steps below.
e) If the result look like this, especially check the yellow marks. Then yo know, it did whent well.

1.2.3 Using the generated symbol in a block/schematic file
a) Open the block/schematic file you already saved. Click on the SYMBOL TOOL.
b) Under project chose the and_block. And place it in the block/schematic file.
c) Click on the PIN TOOL to add the inputs and outputs. Remember to keep all inputs on the left
and outputs on the right.
After adding the appropriate input and output pins, your project should look like this.
Double click on pin_name to give it a custom name.

d) Use the NODE TOOL to connect the input and output pins to the block.
Your finished block should look like this.
Check your connections and save your block file.
1.2.4 Generate/update the schematic file into a VHDL file.

a) You need to now create a VHDL file for the complete schematic. Follow the steps below to
generate a VHDL file.

b) Now you need to do an ANALYSIS & SYNTHESIS. Click on either of the places as shown below
to run the check.
If you see any errors after this, you need to fix it before going any further.

1.3 Create a More complex project from scratches
Make sure you have created a project as described in 1.1 Create an empty project
We want to create a project according to the following design
Symbol:
Figure 2 Top level complex project (symbol)
Architecture:
Figure 3 a more complex project architecture
and_block:
This block generates a high on the output when both the input signals are high.
or_block:
This block generates a high on the output when either one of the input signals is high.
sel_block:
If the sel input is 0, then the output of the entire system is f_and. When sel input is 1 the output of
the entire system is f_or.

1.3.1 Creating a multi-block project
a) Create a block/schematic file. (1.2.1 Create a schematic view)

b) Save it as top-level entity, i.e., save the block schematic file with the same name as the
project.
c) Add the input/output pins. Your block/schematic file should look like this.
1.3.2 Create a new symbol from VHDL (and_block)

We have already created an AND block previously from VHDL.
a) Open a new VHDL file.
b) Copy the VHDL template (from N@tschool) and adapt it to the your block. It should look like
this.
c) Save your VHDL file and name it and_block. Don’t forget to check the Add file to current
project check box.
The entity name and the name of your VHDL file should be the same, otherwise the software
will give you errors later.

d) Create a symbol from your code like you have done before.
e) Add the symbol to your schematic. Connect all the relevant input and output pins.

1.3.3 Create a new block from VHDL (or_block)

a) Follow the same steps as above.
b) The code in your process should now look like this.
Remember to change the name of the ENTITYNAME and the name of the output. When
renaming the entity, do it in all three places to avoid errors.
c) Create a symbol and add it to your block file.

Remember to save the file before creating a symbol.
These are NODES. They show the

connection between two wires.
1.3.4 Create a new block from VHDL (sel_block)

c) Follow the same steps as before. Your entity and sensitivity list will look different now. With
the help of the syntax of IF statement from the appendix (Appendix B: VHDL syntax and
examples:).
Your VHDL file will look like this.
Note: It is important to use the else statement instead of typing again an if statement with :
if sel=’1’.

d) Save your VHDL file. Create a symbol and place it in the block file.
In architecture, internal lines always need to get a name. If not, you get annoying names
when simulating.
Right click on the node line, click on properties, and give it an appropriate name (as done in
the picture above).
e) Check your connections and then save your file.

f) VHDL file are already VHDL but a schematic file is not. The simulator only accepts VHDL.
Therefor you need to now create a VHDL file out of the complete schematic. Follow the steps
below to generate a VHDL file.
Now you need to do an ANALYSIS & SYNTHESIS. Click on either of the places as shown below
to run the check.

If you see any errors after this, you need to fix it before going any further.

1.4 Open an existing project

You can open an existing project in two ways.
(i) Go to the directory you saved it and then double-click on the .qpf (quartus prject file) file
to open the project.
(ii)
a) Open Quartus Prime
b) Click on Open Project.

c) Finding your project is easy because you made a good file structure. Once you find
your project you can open it.
1.5 Edit an existing project
We want to add an assign_block to our previous project.
assign_block:
Depending on the sel, the block assigns f to f0(when sel is 0) and f to f1(when sel is 1).
What should f0 be when sel = 1. As future engineer, you should see this quickly. Normally you should
give a suggestion, but for now we define the output value to be '0' when not defined.
The new architecture:

To do this follow the steps below.
a) Open your existing project.

b) Double click the circled part.
c) Open a new VHDL file and follow the same steps as before. Your entity and sensitivity list
will be different now. With the help of the syntax of IF statement from the appendix
(Appendix B: VHDL syntax and examples:). Also the content of the process part is
different comping to other blocks.
Your VHDL file will look like this.

d) Save the VHDL file and create a new symbol.
e) Place the new symbol in the block file and connect the appropriate inputs and outputs.
Note: When the schematic change, you have to update the VHDL file of the schematic file.
f) Create a new VHDL file for the complete schematic.

Remember to this this every time for every change in the schematic.
g) Save your block file and run an Analysis & Synthesis check after checking all your
connections.

1.6 View the hardware result of your VHDL code (RTL viewer)
h) To see if your made a mess or not, copy a picture of the generaded result in your report.
Open RTL viewer
i) This should be your result, just simple blocks
Remember, simple result is normally good. Big spaghetti should be coded better!

2 Simulation
2.1 Create an expectation to compare your result
a) Draw your own outcome as expected to compare later.

2.2 Start the simulator

(Definition RTL will be explained in DD21)
a) Compile your design (if not done yet). You can chose either way.
This might take a while. So be patient.
b) Then follow the steps below to open the simulation tool. Possible error is explained next.
c) When you get an error like this, then go to: toolsoptionsEDA Tool OptionsModelsim-
Altera and select the folder win32aloem. You find the map in
intelFGA_lite\17.0\modelsim_ase\win32aloem.

d) This is how the simulation tool, ModelSim, could look when it starts. (We know that it could
look like a mess.)
e) Click on Compile and then compile... (again)

f) This window opens. Click on the circled twice to go up a folder. You will then see all the VHDL
files you wrote.
g) Select all your used VHDL files and click compile. Then click Done. (if you compile more then
use, it can result in bad simulation results). In our example project it is every VHDL file that is
listed below.

2
3
h) Check for error in the transcript log before you start a simulation.
For every complied file you get a new result. Make sure you scroll back for any errors.
i) Open the Simulate menu en click Start simulation ...

j) You can see that the list in WORK is the same as in Quatus. Select your top level file, change
Resolution too ns, and click OK:
k) You will see all your signals (internal and external) in the object window.

2.3 Control the simulator/generate a simulation

2.3.1 Add all the signals (you need them all for this tutorial)
a) Select all the signals.
b) Right click on them and then select ADD WAVE.
c) You will se that your signals have been added in the wave window.
2.3.2 Change the height

For a neater and easier to read simulation, we adjust the height of the waves.
a) Select all the signals.
b) Go to format->height
OR
c) Set the height to 30.

2.3.3 Change the order

a) Drag and move the signals in an order you desire, i.e., which is easy to understand.
b) Here the inputs are in the beginning and the outputs are in the end. Sel has been placed
afterwards because after the generation of f_and and f_or, the sel_block is used. After f is
generated from the sel_block, f0 and f1 and generated by the assign_block. Refer to the
architecture to understand the order of the system.
2.3.4 Adding dividers
Dividers can be used to make things clear.
These are dividers.

a) To add these, right click on the signal list. Go to ADD and select NEW DIVIDER.
b) Give your divider a suitable name and click OK. (keep the height to 17 for diverders)

2.3.5 Prepare a DO file

The DO files are instruction for the input waves. They tell them if they are high or low and for how
long.
a) To create a DO file. Open notepad. (Even better, notepad++ or Sublime text)
b) Retype the text below into your text editor. Complete the file. Make sure all combinations
are tested. (not everything is listed yet)
This is the header, you and

use this space to describe the
function of your do file.
Use # in the beginning of any

line to make it a comment.
Once you force a signal then

that runs till you change it.
Run tells the signal for how

long it should run. Here it
runs for 50 ns because we
start the simulator in ns
mode.
Use this document to get a look to all the command:
https://www.microsemi.com/document-portal/doc_view/136364-modelsim-me-10-4c-
command-reference-manual-for-libero-soc-v11-7#G8.3776057
p.170 & 239.
c) Save the notepad file with a .do extension. Don’t forget to change the SAVE AS TYPE to All
Files. Otherwise, you will have a text file saved as DD11_Ass11_2_DOfile.do.txt.
Use the projectlocation/simulation folder to save the file.

2.3.6 Execute the DO file

a) Go back to your wave window. Click on File and select LOAD. (When you are in the MAIN
widow, you have to click on: File Load..  Marco File)
b) Go up one level and select the DO file you created.
c) After this you will see the waves being generated.

d) Click on ZOOM In on active Cursor or press C on your keyboard, to zoom in. Or click on
ZOOM FULL or press F on your keyboard.

e) This is your outcome.
f) Print the file to PDF so you can upload it to FONTYS-WEBPRINT.

We use PDFCreator (Appendix A: Useful links/resources). Or use the PDF printer from Windows.

g) Upload the pdf to FONTYS-WEBPRINT and add comments on the paper.

It is also possible to install a printer driver to skip the website (recommended)
There is 1% chance that someone lost a file. Therefore YOU SHOULD scan this ModelSim plot with
comments when you are done. (for backup)
If the teacher lost the file and you can’t hand-in a new file, you get insufficient.

Add comments. You need to highlight parts in your simulation and then explain them. Compare your result (down here) with your expectation (p26). If you see
any differences, write down the reason in your comments. (Wrong can be right)

2.4 Some tips to hand in your reports.

1. Create a new document.
2. Write your name, class and assignment number in the header.
3. Always draw a block diagram and architecture before starting the project to ensure that you
have understood the assignment. (Verify the result with the teacher)
4. Use https://g2384.github.io/VHDLFormatter/ to (re)indent the code to look neat. Copy the
result back in your project. Use the following settings: (or use sublime with VHDL plugin)
5. Use http://hilite.me/ to make your VHDL code look formatted when you paste it in word.
6. A simulation without comments is counted as no simulation.
7. Always make a copy of the work you hand in(tip). Sometimes teachers can lose their data.
8. Hand in a hard copy unless or otherwise stated.
9. Hand in your report within the deadline.

3 Use the board

After the completion of a successful compilation (step 1.2.4.b)), follow the steps below.
3.1 Prepare your project for the board (assignment editor)
a) Make sure your project is Analysed
b) Go to Assignments  Assignment Editor
c) This is how your window should look now.
d) Double click the green text New in the column TO. Click on the glasses to search for
available IO.

e) Find the IO by clicking on LIST.
f) Select all the IO (not the internal signals) and click COPY. Then click OK.
NOTE: if the list is empty, the project was not (successfully) compiled (1.2.4.b)).

g) In the Assignment Name column chose Location (Accepts wildcards/groups). Tip:
select this one time, then use CTRL-C to copy the value. Select all the other cells in that
column en use CTRL-V to past the same setting there.
In Value column, add the label that is listed in the DE1-Soc IO-List.pdf (N@Tschool DD1
3 practical)
i. For inputs, this example uses switches/push buttons
ii. For outputs, this example uses LEDs
h) Your assignment editor should look like this.
NOTE: if you have an uncompleted pin assignment, it will break the board. This is solvable but is
risky. Ask the teacher for the. If you mess up this step it is broken for every!!!!!!!!!!
i) After assigning each pin to a location, close this windows and go back to the main window of
Quartus Prime. Compile your entire project.
j) Once the Assembler is done, a .SOF file is created in the folder ‘output_files’. Check the
timestamp of the SOF file.
3.2 Uploading the SOF file (Soft programming)

After you have assigned right pins to the I/O, you have to upload your program to the board.
To do this we upload a .SOF file to the board. This file is automatically generated by the
software after a successful compilation.
Make sure the tiny MSEL pins on the back of the board are set to MSEL[4..0] = “10010”. This is
crucial.

a) Now connect your board to your computer, go to Tools in the top menu and select Programmer.

b) Click on Hardware Setup (top left) and under ‘Currently selected hardware’ select your board
(DE1-SoC).
If your board is not found, you haven’t installed the drivers yet. To do this, go to your
quartus install location en open the folder drivers (C:\intelFPGA_lite\17.0\quartus\drivers)
and run the application to install the drivers. After this your board should be
found.
If not: Open Device manager and manual install the DE1 bord.
http://www.computerhope.com/issues/ch000833.htm
c) Select DE-SoC and click Close. (there is no apply button)

d) Click on Auto e) Chose 5CSEMA5.
Detect
f) Right click at the circled spot (left from label 5CSEMA5 AND not on the position of the HPS)
g) Click on output files and select the .SOF file.

h) Check the Program/ Configure check box and click on start.
i) You can see the Progress bar on the top right to see when the .SOF file has been successfully
uploaded less than 15 seconds.

3.3 Creating a JIC file (for hard programming)

If you want to hard program your project there are a few extra steps. Hard-programming will
store the program in a separate chip (SDRAM). We have to generate a new file data write data
to another chip. Lucky there is a tool for that.
a) We need to generate a .JIC file from the .SOF file. Go to File and select Convert Programming
Files.
b) Now select JTAG Indirect Configuration File (.JIC) form the dropdown menu ‘Programming
file type’, set the Configuration device to EPCS128 and select a name and folder where you
want to save your file. Like the picture blow:
c) Now click Flash Loader in the lower window and click Add Device on the right.
d) Select Cyclone V and 5CSEMA5 and hit OK.

e) Now click SOF Data, click Add File on the right and select your .SOF file. This file is located in
the folder ‘output_files’. Click generate and your JIC file is created.
3.4 Upload the JIC file(Hard Programming)
Open the programmer and set up your device like you did before(3.2). Now follow the steps below.
a) Now connect your board, and aging make sure to set MSEL[4..0] to “10010” and go to the
programmer. Do the same as you did while Soft Programming, only select the newly
generated .JIC file instead. Your final window should look like this:
b) Click start. Your board will display some strange signs on the seven segment displays. Also
Hard programming your board takes a lot longer (up to 5 min). This is all normal. When the
progress bar is at 100% and this happens a few times, it is completely done. Disconnect
power to your board and reapply it (reboot it). Your program should load in and you should
be able to use it without a USB connection.

4 Common error/mistakes
4.1 VHDL
1. Error (10500): VHDL syntax error at addslice.vhd(35) near text "f"; expecting ";"
Syntax error. Probably forgotten to add a Semicolon (;) in the previous line.
Always look in the line above and compare it with Fout! Verwijzingsbron niet gevonden.
2. Error (10500): VHDL syntax error at addslice.vhd(31) near text "="; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at addslice.vhd(31) near text "after"; expecting ";"
Error (10526): VHDL Signal Assignment Statement error at addslice.vhd(31): Signal
Assignment Statement must use <= to assign value to signal "d"
The = symbol is used in the IF statement. You need a <= symbol to assign a value to a
signal. In case of a variable you need a := symbol.
3. Error (10500): VHDL syntax error at addslice.vhd(16) near text ")"; expecting an identifier, or
"constant", or "file", or "signal", or "variable"
In the ENTITY part there is a PORT() description. All the ports a separated by a Semicolon
(;). You also added a Semicolon (;) after the last I/O. that’s is wrong. A separator is nog a
closing symbol.
4. Error (10327): VHDL error at addslice.vhd(49): can't determine definition of operator ""-"" --
found 0 possible definitions
VHDL don’t know what to do with math operator. There is a library for that. Include this on
the top of your VHDL file, next to the others: use ieee.std_logic_signed.all;
5.
4.2 Schematic
1. Warning (275002): No superset bus at connection
You forgot the yellow marked part or you connected 2 different NetNames to each other.
2. Warning (275011): Block or symbol "ADDSLICE" of instance "inst" overlaps another block or
symbol
Move the existing block to find which one is overlapping. An in or output could also overlap.
3. Error (275046): Illegal name "a3" -- pin name already exists

There is a duplicate in I/O names. Typo?
4. Error (275062): Logic function of type GND and instance "inst" is already defined as a signal
name or another logic function
This is hard to recognize. The problem is that Quartus was too stupid to give them a
different instance name. Use the right button of the mouse on the GND symbol and click
properties. There you can see there is an instance name and it is identical to another block.
Simple give it a unique name and you’re done.
4.3 ModelSim
1. Tbd

Appendix A: Useful links/resources

Description Source
N@TSCHOOL Always check the DigitalDesign page on Fontys
N@Tschool for assignments, pin-numbers and
more
Board description, datasheet and more http://de1-soc.terasic.com
VHDL examples website (for reference only) http://esd.cs.ucr.edu/labs/tutorial/#gates
VHDL summery (for reference only) https://www.csee.umbc.edu/portal/help/VHDL/su
mmary.html
VHDL examples book (for reference only) http://freerangefactory.org/books_tuts.html
VHDL examples book (for reference only) Search the internet for “Digital Design by Mano”
VHDL examples book (for reference only) Search the internet for “Digital System Design with
VHDL 2e”
VHDL examples book (for reference only On N@Tschool: VHDL programming by example
VHDL examples book (for reference only On N@Tschool: accolade VHDL ref
To neat up your coding https://g2384.github.io/VHDLFormatter/
To copy your VHDL code into report, use this http://hilite.me/  manual select VHDL
webpage to get the colours.
PDF/PNG/JPG Printer https://sourceforge.net/projects/pdfcreator/
DOfile tips https://www.microsemi.com/document-
portal/doc_view/136364-modelsim-me-10-4c-
command-reference-manual-for-libero-soc-v11-
7#G8.3776057
Question bank http://www.indiabix.com/digital-
electronics/questions-and-answers/
Practice tests http://www.indiabix.com/online-test/digital-
electronics-test/
Alternative VHDL simulator http://www.esng.dibe.unige.it/deeds/

Appendix B: VHDL syntax and examples:

1. Comment starts with --
2. Logical operators: AND, OR, NAND, NOR, NOT, XOR
3. Relational operators : =, /=, <, <=, >, >=
4. Mathematical operators: +, -, &, **, *, / (where & is concatenation and ** to the power )
5. Data types:
Data type Example (definitions) Example usage
Bit Variable p : bit; p:='0';
Bit_vector Signal k : bit_vector(3 downto 0); k <= "0101";
Std_logic Signal z : std_logic; z <= '1';
Std_logic_vector Signal temp : std_logic_vector(3 temp <= "1011";
downto 0);
Integer Variable t : integer; t:=20;
Character Variable y : character; y := 'A'
String Signal name : string(1 to 4); name <= "Piet";
6. Statements
Statement Example
Variable assignment P := k;
Signal assignment A(6 downto 0) <= NOT B(11 downto 4);
A <= X XOR Y;
CASE expression IS
WHEN choice 1 => sequential Case sel is
statements; When "00" => a <= b+c;
WHEN choice 2 => sequential When "01" => k <= t AND y;
statements; When "11" => temp := 12;
: When others => z = "Jan";
: End case;
WHEN OTHERS =>
sequential statements;
END CASE;
if boolean_expr_1 then if (a='1' and b='1') or c='1' then

sequential statements; z <= '1' after 10 ns;
elsif boolean_expr_2 then elsif (a='0' or b='0') and c='0' then
sequential statements; z <= '0' after 12 ns;
elsif boolean_expr_3 then else
sequential statements; z <= 'X' after 5 ns;
……………….. end if;
else
sequential statements;
end if;
Concatenation operator & Variable c: std_logic_vector(3 downto 0);

A:= "01"; B:= "11" C:= A&B;
After this the value of C will be "0111"
process( ) Process (a, b)
-- variable declarations Begin
begin F <= a XOR b;
-- sequential statements End process;
end process;

NEXT information is used starting from DD3
Concurrent Statement Example

Selective signal assignment
with <expression> select with mySig select
<target> <= {<expression> when <choices>}; Z <= A when 15,
B when 22,
C when 28;
Conditional signal assignment
<target> <= {<expression> when <condition> Z <= A when (x > 3) else

else} <expression>; B when (x < 3) else
C;
Signal assignment
<target> <= {<expression> }; Sum <= A XOR B;
procedure identifier procedure AssigntoA(

[ ( formal parameter list ) ] is signal A: INOUT string(1 to 11)) is
[ declarations ]
begin begin
sequential statement(s); A<= “TekinYILMAZ”;
end procedure identifier ; end procedure;
function identifier [ ( formal parameter list ) ] function random

return a_type is return float is
[ declarations] variable X : float;
begin begin
sequential statement(s) X:=2.5;
return some_value; return X;
end function identifier ; end function;

Appendix C: VHDL Reserved Words

WORDS YOUR SHOULD NEVER USE AS ENITY NAME, SIGNAL NAME, and more.
abs operator, absolute value of right operand. No () needed.

access used to define an access type, pointer
after specifies a time after NOW
alias create another name for an existing identifier
all dereferences what precedes the .all
and operator, logical "and" of left and right operands
architecture a secondary design unit
array used to define an array, vector or matrix
assert used to have a program check on itself
attribute used to declare attribute functions
begin start of a begin end pair
block start of a block structure
body designates a procedure body rather than declaration
buffer a mode of a signal, holds a value
bus a mode of a signal, can have multiple drivers
case part of a case statement
component starts the definition of a component
configuration a primary design unit
constant declares an identifier to be read only
disconnect signal driver condition
downto middle of a range 31 downto 0
else part of "if" statement, if cond then ... else ... end if;
elsif part of "if" statement, if cond then ... elsif cond ...
end part of many statements, may be followed by word and id
entity a primary design unit
exit sequential statement, used in loops
file used to declare a file type
for start of a for type loop statement
function starts declaration and body of a function
generate make copies, possibly using a parameter
generic introduces generic part of a declaration
group collection of types that can get an attribute
guarded causes a wait until a signal changes from False to True
if used in "if" statements
impure an impure function is assumed to have side effects
in indicates a parameter in only input, not changed
inertial signal characteristic, holds a value
inout indicates a parameter is used and computed in and out
is used as a connective in various statements
label used in attribute statement as entity specification
library context clause, designates a simple library name
linkage a mode for a port, used like buffer and inout
literal used in attribute statement as entity specification
loop sequential statement, loop ... end loop;
map used to map actual parameters, as in port map
mod operator, left operand modulo right operand
nand operator, "nand" of left and right operands
new allocates memory and returns access pointer
next sequential statement, used in loops
nor operator, "nor" of left and right operands
not operator, complement of right operand
null sequential statement and a value
of used in type declarations, of Real ;
on used as a connective in various statements
open initial file characteristic
or operator, logical "or" of left and right operands
others fill in missing, possibly all, data
out indicates a parameter is computed and output
package a design unit, also package body

port interface definition, also port map
postponed make process wait for all non postponed process to suspend
procedure typical programming procedure
process sequential or concurrent code to be executed
pure a pure function may not have side effects
range used in type definitions, range 1 to 10;
record used to define a new record type
register signal parameter modifier
reject clause in delay mechanism, followed be a time
rem operator, remainder of left operand divided by right op
report statement and clause in assert statement, string output
return statement in procedure or function
rol operator, left operand rotated left by right operand
ror operator, left operand rotated right by right operand
select used in selected signal assignment statement
severity used in assertion and reporting, followed by a severity
signal declaration that an object is a signal
shared used to declare shared objects
sla operator, left operand shifted left arithmetic by right op
sll operator, left operand shifted left logical by right op
sra operator, left operand shifted right arithmetic by right
srl operator, left operand shifted right logical by right op
subtype declaration to restrict an existing type
then part of if condition then ...
to middle of a range 1 to 10
transport signal characteristic
type declaration to create a new type
unaffected used in signal waveform
units used to define new types of units
until used in wait statement
use make a package available to this design unit
variable declaration that an object is a variable
wait sequential statement, also used in case statement
when used for choices in case and other statements
while kind of loop statement
with used in selected signal assignment statement
xnor operator, exclusive "nor" of left and right operands
xor operator, exclusive "or" of left and right operands
source: https://www.csee.umbc.edu/portal/help/VHDL/

Fontys Enginering Quartus Manual R10 190911 Laz

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Cyclone V number: 5CSEMA5F31C6

Fontys Engineering Quartus Prime manual

Latest version info:

Fontys Enginering Quartus manual R10 190911 laz.docx Page 1 of 55

Fontys Enginering Quartus manual R10 190911 laz.docx Page 2 of 55

Version Date Author Change

R01 28-06-2017 Joachim Lazaroms Creation of document

R02 12-07-2017 Tanushree Roy Adding chapter 1.1

Fontys Enginering Quartus manual R10 190911 laz.docx Page 3 of 55

The result should look like the window below.

Fontys Enginering Quartus manual R10 190911 laz.docx Page 4 of 55

Fontys Enginering Quartus manual R10 190911 laz.docx Page 5 of 55

e) In the Project Type window click on Next

Fontys Enginering Quartus manual R10 190911 laz.docx Page 6 of 55

Fontys Enginering Quartus manual R10 190911 laz.docx Page 7 of 55

j) Your final window will look like the one below:

Fontys Enginering Quartus manual R10 190911 laz.docx Page 8 of 55

1.2 Design a Simple project from scratch

Figure 1 simple project symbol

1.2.1 Create a schematic view

Fontys Enginering Quartus manual R10 190911 laz.docx Page 9 of 55

c) This is how the empty block diagram/schematic file looks.

Fontys Enginering Quartus manual R10 190911 laz.docx Page 10 of 55

1.2.2 Creating a symbol for a block form VHDL

c) Save your VHDL file and name it and_block.

Fontys Enginering Quartus manual R10 190911 laz.docx Page 11 of 55

Fontys Enginering Quartus manual R10 190911 laz.docx Page 12 of 55

1.2.3 Using the generated symbol in a block/schematic file

Double click on pin_name to give it a custom name.

Fontys Enginering Quartus manual R10 190911 laz.docx Page 13 of 55

Your finished block should look like this.

Check your connections and save your block file.

1.2.4 Generate/update the schematic file into a VHDL file.

Fontys Enginering Quartus manual R10 190911 laz.docx Page 14 of 55

Fontys Enginering Quartus manual R10 190911 laz.docx Page 15 of 55

1.3 Create a More complex project from scratches

We want to create a project according to the following design

Figure 2 Top level complex project (symbol)

Figure 3 a more complex project architecture

Fontys Enginering Quartus manual R10 190911 laz.docx Page 16 of 55

1.3.1 Creating a multi-block project

a) Create a block/schematic file. (1.2.1 Create a schematic view)

1.3.2 Create a new symbol from VHDL (and_block)

Fontys Enginering Quartus manual R10 190911 laz.docx Page 17 of 55

Fontys Enginering Quartus manual R10 190911 laz.docx Page 18 of 55

1.3.3 Create a new block from VHDL (or_block)

c) Create a symbol and add it to your block file.

These are NODES. They show the

1.3.4 Create a new block from VHDL (sel_block)

Your VHDL file will look like this.

Fontys Enginering Quartus manual R10 190911 laz.docx Page 19 of 55

e) Check your connections and then save your file.

Fontys Enginering Quartus manual R10 190911 laz.docx Page 20 of 55

Fontys Enginering Quartus manual R10 190911 laz.docx Page 21 of 55

1.4 Open an existing project

b) Click on Open Project.

1.5 Edit an existing project

We want to add an assign_block to our previous project.

The new architecture:

Fontys Enginering Quartus manual R10 190911 laz.docx Page 22 of 55

To do this follow the steps below.

a) Open your existing project.

Your VHDL file will look like this.