G H PATEL COLLEGE OF ENGINEERING & TECHNOLOGY

(A Constituent College of CVM University)

Vallabh Vidyanagar – 388 120
Department of Electronics and Communication Engineering

AY 2023-2024 (Semester: 8)
Industrial Internship (102000801)
Student Name Tanish Shah
Enrollment Number 12002060501028
Contact Number 8866457001
Mail ID tanishshah@scaledge.io

Company Name SCALEDGE TECHNOLOGY

Company Website scaledge.io
Project / Area / Domain of
VLSI
Internship
Industry Mentor Name Milin Parekh
Contact Number 9033846345
Mail ID milin.p@scaledge.io
Internship Joining Date 02/01/2024

Brief Profile of
Company Headquartered in Silicon Valley, California, Scaledge has development centers in Canada,
the United Kingdom, and India. Since its inception, Scaledge's robust team of specialists
have been assisting customers in bringing advanced products to markets quickly and
efficiently.
We specialize in developing integrated hardware and software solutions that support the
semiconductor, AI/ML, and IoT industries across many domains such as consumer
durables, storage, automotive, wireless, and data center.
Our competence in VLSI across processors, SoCs, and sub-systems, and our maturity in
providing solutions in AI/ML and embedded software, distinguishes us as a "Partner of
Choice" for our customers.
Our vision is to be the world’s best Technology Design Center by being the first choice for
leading companies who want to build innovative products, and being the top choice for
talents who want to steer their successful journey for knowledge and growth.

12002060501028 1
 INTERNSHIP DAILY RECORD
Sr. No. Date Day Work Done Total Hours
Topics: code coverage, generating
04-03-2024 coverage in questa sim, test cases
09:48 AM to 7:13 PM
1 Monday examples at alpha numero.
(9 hours 25 minutes)
Code coverage of the vending machine.
Syncronous FIFO implementation
Tried to get 100% coverage in FSM code
of COIN
Designed SIPO,PIPO shift resgisters and
9:55 AM to 07:11 PM
2 05-03-2024 Tuesday verified the same
(9 hours 16 minutes)
Force and release Signal strength
Reason for code coverage gap Assign
and deassign
CookBook digital components coverage,
10:11 AM to 7:08 PM
3 06-03-2024 Wednesday Skew timing, Sample timing, related
(8 hours 55 minutes)
coverages.
Timer implementation in FSM Design. 9:55 AM to 7:16 PM
4 07-03-2024 Thursday
$test$plusargs, $value$plusargs. (9 hours 21 minutes)
Regression scripting 9:26 AM to 6:48 PM
5 08-03-2024 Friday
Makefile. (9 hours 22 minutes)
6 09-03-2024 Saturday WEEK OFF N/A
Using IC79 print the numeric values on 7 9:00 AM to 6:00 PM
7 10-03-2024 Sunday
segment display with company name. (9 hours)
Compilation -> elaboration ->
9:42 AM to 7:20 PM
8 11-03-2024 Monday simulation
(9 hours 38 minutes)
Discussion on Common synthesis issues
Worked on Mini Project Asynchronous
9:48 AM to 7:17 PM
9 12-03-2024 Tuesday FIFO. Solved synchronization bugs
(9 hours 28 minutes)
regarding read and write pointers
FPGA, ASIC, SOC
Difference between IP and VIP
(Verification).
SOC subsystems, Block level, top level 9:55 AM to 6:37 PM
10 13-03-2024 Wednesday
exhaustive verification (8 hours 41 minutes)
Worked on Mini Project Asynchronous
FIFO. Developed Testbench environment
for AsyncFIFO RTL
Finalized Asynchronous FIFO
verification. 9:46 AM to 6:47 PM
11 14-03-2024 Thursday
Revised Verilog Topics for Assessment (9 hours 1 minutes)
test.
12 15-03-2024 Friday Discussion on Asynchronous FIFO, why, 9:23 AM to 8:30 PM
how and when we need it. (11 hours 7 minutes)
Discussion on Round Robin Arbiter, why
and when we need it. And how to decide
priority mechanism.

12002060501028 2
 Revised Verilog topics for Practical
Assessment Test.
13 16-03-2024 Saturday WEEK OFF N/A
Using key to change the timer and 9:20 AM to 6:15 PM
14 17-03-2024 Sunday counter and check the o/p on display. (8:55 hours)
Today's Lecture Discussed topics:
Evolution of System Verilog from Verilog 09:48 AM to 7:13 PM
15 18-03-2024 Monday
Program block in system verilog. (9 hours 25 minutes)
Glimpse of System verilog Event queue.
Lecture session on System Verilog
Datatypes: 9:55 AM to 07:11 PM
16 19-03-2024 Tuesday
Logic, Struct, enum (9 hours 16 minutes)
Printing Properties
Review of AsyncFIFO and
10:11 AM to 7:08 PM
17 20-03-2024 Wednesday RoundRobinArbiter got done with Harsh
(8 hours 55 minutes)
Bhai. Mini project Closure done.
Operators: Arithmetic Operators,
Relational Operators, Logical Operators,
9:55 AM to 7:16 PM
18 21-03-2024 Thursday Bitwise Operators, Shift Operators,
(9 hours 21 minutes)
Replication Operator & concatenation
operator.
Ternary operator, Static casting.
Streaming Operator {<<}; 9:26 AM to 6:48 PM
19 22-03-2024 Friday
Enhancement in Task and Functions. (9 hours 22 minutes)
Return keyword in task and function.
20 23-03-2024 Saturday
WEEK OFF N/A
21 24-03-2024 Sunday
N/A
22 25-03-2024 Monday ----------------------HOLI-----------------------
Practice on System verilog datatypes, 09:48 AM to 7:13 PM
23 26-03-2024 Tuesday operators, methods, functions and tasks (9 hours 25 minutes)
Arrays and it's types, i.e. static type and
dynamic type

1D and 2D array Packed and Unpacked

array Dynamic array and its built-in
methods Associative array and its built-
in methods
9:55 AM to 07:11 PM
24 27-03-2024 Wednesday
(9 hours 16 minutes)
Queues (Bounded and Unbounded) and
its built-in methods

Array manipulation methods such as

find(), find_index() with(expression),
min(), max(), unique(), unique_index(),
sort(), rsort(), shuffle()

12002060501028 3
  Introduction to OOPs
 Class and Object, its constructor
new( )
 Learned how class handles are
10:11 AM to 7:08 PM
25 28-03-2024 Thursday created
(8 hours 55 minutes)
 Function local variable scope
 Discussion on Package block
 Use of this keyword

Learnt about queue array and tried 9:55 AM to 7:16 PM

26 29-03-2024 Friday example for the same. (9 hours 21 minutes)

27 30-03-2024 Saturday
WEEK OFF N/A
28 31-03-2024 Sunday
 Discussion on given assignment
questions.
 Constructor new( ) : in classes to
declare handle as object 09:48 AM to 7:13 PM
29 01-04-2024 Monday
 Object assignment (9 hours 25 minutes)
 Copying an object
 Static method and properties

 Worked on the Master of SPI

Protocol.
 Trying to figure out that how to 9:55 AM to 07:11 PM
30 02-04-2024 Tuesday
give value to SCLK signal in when (9 hours 16 minutes)
defining as SLAVE.

 Encapsulation local and

protected member and
properties.
 Inheritance
 Super keyword 10:11 AM to 7:08 PM
31 03-04-2024 Wednesday
 Difference between local and (8 hours 55 minutes)
protected methods and
properties during inheritance
from parent class to child class.

 Discussed previous assignment

questions.
 Polymorphism
9:55 AM to 7:16 PM
32 04-04-2024 Thursday  Use of virtual keyword in
(9 hours 21 minutes)
methods.
 Abstraction class (virtual class).

33 05-04-2024 Friday  Encapsulation local and 9:26 AM to 6:48 PM

protected member and (9 hours 22 minutes)
properties.
 Inheritance
 Super keyword
12002060501028 4
  Difference between local and
protected methods and
properties during inheritance
from parent class to child class

34 06-04-2024 Saturday
WEEK OFF N/A
35 07-04-2024 Sunday
 Parameterized class
 Global constant
 Singleton class
 Upcasting
 Limitation of shallow copy and
09:48 AM to 7:13 PM
36 08-04-2024 Monday solution deep copy
(9 hours 25 minutes)
 Static keyword after
task/function keyword
 Nested class
 Extern keyword use

 Eand and randc keyword

 Randomize() method for class
variables
 Rand_mode(0) : to off
9:55 AM to 07:11 PM
37 09-04-2024 Tuesday randomize() method
(9 hours 16 minutes)
 Rand_mode(1) : to on
randomize() method
 Constraint overview

1. Topics covered in session:

 Constraints
 Implicit and Explicit constraint
 Inside and Invert inside
constraint
 Implication ,foreach and weight
distribution constraint
 Operators in constraint
10:11 AM to 7:08 PM
38 10-04-2024 Wednesday  Types of Constraint :
(8 hours 55 minutes)
1. Bi-directional constraint
2. Inline constraint
3. Disable Constraint
4. Soft Constraint
5. Solve before
 Deep copy
 Array Slicing

39 11-04-2024 Thursday 9:55 AM to 7:16 PM

(9 hours 21 minutes)
 Severities : $info , $warning ,

12002060501028 5
 $error ,$fatal
 $sformatf : converts string with
number to string
 SV testbench environment
transaction level activity
overview

 Queue vs. Mailbox

 Mailbox
 Methods in Mailbox : blocking,
non-blocking methods and num
9:26 AM to 6:48 PM
40 12-04-2024 Friday method
(9 hours 22 minutes)
 Pre and post randomization Seed
in systemverilog

41 13-04-2024 Saturday
WEEK OFF N/A
42 14-04-2024 Sunday
1. Topics covered in session:
1. Mailbox Transaction level
functionality
2. How mailbox is used for
communication between
verification components 09:48 AM to 7:13 PM
43 15-04-2024 Monday
3. Optimized way to connect (9 hours 25 minutes)
to mailbox of driver and
generator classes.
4. Static mailbox
2. Practice on mailbox. {Randc
behaviour}
1. Types of Fork join
1. join_any
2. join_none
2. Fork join practice example code
9:55 AM to 07:11 PM
44 16-04-2024 Tuesday 3. Forward class declaration :
(9 hours 16 minutes)
typedef class
4. `ifndef and `endif : To avoid
multiple compilation
5. Final block
1. Topics Covered in session:
1. Interface Block
10:11 AM to 7:08 PM
45 17-04-2024 Wednesday 2. Clocking Block
(8 hours 55 minutes)
2. Made small module based
verification testbench for DFF.
46 18-04-2024 Thursday Topics Covered in sesion: 9:55 AM to 7:16 PM
1. Building Simulation Verification (9 hours 21 minutes)
Testbench
2. Components of Verification

12002060501028 6
 testbench
3. TB architecture
1. Solved constraint question of
magic square and two pointer
9:26 AM to 6:48 PM
47 19-04-2024 Friday array question.
(9 hours 22 minutes)
2. Made small module based
verification testbench for SIPO.
48 20-04-2024 Saturday
WEEK OFF N/A
49 21-04-2024 Sunday

All the details mentioned about the learning and work done are correct to the best of my knowledge.
Student Signature: ____________________________
12002060501028 7
Working Days: ____________________ Working Hours: ___________________
Faculty Mentor Industry Mentor
Name Prof. Rohit R. Parmar Milin Parekh
Assistant Professor – Sr. Verification Engineer
Position
EC, GCET

Mail ID rohitparmar@gcet.ac.i milin.p@scaledge.io

n
Contact 9558823288 9033846345
Number
Positive attitude towards work. Enthusiastic about new task and new
topics learned. Implying self learning in sv topics to try out various
Comment examples on his own.
s on
Progress
Report

Signature

Remarks,
if any.

12002060501028 8