SANDEEP M G
Physical design engineer
OBJECTIVE
I'm a self-reliant and go-getter person
who's good at getting things done. I'm
determined to learn and grow, and I
aspire to forge a promising future by
leveraging my skills in an interdisciplinary
domain.
+91 6364628036
naveensandeepsandy@gmail.com
www.linkedin.com/in/sandeep-m-g-
584b08249
VLSI DOMAIN SKILLS
HDL : Verilog
EDA Tool : Model Sim ,Tanner EDA ,
Design Compiler, Calibre, PrimeTime,
Fusion compiler,
Domain: Physical Design flow including
floor planning, Placement & Routing
and Signoff, Calibre from Siemens EDA
Operating Systems: Working knowledge
on Windows and Linux
Scripting Language: Tcl & Python
Core Skills: RTL Coding using
Synthesizable constructs of Verilog,
FSM based design, Simulation, CMOS
Fundamentals, Static Timing Analysis,
Logic Synthesis, Floor planning,
Placement, Routing, Signoff (ERC,
DRC and LVS) ,DFT
TECHNICAL SKILLS
Programming language: C,Python
(Intermediate)
MATLAB
Microcontroller’s (Arduino uno,
esp8266 ,8051 )
PROFESSIONAL TRAINING
Advanced VLSI Physical Design Course
Maven Silicon VLSI Training Centre, Bangalore
EDUCATION
Bachelor of Engineering 2019 – 2023
Adichunchanagiri Institute of Technology, VTU
Branch - Electronics and communication Engineering
CGPA-7.1
Pre-university 2019
PCMB, PACE UM PU College, shivamogga
Percentage - 70.2%
Secondary School Certificate 2017
Nuthan English High School, Ajjampura
Percentage- 80.2%
VLSI PROJECTS
Router 1x3 - Maven Silicon
Performed Physical Design Flow for Router Design
spanning 32nm Technology.
Tools: Fusion Compiler, Prime Time
RTL synthesis, Floor Plan and Placement implemented at
Compile Fusion stage.
Clock Tree Synthesis and Routing are executed after Compile
Fusion, followed by Sign off ICV checks.
Timing verified with Prime Time tool at pre and post Routing
stages.
ORCA Project - Maven Silicon
Performed Physical Design Flow for ORCA Design spanning
32nm Technology.
Tools: Fusion Compiler, Prime Time
RTL synthesis, Floor Plan and Placement implemented at
Compile Fusion stage.
 DESIGN SKILLS
Digital Electronics : Combinational &
Sequential circuits, FSM, Memories,
CMOS implementation, Stick diagram,
STA : STA Basics, Comparison with
DTA, Timing Path and Constraints,
Different types of clocks Clock domain
and Variations, Clock Distribution
Networks, Fixing timing failure
Verilog Programming : Data types,
Operators, Processes, BA & NBA,
Delays in Verilog, begin - end & fork
join blocks, looping & branching
construct, System tasks & Functions,
compiler directives, FSM coding,
Synthesis issues, Races in simulation,
pipelining RTL & TB Coding, Physical
Design : Logic Synthesis, Floor
planning, Placement, Routing, Clock
Tree Synthesis and Timing Analysis
using FC , DRC, ERC, LVS and signoff
using Calibre.
LANGUAGES
Clock Tree Synthesis and Routing are executed after Compile
Fusion, followed by Sign off ICV checks.
Timing verified with Prime Time tool at pre and post Routing
stages.
RISC-V Project - Maven Silicon
Performed Physical Design Flow for RISC-V Design spanning
32nm Technology.
Tools: Design Compiler, IC Compiler II, Prime Time
Synthesized RISC-V RTL scripts in Design Compiler
Floor and Power Planning, Placement and optimization,
Clock Tree Synthesis and Routing are executed in ICC-II tool
Timing verified with Prime Time tool
ACADEMIC PROJECT
Title : POWER GENERATION AND MEASUREMENT IN
STREET LIGHTS USING SOLID WASTE AND ESP8266.
Generated electrical energy from non-biodegradable waste,
storing it efficiently for street lighting.
Developed a Smart Energy Meter with Arduino and ESP8266
for real-time energy monitoring worldwide. Incorporated
pollution control filters, emphasizing commitment to sustainable
energy and environmental responsibility.

Kannada INTERNSHIP
English
Got Certified in “Design and Development of IOT System
STRENGTHS
on NodeMCU platform using Python Enterprise
Dedication towards work
Application”. Internship at Loginware Softtec Pvt.Ltd.
Pressure management
Positive attitude (Fed - Mar 2023)

HOBBIES

Playing virtual games

Listening to music
Travelling

DECLARATION

I hereby declare that the information in the resume is true and complete to the best of my belief and
my knowledge.

Date :
(Sandeep M G)
Place: Bangalore