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Counters Notes
Counters Notes
A counter is the most versatile and useful subsystems in the digital system. A counter driven by
a clock can be used to count the number of clock cycles. Since clock pulses occur at known
intervals, the counter can be used as an instrument for measuring time and therefore period and
frequency. There are twotypes of counters: synchronous and asynchronous.
Counters operate in
– Count up mode
– Count down mode
When counters are cleared, then all the flip flops are ‘cleared’ and they contain zero.
Counter are preset such that the contents of the flip flop represent any desired binary number.
Asynchronous counter
Events that do not have fixed time relationship with each other and generally, do not occur at the
same time.
Asynchronous Counter is a digital circuit in which flip-flops (FF) within the counter do not
change states at exactly the same time because they do not have acommon clock pulse.
When the output of a flip-flop is used as the clock input for the next flip-flop, we call the
counter a ripple counter, or asynchronous counter.
• High at both the reset inputs resets all flip flops simultaneously.
A decoding gate can be connected to the outputs of a counter in such a way that the output of the
gate will be high (or low) only when the counter contents are equal to a given state.
Synchronous Counters:
Events that have fixed time relationship with each other and generally, occur at the same time.
With all clock inputs wired together, propagation delay is assumed to be equal.Propagation
Delay occurs from the triggering edge of the input clock pulse.
Response time for a Synchronous counter is faster than Asynchronous circuit.A 2 Bit Binary
The flip-flop delay time and possibility of glitches are overcome by the use of asynchronous or parallel
counter.
Counters are said to have a “natural count” of 2n. A counter having a modulus of3 or 5 would be
useful and such counters are said to have a modified count.
Decade Counters
A Mod-5 counter:
A MOD-10 Counter
Presettable Counters
The 74HC/HCT163 are synchronous presettable binary counters which feature an internal look-
ahead carry and can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the clock (CP).The outputs (Q0 to Q3) of
the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input
(PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded
into the counter on the positive-going edge of the clock (providing that the set-up and hold time
requirements for PE are met).
Preset takes place regardless of the levels at count enable inputs (CEP and CET). For the
“163” the clear function is synchronous. A LOW level at the master reset input (MR) sets all
four outputs of the flip-flops (Q0 to Q3) to LOW level after the next positive-going transition
on the clock (CP) input (provided that the set-up and hold time requirements for MR are met).
This action occurs regardless of the levels at PE, CET and CEP inputs.
This synchronous reset feature enables the designer to modify the maximum count with only one
external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both count
enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of
a duration approximately equal to a HIGH level output of Q0. This pulse can be used to enable
the next cascaded stage.
Synchronous Up-Down counter:
Let us try to design a modulo-6 counter, the counting states (memory values) of which are shown
in state transition diagram. We need three memory element or flip-flops for this as with n flip-
flop we can get at most 2n number of different counting states.
000
101 001
010
100
011
Our next objective is to get logic equation for each flip-flop input as a functionof present state
of the counter.
Bn An Bn An
Cn 00 01 11 10 Cn 00 01 11 10
0 0 1 1 0 0
1 1 0 1
JC = An KC = An
Bn Bn An
An Cn
Cn 00 01 11 10 00 01 11 10
0 0 1 0 1 0
1 0 00
0
1
_
JB = Cn An KB = An
The final step is to draw the circuit diagram from the design equations, which isshown.
1 JA A JB B JC C
_ _
A KB B _
1 KA 1 KC C
CLK