Machine Learning in Advanced IC Design: A Methodological Survey.

Chapter 1

INTRODUCTION

1.1 Introduction
The continuous increase in transistor count in Integrated Circuits (ICs), along with
complex design flows, has posed significant challenges for engineers. These challenges
range from the high cost of exploring extensive design spaces, lengthy verification
simulations, to the requirement for expertise in intricate optimization algorithms. This is
where Machine Learning (ML) emerges as a transformative force. ML equips IC
designers, which includes a broad spectrum of professionals such as circuit designers,
physical design engineers, and verification engineers. A Typical IC design flow shown in
the figure 1.1 where many complex processes are involved the overall ship design
process. By harnessing its data-driven learning capabilities, ML effectively addresses the
challenges mentioned.

Figure. 1.1 Typical IC design Flow

The complexity of the ML process also poses a challenge. The process of training
ML models, tuning hyperparameters, and validating the models can be complex and time-
consuming. In some cases, there might not be enough data available to train robust ML
models, leading to a lack of training data. Furthermore, the process of integrating ML
models into existing workflows and systems can be slow and challenging, leading to slow
implementation.

Implementing Machine Learning (ML) for Integrated Circuit (IC) design is not
without its challenges. One of the primary challenges is the quality of data. ML heavily
relies on data, and poor quality can significantly impact the performance of ML models.
This is closely tied to the issues of underfitting and overfitting, common problems in ML.
Underfitting occurs when the model is too simple to capture the underlying structure of
the data, while overfitting happens when the model is too complex, leading to an overfit
of the training data.
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Machine Learning in Advanced IC Design: A Methodological Survey.

As data grows, there can be imperfections in the algorithm which can affect the
performance of the ML models, leading to algorithmic imperfections. The characteristics
of analog systems are challenging, and the "always new" device models are being
progressively introduced with new specifications and functionalities. This presents a
unique challenge in the implementation of ML in IC design.

Lastly, the field of VLSI design is characterized by rapid technological

advancements. VLSI designers must study and integrate these advancements as they
occur on a daily and periodic basis to upgrade their design pattern. These challenges need
to be addressed for the effective implementation of ML in IC design. It's a complex task,
but the potential benefits make it a worthwhile endeavour.

The various ML methodologies that tackle these challenges which are:

 Tackling Complexity with Efficient Feature Representation: In the traditional

approach, engineers had to manually extract features from design data for ML
algorithms to comprehend them. This survey underscores advancements in how
ML can automatically learn efficient features directly from raw design data,
thereby overcoming complexity.
 Shallow vs Deep Learning: A Broad Spectrum of Techniques: The paper
investigates both shallow learning models, where features are predefined, and
deep learning models, specifically Deep Neural Networks (DNNs), which can
automatically extract features through multiple layers.
 Deep Learning Takes the Spotlight: The paper explores diverse types of DNNs,
including Convolutional Neural Networks (CNNs) for image-based design data
and Graph Neural Networks (GNNs) for data with irregular grid structures.
 Generative Models for Comprehensive Design Exploration: The survey delves
into generative models, a type of deep learning that employs DNNs to learn
probability distributions. This enables the generation of modern design samples
that meet specific requirements, facilitating comprehensive design space
exploration.
 Reinforcement Learning for Purposeful Optimization: The paper investigates how
Reinforcement Learning, another potent ML technique, uses DNNs to steer
algorithms towards achieving desired design goals, further optimizing the design
process.

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Machine Learning in Advanced IC Design: A Methodological Survey.

1.2 Problem Statement

The field of Integrated Circuit (IC) design faces several challenges such as the
high cost and time consumption of design space exploration, bottlenecks in verification
simulations, limited scalability of traditional design optimization techniques, and the
expertise barrier in complex design flows. Machine Learning (ML) is being explored as a
solution to these problems. It can automate feature extraction and design exploration,
enable faster and more accurate performance evaluation, enhance design optimization
with data-driven techniques, and democratize IC design with user-friendly tools. Thus,
ML offers promising solutions by leveraging its data-driven learning capabilities to
automate tasks, improve performance evaluation, and optimize designs, highlighting the
need for efficient and scalable design methodologies in advanced IC design.

1.3 Objectives
The main objectives of the survey were to:

 Cost and Time Efficiency in Design Space Exploration: Traditionally,

exploring the vast design space for optimal circuit implementations requires
expensive simulations and manual effort. ML automates feature extraction and
design exploration, significantly reducing the cost and time required.
 Efficiency in Verification Simulations: Large-scale IC designs often involve
time-consuming simulations, especially during verification stages like
lithography simulation. ML can provide faster and more accurate performance
evaluations compared to traditional simulations, thereby accelerating the
design process.
 Scalability in Design Optimization: Existing design optimization algorithms
may not scale effectively with the increasing complexity of IC designs. ML
techniques can optimize designs based on data, potentially surpassing the
limitations of traditional optimization algorithms.
 Accessibility of IC Design Tools: The intricate nature of IC design flows can
create a barrier for engineers who might lack expertise in complex
optimization algorithms. By transforming complex problems into data-driven
approaches, ML has the potential to make IC design tools more accessible to a
broader range of engineers.

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Machine Learning in Advanced IC Design: A Methodological Survey.

Chapter 2

LITERATURE SURVEY
2.1 Related Work
B. Khailany et al., “Accelerating Chip Design with Machine Learning” [1] offers
a comprehensive examination of Machine Learning (ML) applications in expediting chip
design processes. It delves into the mounting complexity of chip designs and the
accompanying challenges. Emphasizing ML's potential to streamline chip design, the
authors elucidate its utilization for overcoming these hurdles. The paper meticulously
reviews existing ML methodologies employed to accelerate chip design, encompassing
techniques like deep learning and reinforcement learning, and their application across
various design stages. Additionally, it scrutinizes the benefits and limitations of
integrating ML into chip design workflows, acknowledging ML's potential to enhance
efficiency and accuracy while acknowledging the complexities involved. Serving as a
valuable resource for researchers and professionals, the paper furnishes a comprehensive
understanding of the current ML landscape in chip design and offers insights into
potential future trajectories in this swiftly evolving domain.

B. K. Joardar, T. K. Bletsch, and K. Chakrabarty, “Learning to Mitigate

Rowhammer Attacks” [2] offers a thorough investigation into the utilization of Machine
Learning (ML) for mitigating Rowhammer attacks. Rowhammer, a vulnerability
stemming from the unintended interaction between physically adjacent rows in Dynamic
Random Access Memory (DRAM), poses significant security risks as existing DRAM
protections are inadequate against it. The authors propose an ML-based solution for
Rowhammer mitigation, demonstrating its efficacy in reliably detecting and preventing
bit flips across various types of Rowhammer attacks. Compared to recent mitigation
techniques, the ML model exhibits lower power and area overhead across 26 different
applications from benchmark suites like Parsec, Pampar, and Splash-2. This paper serves
as a valuable resource for researchers and professionals seeking insights into ML's
application in combating Rowhammer attacks, providing a comprehensive overview of
the current state of the art and potential future directions in this swiftly evolving domain.

A. Krizhevsky, I. Sutskever, and G. E. Hinton, “ImageNet classification with deep

convolutional neural networks” [3] stands as a seminal contribution in the realm of deep
learning. The authors undertook the ambitious task of training a large, deep convolutional

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Machine Learning in Advanced IC Design: A Methodological Survey.

neural network to classify 1.2 million high-resolution images from the ImageNet LSVRC-
2010 contest into 1000 distinct classes. Remarkably, they achieved significantly improved
performance, with top-1 and top-5 error rates of 37.5% and 17.0%, respectively,
surpassing previous state-of-the-art benchmarks. The neural network architecture
comprised five convolutional layers, some accompanied by max-pooling layers, and three
fully connected layers culminating in a 1000-way softmax output. Notably, to expedite
training, they employed non-saturating neurons and leveraged a highly efficient GPU
implementation for convolution operations. Additionally, to curb overfitting in the fully
connected layers, they introduced a novel regularization technique known as "dropout,"
which proved remarkably effective. This seminal work has profoundly impacted the
machine learning landscape, particularly in image classification, serving as a catalyst for
numerous subsequent studies and innovations.

K. Zhu et al., “GeniusRoute: A new analog routing paradigm using generative

neural network guidance” [4] introduces an innovative approach to analog routing by
employing generative neural networks. The authors address the intricate challenges
inherent in analog routing, stemming from layout-dependent effects and diverse
performance metrics. They propose a fully automated analog routing paradigm that
harnesses machine learning to furnish routing guidance, emulating the nuanced strategies
employed in manual layout approaches. The methodology proposed demonstrates
significant enhancements over existing techniques, achieving performance levels
comparable to manual layouts while exhibiting adaptability to circuits of varying
functionalities. This paper serves as a valuable resource for researchers and practitioners
invested in the integration of machine learning in analog routing, furnishing a
comprehensive insight into the current state-of-the-art and potential future trajectories in
this dynamic domain.

S. K. Mandal et al., “An energy-aware online learning framework for resource

management in heterogeneous platforms” [5] introduces an innovative online learning
framework tailored for resource management in heterogeneous platforms. The authors
delve into the complexities associated with managing resources in such platforms,
characterized by diverse hardware components like CPUs, GPUs, and FPGAs. They
propose an energy-aware online learning framework capable of dynamically adapting to
varying workloads and optimizing resource allocation in real-time. Central to their
approach is the utilization of machine learning techniques to predict the performance and
power consumption of different hardware configurations, enabling informed decisions for

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Machine Learning in Advanced IC Design: A Methodological Survey.

resource allocation aimed at achieving a balance between performance and energy

efficiency. Through extensive experiments conducted on a commercial mobile platform
with a diverse set of benchmarks, the authors validate the effectiveness of their
framework. Remarkably, their approach demonstrates the ability to adapt the control
policy to unknown applications after executing less than 25% of their instructions. In
summary, the paper constitutes a significant contribution to the realm of resource
management in heterogeneous platforms, offering a novel methodology that harnesses
machine learning for energy-aware and performance-optimized resource allocation.

Y. Li et al., “A circuit attention network-based actor– critic learning approach to

robust analog transistor sizing” [6] is an innovative methodology for analog transistor
sizing by integrating a circuit attention network and an actor-critic learning approach. The
authors address the intricate challenges inherent in analog transistor sizing, arising from
the complex interplay among different transistors and the sensitivity of analog
performance to transistor sizes. Their proposed approach harnesses machine learning to
deliver robust and efficient solutions to these challenges. Leveraging a circuit attention
network, the methodology captures the intricate interactions between transistors, while an
actor-critic learning approach optimizes transistor sizes. Through extensive
experimentation across a variety of benchmark circuits, the authors demonstrate the
efficacy of their approach. In summary, the paper makes a valuable contribution to the
domain of analog transistor sizing by offering a novel methodology that leverages
machine learning to achieve robust and efficient transistor sizing, thereby enriching our
understanding of the current state-of-the-art and paving the way for potential future
directions in this rapidly evolving field.

2.2 Previous Work Done

M. Rapp et al., “MLCAD: A Survey of Research in Machine Learning for CAD
Keynote Paper” [7] addresses the escalating complexity of ICs stemming from transistor
count scaling, emphasizing how ML can develop robust models to tackle design
challenges at both design and run times. The authors categorize ML usage for design-time
and run-time optimization, conducting a meta-study to discern well-explored and
underexplored areas in Computer-Aided Design (CAD) with ML, along with trends in
ML algorithms. The paper offers a detailed categorization and overview of the current
ML landscape in CAD, discussing remaining challenges and promising research avenues.
In sum, it serves as a valuable reference for researchers and professionals, providing
insights into the present state and prospects of ML in CAD for ICs.

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Machine Learning in Advanced IC Design: A Methodological Survey.

K. I. Gubbi et al., “Survey of machine learning for electronic design automation”

[8] offers a thorough examination of the integration of Machine Learning (ML) in
Electronic Design Automation (EDA). The authors address the escalating complexity of
very large-scale integrated (VLSI) designs, primarily attributed to the downscaling of
CMOS technology. Despite ML techniques' historical application in EDA since the
1990s, recent ML advancements coupled with the mounting intricacies of EDA tasks
have spurred heightened interest in employing ML for addressing EDA challenges. The
paper meticulously reviews existing studies on ML for EDA, categorized according to the
EDA hierarchy. By presenting a comprehensive overview, the paper serves as an
invaluable resource for researchers and professionals interested in harnessing ML for
EDA, offering insights into the present state and prospective trajectories of this swiftly
evolving domain.

Huang et al., “Machine learning for electronic design automation: A survey” [9]
underscores the rising demand for semiconductor ICs, coupled with advancements in ML
and the deceleration of Moore's law, which collectively fuel the growing interest in
leveraging ML to augment EDA and CAD tools and processes. The paper systematically
surveys existing EDA and CAD tools, methodologies, processes, and techniques for ICs
employing ML algorithms. ML-based EDA/CAD tools are categorized based on IC
design steps, encompassing synthesis, physical design (such as floorplanning, placement,
clock tree synthesis, and routing), IR drop analysis, static timing analysis (STA), design
for test (DFT), power delivery network analysis, and sign-off. Additionally, it delves into
the contemporary landscape of ML-based VLSI-CAD tools, current trends, and prospects
of ML in VLSI-CAD. Serving as a valuable resource, this paper furnishes researchers and
professionals with a comprehensive understanding of the current state and potential future
trajectories of ML in EDA and CAD for ICs.

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Machine Learning in Advanced IC Design: A Methodological Survey.

Chapter 3

METHODOLOGY & IMPLEMENTATION

3.1 Linear Model

Is a Simple and Efficient Workhorse for IC Design, where the fundamental
concept in machine learning, play a significant role in various stages of Integrated Circuit
(IC) design. Often referred to as shallow learning models, they offer a balance between
simplicity and effectiveness. Linear models are known for their ease of training. A
technique called least-squares method helps the model adjust these weights to minimize
the difference between the predicted values (ŷ) and the actual values we have for the
outcome (label) shown in the figure 3.1. This training process allows the model to learn
the relationships between features and the desired outcome.

Figure. 3.1 (a) Linear Model (b) ANN

The key advantage of linear models lies in their simplicity and efficiency. Unlike
more complex models, they require less computational power and are easier to interpret.
This makes them particularly well-suited for real-time applications on chip, where
minimizing overhead is crucial. Imagine a scenario where someone tries to tamper with
your computer's hardware. Linear models can be used to analyse data like memory access
patterns and identify such security threats. Their low computational cost allows them to
run continuously on the chip itself, detecting suspicious activity in real-time with minimal
impact on performance.

Battery life is a major concern for mobile devices. Linear models can be employed
to predict future traffic on a chip's internal network, allowing for optimized power
management strategies. By anticipating workload demands, the model can help adjust

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Machine Learning in Advanced IC Design: A Methodological Survey.

power settings for different components, leading to more efficient power usage. Linear
models have a key limitation: they assume that each feature has an independent effect on
the outcome. In real-world scenarios, features can be interconnected and influence each
other. For instance, high memory usage might also lead to increased network traffic. Just
like a good cook might adjust a recipe, researchers can modify the basic linear model
structure to improve its effectiveness for specific tasks. For example, using different types
of linear regression models might yield better results for predicting power consumption
across various types of processing cores on a chip.

Combining Linear Layers to overcome limitation where each layer can focus on a
specific set of features, and the combined output provides a more comprehensive
prediction. This approach can be used for tasks like workload and power prediction,
where different features like memory usage and processing activity play a role. The
usefulness of linear models extends beyond power management and security. They also
contribute to the verification stages of IC design:

Manufacturing variations, voltage fluctuations, and temperature changes (PVT

corners) can affect a chip's performance. Linear models can be used to predict timing
behaviour under these different conditions, even for untested corners. This helps ensure
the chip functions reliably across various operating scenarios. EM occurs when excessive
current flow weakens the metal wires within a chip. Linear models, specifically logistic
regression, can be used to analyse design data and identify potential EM violations. This
helps prevent chip failures caused by this phenomenon.

Linear models, despite their simplicity, offer a valuable toolbox for IC designers.
Their efficiency, ease of use, and diverse applications in areas like security, power
management, and verification make them a cornerstone for various stages of the design
process. However, it's important to be aware of their limitations and explore variations or
combinations with other models when dealing with complex relationships between
features.

3.2 Non-Linear Models

While linear models provide a solid foundation, they sometimes struggle to
represent the intricate relationships between features and predictions in advanced IC
design. This is where non-linear models come into play. Unlike their linear counterparts,
these models offer a more sophisticated toolbox, enabling the capture of complex
interactions within the data. Some prominent examples of non-linear models used in IC
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Machine Learning in Advanced IC Design: A Methodological Survey.

design include Artificial Neural Networks (ANNs), Gaussian Processes (GPs), Support
Vector Machines (SVMs), and Random Forests. For trying to predict the weather. While
a simple linear model might struggle to account for all the factors involved (e.g.,
temperature, humidity, wind), non-linear models can handle these complexities. Here's
how some of them achieve this:

 Artificial Neural Networks (ANNs): Think of these models as interconnected

layers of simple processing units (neurons) inspired by the human brain. Each
layer can perform transformations on the data using non-linear activation
functions like ReLU (Rectified Linear Unit) or Sigmoid (Figure 3.2 b). These
functions introduce non-linearity, allowing the model to learn complex
relationships between features that would not be possible with linear models
alone.
 Non-linear SVMs and GPs: Imagine transforming data points from a flat map to a
3D space. This is the concept behind kernel functions used by non-linear SVMs
and GPs (Figure 3.2 b). These functions map data points from the original feature
space (e.g., flat map) to a higher-dimensional space where linear separation
becomes possible, even if it was not achievable in the original space. However,
choosing the right kernel function for a specific task can be challenging, requiring
few experimentations.

Figure. 3.2 (a) Activations. (a) Feature space mapping by the kernel.

 Random Forests: This model takes a different approach by using adaptive basis
functions. Imagine dividing the input feature space (think of it as a map) into
regions. Random Forests define these regions using functions and then assign
weights to each region based on the data. This allows the model to capture
complex relationships within the data without relying on explicit non-linear
transformations.

Non-linear models offer a diverse toolbox for tackling various challenges in IC

design:
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Machine Learning in Advanced IC Design: A Methodological Survey.

 Design Rule Checking (DRC) Prediction: As chip designs become more intricate,
verifying adherence to design rules becomes time-consuming. A non-linear SVM
model can predict potential DRC violations after global routing (a stage in the
design flow) without requiring a detailed routing step, which can be
computationally expensive. The model analyses feature like connected pins and
cell density in the layout to identify potential problem areas.
 Rapid Layout Feasibility Evaluation: Imagine quickly assessing if a layout design
is even feasible. An ANN model can estimate the correlations between various
interconnect parasitic (unwanted electrical effects) based on the layout
configuration. This is crucial because the relationship between hardware
configuration and performance can be highly non-linear, making traditional linear
models ineffective.
 Fast Performance Estimation: Traditional analytical performance evaluation
methods can be computationally expensive. Support Vector Regression (SVR), a
type of non-linear model, can be used to rapidly estimate power consumption
based on input signals and hardware configuration. Similarly, non-linear models
have been used to estimate the performance of adders, replacing traditional EDA
(Electronic Design Automation) tools for faster power, delay, and area estimation.
Circuit structure information and tool settings are used as input features for these
models.

In some non-linear models, like GPs, can provide predictions with uncertainties. This
allows for a technique called Bayesian optimization, which uses this information to guide
the selection of the most informative data points for training the model. This reduces the
number of simulations needed and speeds up the design exploration process. By reducing
EDA tool runtime and enhancing learning during the design stage, Bayesian optimization
techniques based on regression forests can be used for faster exploration across various
areas like digital design, analog design, and hardware deployment.

Regression forests can also be used to find a sweet spot between different design
goals. Imagine you want a chip that is both powerful and energy efficient. Regression
forests can model the relationship between design choices and a metric called Pareto
hypervolume, which helps achieve a better trade-off between various design objectives.

In conclusion, non-linear models offer a significant leap forward compared to

linear models. By capturing complex relationships within the data, they enable faster

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Machine Learning in Advanced IC Design: A Methodological Survey.

performance estimation, efficient design space exploration, improved design rule

checking, and better multi-objective optimization, ultimately leading to more powerful
and efficient IC designs.

3.3 Convolutional Neural Networks (CNNs)

Convolutional Neural Networks (CNNs) are a type of deep learning model that
excel at analysing image data. This makes them particularly well-suited for the world of
IC design, where chip layouts can be represented as images. Imagine analysing a
photograph to identify objects within it. CNNs work in a similar way for IC design. They
consist of several key layers (Figure 3.3):

Figure. 3.3 Typical CNN structure.

Convolutional Layers layers act like filters that scan the layout image. Each filter
focuses on detecting specific features, like lines, shapes, or patterns. As the filter slides
across the image, it performs calculations to highlight these features, creating a "feature
map." Pooling layers aim to reduce the complexity of the feature maps as shown in figure
3.4 a. Imagine summarizing the information in a small neighbourhood within an image.
Pooling layers achieve this by taking the maximum value (max-pooling) or the average
value (average-pooling) within a specific region of the feature map as shown in figure 3.4
b. This helps the model focus on the most important information. These final layers take
the information extracted from the feature maps and use it for tasks like classification
(e.g., identifying a potential defect) or regression (e.g., predicting performance metrics).

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Machine Learning in Advanced IC Design: A Methodological Survey.

Figure. 3.4 (a) Convolution operation. (b) Pooling operations.

The field of deep learning is constantly evolving, and researchers are exploring
ways to improve CNNs. Imagine focusing on a specific part of an image while ignoring
the rest. The attention mechanism works similarly. It assigns weights to different areas of
the feature map, directing the model's focus towards crucial information for improved
accuracy. This powerful architecture is often used for tasks involving sequences. In IC
design, it can be used with CNNs to capture global relationships within the layout data.
Imagine looking at an entire image, not just individual parts, to understand the bigger
picture. Transformers with multi-head attention modules help achieve this for complex
layout analysis.

Manufacturing chips involves a process called lithography, where patterns are

transferred onto the chip surface. Certain layout features can make some areas more prone
to printing errors (hotspots). Traditionally, identifying these hotspots is time-consuming.
CNNs can analyse layout features and rapidly predict where hotspots might occur,
allowing for early intervention.

As current flows through wires on a chip, there can be a voltage drop (IR-drop).
Predicting this drop is crucial for ensuring chip reliability. CNNs can analyse the
distribution of power across the layout and predict the maximum IR-drop, guiding
designers towards layouts with minimal voltage drops.

Chip layouts can come in various sizes. A special type of CNN called a Fully
Convolutional Network (FCN) can address this challenge shown in figure 3.5. FCNs
replace fully connected layers with convolutional layers, allowing them to handle inputs
of different sizes. This makes them suitable for tasks like predicting potential design rule
violations or performance metrics across layouts of varying dimensions.

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Machine Learning in Advanced IC Design: A Methodological Survey.

Figure. 3.5 Fully Convolution Neural Network.

Global routing is a stage where connections between different parts of the chip are
established. Traditionally, this involves trial-and-error routing to check for design rule
violations (DRC). FCNs can analyse the layout and predict potential DRC violations
without actual routing, saving significant time. They consider factors like placement of
blocks, wire density, and pin locations to make these predictions.

CNNs can be used to predict performance metrics like congestion or how easily
wires can be routed within a layout. By analysing how the model's output changes with
respect to the input layout, engineers can understand which layout features most
significantly impact performance. This information can then be used to guide the routing
and placement processes for optimal chip design.

Attention mechanisms can be easily integrated into CNNs for tasks like
lithography hotspot detection. By focusing on critical features in the layout, they can lead
to more accurate hotspot identification. Transformers with multi-head attention modules
can be used to develop one-stage detectors for identifying hotspots within large-scale
layouts. These models can directly predict the bounding boxes (areas containing hotspots)
within the layout image, offering a faster and more efficient approach.

Attention is one of the advanced modules to enhance feature representation. It

assigns different weights to each part of the input and extracts more critical information to
enable the model to make more accurate judgments. The attention maps are calculated
from channel and space dimensions. In Figure 3.6 (a), a shared multilayer perceptron
(MLP) is used to extract two features from the outputs of two pooling branches in the
channel attention module.

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Machine Learning in Advanced IC Design: A Methodological Survey.

Figure. 3.6 Attention (a) channel attention and (b) spatial attention.

In Figure 3.6 (b), the max-pooling, mean pooling, and convolutional layers are
stacked to obtain spatial attention from a channel-refined feature. Based on the attention
mechanism, the transformer is proposed in many sequence-to-sequence tasks. They both
contain multiheaded attention modules to extract information at different locations
globally.

3.4 Graph Neural Networks (GNNs)

If a circuit as a network of interconnected components, Graph Neural Networks
(GNNs) take advantage of this network structure to bring new capabilities to IC design.
They excel at analysing the relationships between different parts of a circuit, represented
as a graph where devices are like stations and connections are like lines. The blueprint for
a circuit, called a netlist, can be visualized as a graph. Devices like transistors become
nodes (stations) on the map, and connections between them become edges (lines). Each
device also has properties like size, which act like labels on these stations.

GNNs don't just analyse individual devices, they also consider how they're
connected. Special techniques called embedding methods are used to create a more
comprehensive picture. Imagine asking each station on the map about its neighbours and
summarizing the information. This allows GNNs to capture the relationships between
devices within the circuit. One way to learn from connections is through graph
convolution. This method considers a device's neighbours (up to a certain distance) and
generates a new "understanding" of that device based on the information gathered. So, a
GNN model might consider all the devices connected to a specific transistor (within a
two-station radius) to understand its role within the circuit as shown in Figure 3.7.

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Machine Learning in Advanced IC Design: A Methodological Survey.

Figure. 3.7 Netlist, graph representation, and graph convolution.

GNNs go beyond just representing the circuit structure. They use special
techniques called embedding methods to understand how components relate to each other.
Imagine asking your friends about a restaurant their opinions (information) can influence
your decision (embedding). Similarly, GNNs gather information from a node's
neighbours (connected components) and combine it to create a new feature that represents
the node's role within the circuit. Some common embedding methods include:

This method considers how close connected components are to a node. It gathers
information from a node's neighbourhood (up to a certain distance) to understand its
context within the circuit. Imagine a GNN model analysing a transistor (M1) – it might
consider information from nearby resistors and capacitors to understand M1's role in the
circuit (Figure 3.6).

Manually identifying crucial elements in analog circuits can be time-consuming.

GNNs can analyse the circuit netlist and automatically learn to recognize these important
features, aiding in the design process. GNNs can be combined with other techniques like
Generative Adversarial Networks (GANs) to create a hierarchy for analog circuits. Think
of it like organizing a city into districts and neighbourhoods. This improved organization
helps with managing the design process. Traditionally, verifying a circuit design can be
computationally expensive. GNNs can be used to identify points within the circuit where
additional checks might be needed, leading to faster verification.

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Machine Learning in Advanced IC Design: A Methodological Survey.

Predicting Aging Effects: Over time, transistors can become less effective. GNNs
can consider the different types of devices within a circuit and predict which ones might
be more susceptible to aging, allowing for preventive measures during design.

Standard GNN techniques might struggle with circuits containing many

connections between devices. Here's where Graph Attention (GAT) comes in GAT
assigns weights (like importance scores) to connections between devices. Imagine
focusing more on nearby stations on the map compared to distant ones. This allows the
model to prioritize relevant information from neighbouring devices based on the specific
context. GAT can introduce different scores for each connection, enabling a more
nuanced analysis. This allows the model to consider various aspects of the connections
and their impact on different devices within the circuit.

GAT can enhance GNNs' ability to learn from existing designs. This allows them
to predict electrical effects (called net parasitic) and device behaviour even without
complete physical design information, which can be helpful in the early stages of design.
GNNs with GAT can be used to estimate the length of wires before they're placed within
the circuit. By considering the relationships between devices and their neighbours, GAT
helps the model prioritize relevant information for more accurate length estimation.

While other methods focus on understanding individual devices or connections,

graph pooling aims to represent the entire circuit as a single entity. Imagine gradually
merging stations on the map into larger hubs while capturing the essence of each merged
region. This is like how graph pooling works. A common technique called DIFFPOOL
iteratively combines nodes and their features, reducing the complexity of the graph while
preserving important information.

Simulating circuit performance using traditional methods can be computationally

expensive. GNNs with DIFFPOOL can be used to predict performance metrics like gain
in analog circuits without requiring these simulations. This information can then be used
to optimize circuit design. GNNs with DIFFPOOL can analyse circuit data and identify
potential issues that might cause delays in 3D integrated circuits. Imagine a circuit as a
network of interconnected components. Graph Neural Networks (GNNs) are a type of
deep learning model that excels at analysing these interconnected systems, making them
particularly valuable for IC design. GNNs can represent this diagram as a graph, where
electronic components like transistors and resistors become nodes (points), and the
connections between them become edges (lines). Each node can also hold information
about the component, such as its size or type.
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Machine Learning in Advanced IC Design: A Methodological Survey.

Analog circuits often have specific design rules. Traditionally, engineers manually
identify these constraints. GNNs can analyse the circuit netlist (graph) and automatically
learn to identify critical structures that require special attention during design, saving
engineers time and effort. GNNs can be combined with other techniques like Generative
Adversarial Networks (GANs) to classify circuits and organize them into sub-blocks. This
can be particularly useful in complex analog designs, where better organization aids in
managing and understanding the circuit.

Verifying a circuit design involves checking for errors. GNNs can be used to
design classifiers that can quickly identify areas in the netlist that might require further
testing, accelerating the verification process. Electronic components can degrade over
time. GNNs can be used to identify transistors susceptible to aging effects in analog
circuits. By considering different types of elements within the circuit, GNNs can make
more accurate predictions.

Standard GNN methods might struggle with circuits that have many connections
between components. Graph Attention (GAT) addresses this by assigning weights
(importance scores) to connections (edges). Imagine focusing on the most helpful advice
from your friends about the restaurant – GAT works similarly. By assigning higher
weights to crucial connections, GAT allows the model to prioritize relevant information
from neighbouring nodes, leading to more accurate results. Additionally, GAT can
introduce multiple weights for each connection, enabling even more nuanced learning
based on the specific context.

Unwanted electrical effects (parasitic) can impact circuit performance. GAT can
enhance GNNs' ability to learn from existing designs and predict these parasitic, even for
new circuits without complete physical design information. Estimating the length of
connections (nets) before placing components on the chip is crucial. GNNs with GAT can
capture a more comprehensive understanding of a node and its neighbours, allowing for
more accurate net length estimations.

3.5 Generative Models

Only having a tool that can not only analyse existing chip designs but also
generate new design elements or predict missing information. This is the power of
Generative Models, a category of machine learning that excels at learning from data

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Machine Learning in Advanced IC Design: A Methodological Survey.

patterns and creating new samples. This section explores two prominent generative
models used in IC design:

1. Variational Autoencoders (VAEs) and

2. Generative Adversarial Networks (GANs).

Variational Autoencoders (VAEs): VAEs tackle the challenge of understanding

complex relationships between various features in a chip design. They achieve this by
introducing a hidden concept called a "latent variable" that captures the essence of the
design shown in the figure 3.8. Imagine summarizing a complex design into a single,
simplified representation. This latent variable allows the VAE to learn a connection
between the actual design data (like chip layout) and this simplified version, and then
recreate the original design from the simplified representation.

Figure. 3.8 Variational Autoencoders (VAEs).

Routing involves strategically connecting different parts of a chip with wires. A

VAE can analyse a chip layout (considering pin locations and overall design) and predict
areas suitable for routing wires. This prediction, like a probability map, can guide
automated routing tools for better performance optimization during the design process.

Generative Adversarial Networks (GANs): Unlike VAEs, GANs take a more

competitive approach to learning. They involve two neural networks: a generator and a
discriminator shown in the figure 3.9. Imagine a game where the generator creates new
designs (like chip masks for manufacturing), and the discriminator tries to distinguish
these generated designs from real ones. Through this ongoing competition, the generator
progressively improves its ability to create realistic and useful designs.

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Machine Learning in Advanced IC Design: A Methodological Survey.

Figure. 3.9 Generative Adversarial Networks (GAN).

A special type of GAN called a Conditional GAN (CGAN) takes things a step
further. CGANs can generate new designs based on specific requirements or conditions.
This is particularly useful in IC design, where designers often have certain goals in mind.
Noise can disrupt chip functionality. CGANs can be used to generate "noise maps" that
indicate areas where noise sensors are most needed. This helps engineers place sensors
strategically with minimal placements, ensuring efficient noise monitoring.

Manufacturing chips involves creating masks that define circuit patterns. CGANs
can be used to optimize these mask layouts. Imagine the CGAN taking an existing mask
layout and generating a new one that compensates for potential manufacturing issues, all
without requiring complex simulations. Clock signals are crucial for chip operation.
CGANs can be used to optimize clock tree design, which efficiently distributes these
signals. By providing desired parameters like power consumption and wire length, the
CGAN can recommend optimal layouts for the clock tree network.

In conclusion, Generative Models offer a powerful toolkit for IC design. VAEs

can analyse complex design data and predict relevant features, while CGANs can
generate entirely new design elements based on specific conditions. These capabilities
have the potential to streamline design workflows, improve design efficiency, and even
lead to innovative design solutions.

3.6 Reinforcement Learning

If a chip design process where an AI agent learns by doing, like a student
mastering a new skill. This is the essence of Reinforcement Learning (RL), a powerful
technique for IC design. Here, the agent interacts with a simulated environment,
experimenting with different design choices and receiving feedback to improve its
strategies. RL works by placing an agent in a simulated environment. The agent can
take actions, like placing a specific block on a chip design, and receives rewards based on

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Machine Learning in Advanced IC Design: A Methodological Survey.

the outcome. For example, a more efficient placement might result in a higher reward.
Over time, the agent learns to choose actions that consistently lead to better rewards. To
understand RL problems, we use a concept called a Markov Decision Process (MDP)
shown in figure 3.10. The MDP as a game with four key elements:

Figure. 3.10 Markov Decision Process (MDP).

 States: These represent all the possible situations the agent can encounter (e.g.,
different chip design layouts with varying block placements).
 Actions: These are the choices the agent can make (e.g., selecting and placing a
specific block).
 State Transitions: These represent the probability of moving from one situation
(e.g., current chip layout) to another (e.g., layout after placing a block).
 Rewards: These are like feedback signals telling the agent how good or bad an
action was in a particular situation (e.g., higher reward for a more efficient
placement).

The goal of RL in IC design is for the agent to develop an optimal strategy, or policy,
that consistently leads to the best outcomes (highest rewards) over time.

Reinforcement Learning holds great promise for automating various aspects of IC

design. By continuously learning from simulated environments, RL agents can develop
effective strategies for tasks like strategically placing blocks on a chip, efficiently routing
wires between them, and managing power consumption. This can lead to improved design
quality, faster design cycles, and potentially even innovative design solutions in the
future. Imagine a chip designer with a magic tool that predicts the future outcomes of
their design choices. This is essentially what value function-based methods offer within
Reinforcement Learning (RL) for IC design. These methods help RL agents learn the best
strategies for design tasks by estimating a special value, the "value function.". When the
agent updates its strategy (policy), the value function needs to be re-estimated, which can
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Machine Learning in Advanced IC Design: A Methodological Survey.

sometimes hinder overall learning. Researchers are actively exploring techniques to

overcome these limitations and further improve the effectiveness of value function-based
methods in RL for IC design.

In conclusion, value function-based methods provide a powerful approach for RL

in IC design. By iteratively estimating the value function and improving the policy, these
methods enable agents to learn optimal strategies for tasks like DVFS, leading to
improved performance and power management in chip designs. The future holds promise
for even faster and more efficient learning through ongoing research efforts.

Machine learning (ML) has become a game-changer in IC design, but there's still
room for improvement. This section explores some of the key challenges and promising
solutions to push the boundaries of ML-powered chip design.

 Challenge 1: Scaling Up for Monster Designs

In training an ML model on a massive chip design, the data can be so huge that it
overwhelms even powerful computers. A common approach is to break the design into
smaller pieces, but this can miss important connections between different parts of the
chip. MOR techniques can create simplified versions of circuits that are much faster to
simulate. By using these mini circuits, the ML model can analyse stress conditions
(voltage, current) in each section while still considering how everything interacts in the
bigger picture.

 Challenge 2: Guiding the Design Process with ML

Current ML models in chip design often act like assistants, suggesting improvements
without significantly reducing the overall design time. The goal is for ML to actively
guide design decisions and lead to faster creation of high-quality chips. By incorporating
ML models as constraints within design optimization problems, we can dramatically
reduce the number of possibilities the computer needs to explore. This translates to faster
turnaround times and better chip designs.

 Challenge 3: Optimizing Performance During Physical Design

Integrating ML models into the physical design stages (placement and routing of chip
elements) can improve performance. Existing models might not consider every factor that
affects performance. Working with Design Tools: Interacting with traditional chip design
tools for performance evaluation can be slow. ML models often contain valuable
information about how different design choices impact performance. This information
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Machine Learning in Advanced IC Design: A Methodological Survey.

can be harnessed to guide existing optimization algorithms, leading them towards high-
quality solutions faster. Additionally, using powerful computing platforms like GPUs can
significantly speed up the design process.

By addressing these challenges and focusing on scalability and design guidance, ML

has the potential to revolutionize IC design. Imagine creating high-quality chips faster
and more efficiently, all thanks to the power of machine learning. This future is closer
than ever before.

All these methods That are discussed in the paper have their own advantages and
disadvantages. Hence, it cannot be considered whether one method is good or bad. So
from comprehensive analysis of the research article a conclusion is drawn in the below
table 1 it shows the overall survey in a summarized way:

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Machine Learning in Advanced IC Design: A Methodological Survey.

Table 1 Summary of all the ML Models in the survey

Applications in
Methodology Description Strengths Weaknesses
IC Design
These - Regression
- Lower
traditional - Limited analysis: Modeling
computational
models learning relationships
cost compared
encompass capacity for between design
to deep learning.
various complex, non- parameters and
Shallow statistical and linear performance metrics
- Interpretable
Learning linear algebra relationships. (e.g., power
results: Model
Models techniques. consumption, delay).
behavior and
They are - May struggle - Classification
decision-making
typically less with high tasks: Categorizing
processes can be
complex than dimensional design elements or
more easily
deep learning data. identifying defects
understood.
approaches. (fault detection).

- Physical Design:
Placement
optimization:
Analyzing
placement
- Excellent at
CNNs are a configurations to
capturing local
powerful type - Can be minimize congestion
patterns and
of deep learning computationall or wirelength.
features within
architecture y expensive to - Design rule
an image or
specifically train for large checking (DRC):
Convolutional layout due to
designed to datasets. Identifying potential
Neural convolutional
work with grid- layout violations
Networks layers.
like data, - May require based on predefined
(CNNs)
making them significant data rules.
- Effective at
ideal for tasks pre-processing - Manufacturing
learning
involving for optimal Process Modeling:
hierarchical
spatial performance. Predicting yield or
representations
relationships. identifying potential
of data.
hotspots for failure
during the
manufacturing
process based on
chip layout images.

Graph Neural GNNs are a - Well-suited for - GNNs are a - Circuit Design:
Networks type of deep analyzing relatively new Topology synthesis:
(GNNs) learning model complex research area, Exploring different
designed to relationships and there are circuit structures to
work with within circuits still ongoing find the optimal
graph structured due to their efforts to design for a given
data. ability to develop more functionality.
Since circuit process graph efficient and Transistor sizing:
schematics can data. scalable Optimizing
be naturally - Can effectively architectures. transistor sizes

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Machine Learning in Advanced IC Design: A Methodological Survey.

within a circuit to
represented as meet performance
graphs, GNNs targets.
are well- capture long- - Design
positioned for range Verification:
tasks that dependencies in Analyzing circuit
involve the data. connectivity and
analyzing these identifying potential
circuits. bugs or errors within
the schematic.
Generative This category - Offer the - Generative - Physical Design:
Models (VAEs, encompasses ability to create models can be Mask optimization
GANs) models that can entirely new complex to for lithography:
learn from design options train and Generating
existing design or variations, require careful improved mask
data and expanding hyperparameter layouts that
generate new design tuning. - The compensate for
designs or exploration quality of process variations.
design capabilities. generated Standard cell
elements. Two designs might placement:
prominent - Can be used require Proposing new
examples are: for data additional placement
Variational augmentation, refinement or configurations based
Autoencoders generating human on existing library
(VAEs): VAEs synthetic data to intervention. cells.
learn a latent improve model
representation performance.
of design data
and can
reconstruct
existing designs
or generate new
variations based
on the learned
features.

Generative
Adversarial
Networks
(GANs): GANs
consist of two
competing
neural
networks: a
generator that
creates new
designs and a
discriminator
that tries to
distinguish real
designs from
generated ones.
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Machine Learning in Advanced IC Design: A Methodological Survey.

RL employs a - Design
unique Optimization:
approach where Device sizing:
an agent learns - RL algorithms Finding optimal
through trial can be transistor sizes for a
- Well-suited for
and error in a computationall circuit to achieve
complex design
simulated y expensive, desired performance
optimization
environment. especially for targets.
problems where
The agent large and
the relationship
interacts with complex design - Placement
between actions
the spaces. optimization:
and outcomes is
environment, Optimizing the
not easily
Reinforcement taking actions - Exploration placement of blocks
defined.
Learning (RL) and receiving vs. exploitation on a chip layout to
rewards based trade-off: minimize
- Can learn
on the Balancing congestion,
effective
outcomes. learning new wirelength, or power
strategies
Over time, the strategies consumption.
without the need
agent learns to (exploration)
for explicit
choose actions with exploiting - Clock tree
programming of
that lead to currently synthesis:
all design rules.
higher rewards, known good Generating efficient
enabling it to options. clock tree structures
discover for distributing
optimal design clock signals
strategies. throughout the chip.

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Machine Learning in Advanced IC Design: A Methodological Survey.

Chapter 4
RESULTS
The ever-growing complexity of integrated circuits (ICs) demands innovative
solutions for design automation and optimization. This survey explored the exciting
intersection of machine learning (ML) and advanced IC design, highlighting the immense
potential of ML to revolutionize this critical field:

 Reinforcement Learning (RL) has emerged as a powerful tool for tackling various
design challenges, from placement and routing to power management. RL agents
can learn optimal design strategies through trial and error within a simulated
environment.
 Value function-based methods provide a valuable framework for RL in IC design,
but limitations in convergence time and stability necessitate further research.
 Policy function-based methods offer an alternative approach, particularly for
problems with vast state and action spaces. However, challenges related to sample
efficiency and local optima require careful consideration during implementation.
 Scalability remains a hurdle for applying ML to massive industrial designs.
Promising solutions involve Model Order Reduction (MOR) techniques to create
smaller, faster-to-simulate circuits that capture essential information for effective
verification.
 Current ML models in IC design primarily function as assistants, suggesting
improvements without significantly reducing design time. Future advancements
lie in integrating ML models as constraints within the design optimization process,
leading to faster exploration of high-quality solutions.
 Performance-aware physical design with ML faces challenges in modelling
overall performance and interacting with existing Electronic Design Automation
(EDA) tools. Leveraging the gradient information within ML models and
deploying these approaches on high-performance computing platforms can offer
significant speed improvements.

The successful implementation of ML in IC design requires careful consideration

of several factors:

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Machine Learning in Advanced IC Design: A Methodological Survey.

 Choosing the right RL technique depends on the specific design task, data
availability, and state/action space size.
 Tailoring neural network architectures (actor and critic networks) to the design
problem can improve efficiency. Graph neural networks (GNNs) are particularly
effective for circuit schematics.
 Addressing sample efficiency is crucial. Techniques like pre-training and focusing
on relevant state space regions can help.
 Preventing local optima requires employing exploration techniques and diverse
initialization methods for the RL networks.
 Scalability and model compression techniques like knowledge distillation or
pruning can enable deployment on resource-constrained hardware.

The future of IC design is intricately linked with the advancements in machine

learning. By overcoming the current challenges and focusing on scalability, design
guidance integration, and performance-aware physical design, ML can revolutionize chip
creation:

 Faster Design Cycles: Imagine significantly reduced design times while

maintaining high-quality standards. ML-powered design automation can make this
a reality.
 Efficient Exploration: Exploration of the vast design space will become more
efficient, leading to the discovery of even better design solutions.
 Higher Quality Chips: ML can help ensure that chips meet all design
specifications and performance requirements.

Beyond these advancements, further research in interpretable ML models, efficient

hardware co-design, and security considerations will be crucial for the continued success
of machine learning in IC design. As both ML and IC design continue to evolve, their
synergy holds the promise of a future filled with even more powerful and sophisticated
chips that drive innovation across various industries.

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Machine Learning in Advanced IC Design: A Methodological Survey.

Chapter 5
CONCLUSION
The integration of machine learning (ML) into advanced integrated circuit (IC)
design signifies a promising frontier in chip creation, propelled by the escalating
intricacies of ICs demanding innovative design solutions. This survey delved into the
intersection of ML and advanced IC design, underscoring the transformative potential of
ML in this pivotal domain. Reinforcement Learning (RL) has emerged as a potent tool for
addressing diverse design challenges encompassing placement, routing, and power
management.

RL agents exhibit the capability to learn optimal design strategies through

iterative trial and error within simulated environments. While value function-based
methods furnish a robust framework for RL in IC design, challenges pertaining to
convergence time and stability necessitate further exploration. Alternatively, policy
function-based methods offer a viable approach, particularly suited for problems
characterized by extensive state and action spaces, albeit grappling with issues related to
sample efficiency and local optimal.

Scalability emerges as a formidable obstacle in applying ML to large-scale

industrial designs, with potential solutions involving Model Order Reduction (MOR)
techniques to craft smaller, faster-to-simulate circuits capturing essential design
information for effective verification. Presently, ML models in IC design predominantly
serve as aides, suggesting enhancements without significantly curtailing design duration.
Future strides hinge on integrating ML models as constraints within the design
optimization framework, facilitating expedited exploration of high-quality solutions.
However, the effective implementation of ML in IC design mandates meticulous
consideration of various factors encompassing RL technique selection, neural network
architecture tailoring, sample efficiency enhancement strategies, and mitigation of
scalability challenges through model compression techniques.

Envisioning the horizon, the marriage of ML and IC design holds the promise of
accelerated design cycles, streamlined exploration of the design space, and the assurance
of higher-quality chips meeting stringent performance standards. Beyond these
advancements, continued research in interpretable ML models, efficient hardware co-
design, and fortified security measures will be indispensable for the enduring success of

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Machine Learning in Advanced IC Design: A Methodological Survey.

ML in IC design, fostering a future characterized by even more potent and sophisticated

chips propelling innovation across diverse sectors.

REFERENCES
[1] B. Khailany et al., "Accelerating Chip Design with Machine Learning," in IEEE
Micro, vol. 40, no. 6, pp. 23-32, 1 Nov.-Dec. 2020.

[2] B. K. Joardar, T. K. Bletsch, and K. Chakrabarty, "Learning to Mitigate

Rowhammer Attacks," 2022 Design, Automation & Test in Europe Conference &
Exhibition (DATE), Antwerp, Belgium, 2022, pp. 564-567.

[3] A. Krizhevsky, I. Sutskever, and G. E. Hinton, “ImageNet classification with

deep convolutional neural networks,” in Proc. NIPS, 2012, pp. 1097–1105.

[4] K. Zhu et al., “GeniusRoute: A new analog routing paradigm using generative
neural network guidance,” in Proc. ICCAD, 2019, pp. 1–8.

[5] S. K. Mandal et al., “An energy-aware online learning framework for resource
management in heterogeneous platforms,” ACM Trans. Design Autom. Electron.
Syst., vol. 25, no. 3, pp. 1–26, May 2020

[6] Y. Li et al., “A circuit attention network-based actor– critic learning approach to

robust analog transistor sizing,” in Proc. MLCAD, 2021, pp. 1–6.

[7] M. Rapp et al., "MLCAD: A Survey of Research in Machine Learning for CAD
Keynote Paper," in IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, vol. 41, no. 10, pp. 3162-3181, Oct. 2022.

[8] K. I. Gubbi et al., “Survey of machine learning for electronic design automation,”
in Proc. GLSVLSI '22: Proceedings of the Great Lakes Symposium on VLSI
2022, pp. 513–518, June 2022.

[9] Huang et al., “Machine learning for electronic design automation: A survey,”
ACM Trans. Design Autom. Electron. Syst., vol. 26, no. 5, pp. 1–46, Jun. 2021.

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