IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 29, NO.

4, APRIL 2021 739

Frequency-Locked RF Power Oscillator With

43-dBm Output Power and 58% Efficiency
Sanghun Lee , Kisang Jung , Hak Seong Kim, Huan Nguyen, Thinh Nguyen, Luan Nguyen, Cuong Huynh ,
Kunhee Cho, Member, IEEE, and Jusung Kim , Member, IEEE

Abstract— This article presents the frequency-locked

high-power RF oscillator using a gallium nitride (GaN) high
electron mobility transistor (HEMT) amplifier and phase-locked
loop (PLL) for 2.4-GHz industrial, scientific, and medical
(ISM) band applications. The proposed architecture exploits
the GaN power amplifier in the positive-feedback loop, whereas
the desired phase shift for the target oscillating frequency is
regulated from the PLL. To the best of our knowledge, this
work is the first to employ the frequency locking scheme for
a high-power solid-state RF oscillator. A detailed analysis of
the oscillation conditions and the efficiency is provided. The
prototype circuit is implemented with hybrid phase shifters
and a fractional-N frequency synthesizer. The implemented RF
oscillator circuit operates from 2.3 to 2.575 GHz and achieves a
low phase noise of −131.8 dBc/Hz at a 1-MHz offset frequency.
The power efficiency of the proposed oscillator reaches 58%,
and the PLL incurs only 0.2% efficiency degradation.
Index Terms— Frequency lock, gallium nitride (GaN) high
electron mobility transistor (HEMT), high efficiency, high power,
industrial, scientific, and medical (ISM), oscillator, phase-locked
loop (PLL), phase shifter.
I. I NTRODUCTION
H IGH-POWER sources in the RF and microwave fre-
quency ranges are versatile in many applications in
industry and science [1], [2]. The relevant applications include
induction heating, electric welding, and RF lighting. During
the past several decades, continuous effort has been employed
to realize high-power sources with solid-state devices [3], [4]
and to increase the oscillation frequency of solid-state power
sources [5].
Manuscript received July 8, 2020; revised October 7, 2020 and
November 27, 2020; accepted January 27, 2021. Date of publication
February 12, 2021; date of current version April 1, 2021. This work was
supported by the Technology Innovation Program (or Industrial Strategic
Technology Development Program-ATC) (Commercialization of 100W-class
transceiver for compact radar system by localized development of Ka-band
GaN MMIC) funded by the Ministry of Trade, Industry & Energy (MOTIE,
South Korea) under Grant 10076892. (Corresponding author: Jusung Kim.)
Sanghun Lee, Kisang Jung, and Hak Seong Kim are with Wavepia Inc.,
Hwaseong 18469, South Korea.
Huan Nguyen, Thinh Nguyen, Luan Nguyen, and Cuong Huynh are with
the Department of Telecommunications Engineering, Ho Chi Minh City
University of Technology, Ho Chi Minh City 700000, Vietnam.
Kunhee Cho is with the School of Electronics Engineering, Kyungpook
National University, Daegu 41566, South Korea, and also with the School of
Electronic and Electrical Engineering, Kyungpook National University, Daegu
41566, South Korea.
Jusung Kim is with the Department of Electronics and Control Engi-
neering, Hanbat National University, Daejeon 34158, South Korea (e-mail:
jusungkim@hanbat.ac.kr).
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TVLSI.2021.3056720.
Digital Object Identifier 10.1109/TVLSI.2021.3056720
1063-8210 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
Fig. 1. Illustration of solid-state RF source with control electronics.
Furthermore, many studies have been conducted to improve
the dc-to-RF conversion efficiency of high-power RF sources
because it determines the thermal stress, which degrades the
reliability of the solid-state devices and increases the bill of
material related to heat management of high-power signal
sources. In [4], a class-F oscillator implemented with an MES-
FET device was designed to operate at a 1.6-GHz frequency,
while the authors of [5], [6] designed a class-E oscillator by
synthesizing the phase shift of the feedback network for the
desired oscillation frequency. The design criteria based on the
linear loop-gain analysis is provided in [7], [8] and ensures
the high efficiency of the oscillator. Nonlinear design tech-
niques were proposed in [2], [9] that employed harmonic
termination optimization based on the load–pull simulation.
Conversely, previous studies [2]–[7], [9] have demonstrated
the limited performance in either the output power level or
the oscillation frequency. They do not provide a means to
frequency-lock the oscillation frequency and, thus, cannot
provide fine resolution at their operating frequency.
Fig. 1 illustrates the microwave heating RF source with
solid-state devices configured by the low-cost control elec-
tronics (e.g., frequency control and power control). Using
solid-state RF sources could allow for some feedback of
information about the object being heated. It may be possible
to configure the system to measure forward and reverse powers
and, from this information, determine the optimum frequency
within the 2.4–2.5-GHz band for either cooking or heating
the object. An example of such a system would be an RF
source with a low-cost forward and reverse power detector
built-in. The food could initially be interrogated by a range
of frequencies using a low-power mode of operation. Based
on the results, the system would then select the optimum
frequencies for cooking the food.
Microwave heating uses the RF energy in the microwave
spectrum around 2.45 GHz to heat an item, and the
RF energy is traditionally supplied by a magnetron [10].

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740 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 29, NO. 4, APRIL 2021
Fig. 2. Block diagram of the proposed RF power oscillator.
However, a magnetron does not provide agile frequency con-
trol, rapid power change, and feedback from the environment.
On the other hand, frequency-locked solid-state RF sources
can offer the best frequency and power settings depending on
the objects to be heated. Also, it could allow the feedback
of information about the object and configure the system to
determine the optimum condition. For instance, the dielectric
constant of the material to be heated determines the voltage
standing wave ratio (VSWR) [10], and thus, it is desirable to
track the best frequency range for optimized VSWR.
Then, in this work, we propose a high-power solid-state
RF oscillator with a gallium nitride (GaN) high electron
mobility transistor (HEMT)-based power amplifier in the
positive-feedback loop, which is suitable for microwave heat-
ing applications around the 2.4-GHz industrial, scientific, and
medical (ISM) radio band. The feedback network includes ana-
log and digital phase shifters, which are regulated to provide
the desired operating frequency. The phase-locked loop (PLL)
circuit with the adaptive frequency calibration (AFC) scheme
first determines the 6-bit digital phase shifter (DPS) config-
uration to coarse-lock the oscillation frequency. Thereafter,
an analog phase shifter (APS) is employed to fine-tune the
oscillation frequency where the desired phase shift is set
by the PLL. The loop behavior and efficiency of the power
oscillator are described in detail, and we provide the design
guidelines for the proposed high-efficiency power oscillator
with a frequency lock.
This article is organized as follows. Section II provides a
system description followed by the power oscillator design
fundamentals. Section III gives the design and implementation
details. Section IV presents the measurement results. Finally,
Section V concludes the article.
II. P ROPOSED RF P OWER O SCILLATOR
A. System Description
The block diagram of the proposed RF power oscillator
is shown in Fig. 2. The oscillator is constructed with a
single-loop positive-feedback network where the feedforward
circuit is the GaN power transistor in the common-source
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TABLE I
D ESIGN PARAMETERS FOR THE F REQUENCY S YNTHESIZER
amplifier configuration, and the feedback network is composed
of the hybrid phase shifter and the directional couplers. Two
directional couplers are cascaded to provide the feedback
signal for the power oscillator and to couple the feedback
signal to the fractional-N synthesizer for frequency locking.
The hybrid phase shifter is formed by cascading the analog
and digital phase shifters for fine and coarse tuning of the
oscillator output frequency, respectively.
The AFC circuit firstly compares the power oscillator’s
output frequency with the on-chip counter derived from the
crystal oscillator (XO) and sets the desired operating frequency
by fixing the 6-bit digital codes for the DPS. The decision
regarding the digital codes is then made sequentially from the
most significant bit to the least significant bit using the binary
search algorithm until the two comparison frequencies become
identical. The tuning voltage of the APS then fine-tunes the
operating frequency of the power oscillator whose value is
determined from the loop filter output voltage.
The parameters for the frequency synthesizer in the Type-II
PLL configuration [11] are listed in Table I. The phase noise
performance of the GaN power oscillator is superior with a
high output power [12]. The loop bandwidth is set at 1/1000
of the reference frequency, which is significantly smaller
than Gardner’s stability limit (<( f ref /10)) [13], whereas the
noise contribution is minimized due to the third-order MASH
sigma–delta modulator (SDM) for fractional-N frequency
synthesis. The divider chain is composed of the divide-by-
2 prescaler and multimodulus (MM) divider, providing a
divided ratio of 74–78. The design and implementation details
of the core building blocks are further described in Section III.
Fig. 3 shows the simulated transient response of the fre-
quency lock acquisition with the proposed RF power oscillator.
A coarse frequency lock is initially acquired by fixing the DPS
bits using the AFC. Results are shown in Fig. 3, which depicts
the code transition from 32 (the initial value) to 28 (the final
settled value) after six successive approximation processes.
Once the AFC process is complete, the “AFC Done” signal is
turned ON, and the fine frequency lock is initiated. The total
acquisition time is 450 μs, with 200 and 250 μs for coarse
and fine frequency lock, respectively.
B. Design Fundamentals
The oscillation frequency and the gain (sensitivity) of the
power oscillator can be derived from the loop gain [14].
LEE et al.: FREQUENCY-LOCKED RF POWER OSCILLATOR WITH 43-dBm OUTPUT POWER AND 58% EFFICIENCY 741

Fig. 3. Simulated transient response of the PLL lock acquisition procedure.

where φdc,1 and φdc,2 are the phase delays to the transmitted
and coupled ports of the directional coupler, respectively, while
φps,dig and φps,ana are the phase delays from the DPS and
the APS, respectively. It should be noted that the gain (loss)
of each block is a positive number, and the phase delay of
each block includes a sign-inversion (e.g., φamp > π due
to the inverting amplification). From condition (2), the gain
of the GaN power amplifier has to be sufficiently large to
overcome the losses because of the directional couplers and
phase shifters.
The phase delay due to the phase shifters is governed by
the fine and coarse frequency loop; therefore, the oscillation
frequency is adjusted based on the added phase shift due to
the phase shifters. The voltage gain and phase delay due to
Fig. 4. Block diagram for the computation of the RF power oscillator loop
gain. the feedforward amplifier are given by

Based on the block diagram shown in Fig. 4, one can construct Aamp = gm · R L (5)
the conditions for oscillation. First, the voltage gain of the φamp = π + arctan(ωτ1 ) + arctan(ωτ2 ) (6)
amplifier, Aamp , and the insertion loss of the feedback network
(β(ω)) must satisfy where τ1 = R L · C O and τ2 = (1/gm ) · CY are time
constants arising from the amplifier load impedance and the
|Aamp · β(ω)| ≥ 1. (1)
transconductance. The phase condition in (2) can then be
Thus, with the given feedback network, the first (gain) written as
condition can be expressed as follows:
arctan(ωτ1 ) + arctan(ωτ2 ) = φfix − φps = φc . (7)
1
Aamp ≥ √ (2)
C · 1 − C · Aps,dig · Aps,ana
2 The fixed phase delays are lumped into φfix , while φps
denotes the amalgamated phase shift due to the analog
where C is the coupling coefficient due to the directional
and digital phase shifters. The oscillation frequency (ωo )
coupler, and Aps,dig ( Aps,ana ) represents the voltage gain or loss
of the proposed RF power oscillator and the sensitivity
of the digital (analog) phase shifter. Second, the total phase
(K osc ) due to the controllable phase shift are then determined
shift forming the positive-feedback loop must satisfy
 as
φi = 2nπ. (3) 
− cot φc (τ1 + τ2 ) + cot2 (φc )(τ1 + τ2 )2 + 4τ1 τ2
i ωo =
2τ1 τ1
Again, the second (phase) condition can be reconstructed as (8)
follows: ∂ω −1
K osc = ≈    . (9)
φamp + φdc,1 + φdc,2 + φps,dig + φps,ana = 2nπ (4) ∂φps (τ1 + τ2 ) 1 − ω2 τ12 − τ1 τ2 + τ22

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742 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 29, NO. 4, APRIL 2021

The efficiency of the RF power oscillator is further cal-

culated from the block diagram shown in Fig. 4. Assuming
the same reference impedance at each node of the RF power
oscillator, the oscillator efficiency (ηosc ) is written as
Posc
ηosc =
Pdc,amp + Pdc,synth
(1 − C 2 ) · Pout
= (10)
Pdc,amp + Pdc,synth
where Pout and Posc represent the signal power at the feedfor-
ward amplifier output and the oscillator output, respectively.
The dc powers for the active circuits, the feedforward amplifier
and the fractional-N synthesizer, are denoted as Pdc,amp and
Pdc,synth , respectively. In addition, the power-added efficiency
of the power amplifier can be derived as
Pout − Pin
ηamp =
Pdc,amp Fig. 5. Schematic of the hybrid phase shifter as a combination of the APS
  and the 6-bit DPS.
Pout 1 − C 2 · (1 − C 2 ) · A2ps,dig · A2ps,ana
= . (11)
Pdc,amp
Therefore, we can derive the following relationship in the
steady state when the loop gain of the power oscillator
converges to unity ( Aamp · C · (1 − C 2 )1/2 · Aps,dig · Aps,ana = 1):

Pdc,amp
ηosc = ηamp ·
Pdc,amp + Pdc,synth
1 − C2
·
1 − C 2 · (1 − C 2 ) · A2ps,dig · A2ps,ana

Pdc,amp
≈ ηamp · (1 − C ) ·
2
. (12)
Pdc,amp + Pdc,synth
Equation (12) enables several strategies to design
high-efficiency power oscillators. First, feedforward
components are critical to ensure high efficiency. The
power-added efficiency of an amplifier (ηamp ) must be
optimized. The coupling factor (C) of the directional coupler
in the feedforward path must be minimized while satisfying
the condition in (1). Second, the gain of the feedforward
amplifier is also critical although the factor, Aamp , is not
Fig. 6. Detailed schematic of the DPS: (a) Switched LC network, (b) HP/LP
shown in (12). In other words, Aamp dictates the allowed network, (c) APN, and (d) two-stage APN.
minimum for the coupling factor, C. Finally, losses in the
feedback path (β(ω)) are not detrimental to the oscillator’s The reflective-type phase shifter (RTPS) [16] exhibits wide-
high-efficiency operation. Thus, the use of the additional band characteristics but still suffers from a large area at the
directional coupler in the feedback and cascaded phase shifters desired operating frequency range. The active phase shifter
is not critical for the efficiency of the power oscillator. offers a compact footprint but consumes large power with a
low-linearity performance [17]. All these considerations led
III. D ESIGN AND I MPLEMENTATION D ETAILS
us to adopt the lumped-element-based phase shifter realized
A. Phase Shifters with a combination of different phase lag/lead networks for
Herein, the phase shifter is based on combinations of the low insertion loss and phase stability.
switched LC, all-pass network (APN), and high-pass/low- Fig. 5 shows the top-level schematic of the hybrid phase
pass (HP/LP) network. The 250-nm gallium arsenide (GaAs) shifter comprising a two-stage APS and a 6-bit DPS. The APS
process is utilized for the implementation of lumped-element- is realized with a bridge-T APN with stagger-tuned center
based phase shifters. The distributed phase shifter using the frequencies for a flat phase response. The 6-bit DPS comprises
transmission line (TL) loaded by varactors [15] can offer a series connection of different phase lead/lag networks with
a low insertion loss. However, at the desired frequency of its detailed schematic shown in Fig. 6. It consists of six unit
ISM bands around 2.4 GHz, the distributed phase shifter cells that provide phase shifts of 180◦ , 5.625◦, 11.25◦, 22.5◦ ,
occupies a huge die area, and the number of varactors is large. 45◦ , and 90◦ . The order of the unit cells is selected based

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LEE et al.: FREQUENCY-LOCKED RF POWER OSCILLATOR WITH 43-dBm OUTPUT POWER AND 58% EFFICIENCY 743

TABLE II
E LEMENT VALUES FOR DPS

Fig. 7. Schematic of the phase-frequency detector.

Fig. 9. Photograph of the frequency-locked RF power oscillator.

Fig. 10. Micrograph of the APS.

Fig. 8. Schematic of the charge pump and loop filter.

on the loading effects. The APS provides 30◦ of the phase

shift range over 0–1.8 V of the varactor tuning range. The
DPS performs a phase shift from 0◦ to 360◦ with a minimum
phase step of 5.625◦ (=360◦ /26 ). Element values for the APS
are illustrated in Fig. 5, and the element values for DPS are
enumerated in Table II. Fig. 11. Micrograph of the DPS.

B. Building Blocks of the Frequency Synthesizer
The sequential phase- and frequency-detector (PFD) circuit
in Fig. 7 is used with tristate outputs (UP · DOWN = 1),
which drives the charge pump in the Type-II PLL config-
uration. To eliminate the dead zone due to the insufficient
loop gain under a small phase difference, the PFD circuit has
an adjustable delay chain providing 200 ps to 1 ns in the
reset-signal path. Fig. 8 shows the simplified schematic of the
charge pump used whose output charges (discharges) the loop
filter and, thus, determines the control voltage for the APS
circuit in Fig. 5. The current-steering type is utilized for the
high-speed operation of the charge pump. The error amplifier
with a loop gain of 50 dB and the compensation capacitor
(C = 3.5 pF) virtually short the two outputs (V R and VC )
to minimize the current mismatch in the charge pump output
current (Iout ). The design parameters of the charge pump and
loop filter are provided in Table I.
IV. M EASUREMENT R ESULTS
A photograph of the frequency-locked RF power oscillator
is shown in Fig. 9, which includes the phase shifters
(analog and digital) and frequency synthesizer depicted in
Figs. 10–12. The phase shifters are fabricated in a 250-nm
GaAs process, whereas the frequency synthesizer chip is
fabricated in TSMC 0.18-μm CMOS technology. Although
single die (chip) CMOS realization is desirable, the need for a

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744 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 29, NO. 4, APRIL 2021
Fig. 12. Micrograph of the frequency synthesizer fabricated in a 0.18-μm
CMOS process.
Fig. 13. Micrograph of (a) fabricated GaN HEMT transistor and (b) imple-
mented power amplifier module.
Fig. 14. Measured GaN HEMT amplifier performance: (a) output power
versus input power and (b) power-added efficiency versus output power.
Fig. 15. Measured frequency-locked power oscillator output frequency versus
the input codes of the DPS.
high-power amplifier and highly linear phase shifter prohibits
this approach in our work. Thus, a hybrid implementation
(amplifier in GaN, phase shifters in GaAs, and the frequency
synthesizer in CMOS) was adopted.
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Fig. 16. Measured output power spectrum of the frequency-locked power
oscillator operating at 2.4 GHz.
Fig. 17. Measured single sideband phase noise of the free-running power
oscillator.
Fig. 18. Measured single sideband phase noise of the frequency-locked power
oscillator at 2.4 GHz.
TABLE III
B REAKDOWN OF P OWER C ONSUMPTION
The supply voltage of the frequency synthesizer is 5 V, but
internal building blocks operate with a 1.8-V supply generated
from an on-chip low dropout regulator (LDO). The loop
filter output from the synthesizer provides 0–1.8 V of control
voltage to APS, while the DPS requires −5/0 V control voltage
to turn OFF / ON the relevant switches. Then, a level shifter is
required to interface 6-bit AFC digital codes to DPS.
Commercial directional couplers (RCP2650Q10 and
CMX30P20 from RN2 technologies) are utilized to provide
the feedback signal for the power oscillator and to couple the
LEE et al.: FREQUENCY-LOCKED RF POWER OSCILLATOR WITH 43-dBm OUTPUT POWER AND 58% EFFICIENCY
TABLE IV
C OMPARISON TO R ECENTLY P UBLISHED W ORKS
feedback signal to the fractional-N synthesizer. The coupling
coefficients for these couplers are 10 and 20 dB, respectively.
The prescaler requires an additional attenuator not to receive
an excessively large power, which is implemented within the
CMOS chip. It should be noted that the design fundamentals
in Section II-B assume the equal coupling coefficient (C)
to provide the intuition and simplicity while not losing the
generality of the presented theory. The GaN power transistor,
phase shifters, directional couplers, and frequency synthesizer
are all mounted on a common FR-4 printed circuit board
(PCB).
A separate GaN HEMT power amplifier module is assem-
bled, and Fig. 13 shows the micrograph of the fabricated
GaN device and the implemented PA module. From the
load–pull simulation of unmatched GaN HEMT transistor,
optimum source/load impedances for maximum efficiency
and output power are obtained to be 1.45 − j 2.785 and
7.8 − j 1.735 , respectively. LC matching networks are
inserted on PCB, where inductors are realized with microstrip
lines and capacitors are lumped components. Its large signal
gain and efficiency are measured over 2.4–2.5-GHz frequency
range, as shown in Fig. 14. The power gain and power-added
efficiency show greater than 16 dB and 64.9%, respectively,
at a saturated output power (Psat ). At the gate voltage (VGS ) of
−2.283 V, the transistor shows a quiescent current of 100 mA
at a 28-V drain voltage (VDS ). We provided the key design
approaches derived from (12). From the measured forward
amplifier performance, it can be directly induced that the
efficiency of the overall oscillator is dictated by the highly
efficient feedforward component and small coupling factor of
the directional coupler in the feedforward path.
The 6-bit digital codes are swept, and the output frequency
of the power oscillator is measured, whose results are depicted
in Fig. 15. The measured frequency locking range is 275 MHz,
with the minimum and maximum at 2.3 and 2.575 GHz,
respectively. Fig. 16 shows the output power spectrum of the
proposed power oscillator under the frequency-locked state at
2.4 GHz. The output power of the proposed power oscillator
exceeds the upper power limit of the spectrum analyzer used
for the measurement. The attenuator (WA81, Weinschel) with
a fixed attenuation factor of 40 dB is then cascaded to step
down the output power within the spectrum analyzer’s power
limit. The output power is measured to be 43 dBm, where the
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745
effects of the attenuation (40 dB) and the input/output cable
loss (3.5 dB) are deembedded.
The single sideband (SSB) phase noise of the fabri-
cated oscillator is measured under both free-running and
frequency-locked conditions. The measured results for both
cases are shown in Figs. 17 and 18. The measured phase
noise of the free-running oscillator is −38.6 dBc/Hz at a 1-
kHz offset frequency, whereas the phase noise at a 1-MHz
offset frequency is −129.6 dBc/Hz. When the oscillator is
frequency locked at 2.4 GHz, the phase noise is measured to
be −71.5 dBc/Hz and −131.8 dBc/Hz at 1-kHz and 1-MHz
offset frequencies, respectively.
The breakdown of the measured power consumption is
depicted in Table III. With the measured output power
of 43 dBm, the efficiency of the proposed oscillator reaches
58.2% and 58%, while the oscillator is free-running and
frequency locked, respectively.
The performance of the frequency-locked high-power RF
oscillator for the 2.4-GHz ISM band compared with the
reported research efforts is shown in Table IV. Although higher
efficiency is reported in [2], [18], these works operate at
sub-1-GHz frequency range. The work in [5] demonstrates
the highest operating frequency but shows a limited output
power of 26.7 dBm (0.47 W). Kim et al. [19] report similar
operating frequency and efficiency as our work; however,
a bulky mechanical phase shifter is utilized. Our work provides
a means to frequency-lock the oscillation frequency and, thus,
can provide a fine resolution.
V. C ONCLUSION
In this work, the frequency-locked RF power oscillator using
a GaN HEMT amplifier and PLL is presented and verified
for the 2.4-GHz ISM band frequency range. The GaN power
amplifier is configured in a positive-feedback loop with hybrid
phase shifters in the feedback path. The adjustable phase
shifter is regulated from the PLL, and thus, the desired output
frequency can be locked with fine-tuning frequency steps.
To the best of our knowledge, this work is the first to employ
the frequency locking scheme for a high-power solid-state RF
oscillator.
The oscillation condition and the efficiency of the power
oscillator are theoretically analyzed. The measurements of the
proposed oscillator show an output power of 43 dBm, an effi-
746 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 29, NO. 4, APRIL 2021
ciency of 58%, including the synthesizer’s power consumption,
and a locking range of 2.3–2.575 GHz.
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