7. Write down a Verilog Code to implement ALU.

// Arithmetic and Logical Unit verilog code

module ALU(x,y,sel,z);
input [7:0]x,y;
output reg [15:0]z;
input [2:0]sel;
parameter ADD=3'b000;
parameter SUB=3'b001;
parameter MUL=3'b010;
parameter DIV=3'b011;
parameter AND=3'b100;
parameter OR=3'b101;
parameter NOT1 =3'b110;
parameter NOT2 =3'b111;
always@(*)
case(sel)
ADD: z=x+y;
SUB: z=x-y;
MUL: z=x*y;
DIV: z=x/y;
AND: z=x&&y;
OR: z=x||y;
NOT1: z=!x;
NOT2: z=!y;
endcase

endmodule

8. Write a Verilog code to design a 4-bit parallel adder.

Verilog Code:
Full Adder Module

1module fulladder(a,b,ic,o,oc);
2
3input a,b,ic;
4
5output o,oc;
6
7assign o = (~ic & ((a & ~b) | (~a & b)) ) | (ic & ~((a & ~b) | (~a & b)) );
8
9assign oc = (a & b) | (b & ic) | (ic & a);
10
11endmodule

Parallel Adder Module

1module main(in1,in2,ic,out,oc);
2
3input [3:0]in1;
4
5input [3:0]in2;
 6
7
input ic;
8
9output [3:0]out;
10
11output [3:0]oc;
12
13fulladder fa1(in1[0],in2[0],ic,out[0],oc[0]);
14
15fulladder fa2(in1[1],in2[1],oc[0],out[1],oc[1]);
16
17fulladder fa3(in1[2],in2[2],oc[1],out[2],oc[2]);
18
19fulladder fa4(in1[3],in2[3],oc[2],out[3],oc[3]);
20
21endmodule

9. Write a Verilog code to design a 4:1 Multiplexer.

1. Verilog Code:
module mux (in0, in1, in2, in3,sel, out);
input in0,in1,in2,in3;
input [1:0] sel;
output reg out;
always@(in0 or in1 or in2 or in3 or sel)
begin
if (sel==2’b00)
out = in0;
else if (sel==2’b01)
out =in1;
else if (sel==2’b10)
out =in2;
else
out = in3;
end
endmodule
In this example, the mux module has four inputs (in0,in1,in2,in3), two control inputs
(sel[1:0]), and one output (out). The output is determined by the values of the
control inputs (sel). If sel is 2'b00, then the output is equal to the first input (in0).
If sel is 2'b01, then the output is equal to the second input (in1). If sel is 2'b10,
then the output is equal to the third input (in2). If sel is 2'b11, then the output is
equal to the fourth input (in3).
The if-else statement is a common control flow statement used in Verilog to
implement conditional logic. In this example, the if-else statement is used to compare
the control inputs to the possible selection values and assign the output accordingly.

10. Write a Verilog code to design a 1:8 Demultiplexer.

module Demultiplexer(in,s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7);
input in,s0,s1,s2;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0=(in & ~s2 & ~s1 &~s0),
d1=(in & ~s2 & ~s1 &s0),
d2=(in & ~s2 & s1 &~s0),
d3=(in & ~s2 & s1 &s0),
d4=(in & s2 & ~s1 &~s0),
d5=(in & s2 & ~s1 &s0),
d6=(in & s2 & s1 &~s0),
d7=(in & s2 & s1 &s0);
endmodule