5 4 3 2 1

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D D

Loveland Schematics
Skylake-U
C 2015-09-18 C

REV : A00

B B

A DY : None Installed <Variant Name> A

UMA: UMA only installed Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

OPS: DISCRTE OPTIMUS installed Title

Cover Page
Size Document Number Rev
A3
Loveland SKL-U A00
Date: Friday, September 18, 2015 Sheet 1 of 105
5 4 3 2 1
 5 4 3 2 1

CHARGER
BQ24780RUYR 44
Project code:
INPUTS OUTPUTS
Love14 SKL --> 4PD060010001
Love15 SKL --> 4PD061010001
Loveland SKL-U Block Diagram AD+
BT+
DCBATOUT

PCB P/N: 14291 SYSTEM DC/DC

RT6576DGQW 45
Revision: A00 INPUTS OUTPUTS
Vinafix.com 3D3V_AUX_S5
5V_PWR_2
DCBATOUT 5V_S5
D
VGA DB D

3D3V_S5
DP/VGA Converter
GPU Intel CPU DDI2 REALTEK RTD2168-CGT VGA VGA Conn. CPU Core Power
NCP81208MNTXG 46~50
VRAM(DDR3L) *4 NVDIA IOBD 6 IOBD 6
PCIE x 4 Skylake U 2+2U NCP81382MNTXG X2
2GB N16V-GM-S
25W NCP81253MNTBG
78,79
DDR3L 15W (UMA&DIS)
INPUTS OUTPUTS
73,74,75,76,77
DCBATOUT VCC_CORE
DIS only DCBATOUT +VCCGT
IO Board DCBATOUT +VCCSA
SKL PCH-LP USB2.0 x 1 USB2(USB2.0)
IOBD 4 DDR3L SUS
DDR3L 10 USB 2.0/1.1 ports TPS51716RUKR 51
1600 DDR3L 1333/1600MHz Channel A 6 USB 3.0 ports INPUTS OUTPUTS
High Definition Audio CardReader DCBATOUT 1D35V_S3
SODIMM A USB2.0 x 1 SD Card Slot
12
3 SATA ports Realtek 0D675V_S0
6 PCIE ports RTS5170
LPC I/F CPU DCDC-V1D00A
DDR3L 53
ACPI 5.0 SY8208DQNC
1600 DDR3L 1333/1600MHz Channel B
INPUTS OUTPUTS
SODIMM B DCBATOUT 1D0V_S5
C 12 USB2.0 C
FRINGERPRINT LDO-V1D5V
NB-2020-U 92 S-1339D15-M5001 54
INPUTS OUTPUTS
14"/15" LCD eDP 3D3V_S5 1D5V_S0
55
PCIE x 1 NGFF WLAN LDO-V1D8V
802.11a/b/g/n APL5930KAI-TRG 54
Touch Panel USB2.0 x 1 BT V4.0 combo INPUTS OUTPUTS
USB2.0 x 1 AC 3160 61 3D3V_S5 1D8V_S5
IR Camera 5V/3V S0
USB2.0 x 1 G5016KD1U 40
Digital MIC 55 INPUTS OUTPUTS
5V_S5 5V_S0

SM Bus Free Fall Sensor 3D3V_S5 3D3V_S0

ST LNG2DM 67 VCCSTG
M5938ARD1U 40
RJ45 LAN 10/100/1000 INPUTS OUTPUTS
PCIE x 1
Conn. 32 RTL8111G 31
HDD P11 5V_S5 +VCCIO
+VCCSTG

VCCST
M5938ARD1U 40
B
SATA(Gen3) x 1 HDD B
HDMI V1.4a 57
DDI1 60
INPUTS OUTPUTS
5V_S5 +V1.00U_CPU
+VCCST_CPU
LPC BUS LPC debug port
Left side
68 PCB LAYER
USB2.0 x 1 L1:Top
USB1(USB3.0) Thermal
L2:VCC
L3:Signal
35,36
USB3.0 x 1 KBC SMBUS NUVOTON L4:Signal
NCT7718W 26 L5:GND
SMSC L6:Bottom
MEC1404-NU-GP
24 FAN
Left side 26
USB2.0 x 1
USB3(USB3.0) SPI
35,36
USB3.0 x 1
PS2 Int. KB
Flash ROM
65
16MB 25
SPI
A A

2CH SPEAKER HDA TPM 2.0

NPCT650JAAYX 91
(2CH 2W/4ohm) CODEC
HDA PrecisionTouch pad <Core Design>
Realtek
ALC3246 27
I2C 65 Wistron Corporation
29 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
29 MIC_IN/GND
Title
Universal Jack Block Diagram
HP_R/L Size Document Number Rev
A2 Loveland SKL-U <RevCode>
Date: Tuesday, September 15, 2015 Sheet 2 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

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C C

(Blanking)

B B

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 3 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

#544669 CRB Rev0.52

Vinafix.com +VCCST_CPU

1
D D
R419

+VCCSTG
+VCCSTG = 1.0 V 1KR2J-1-GP

2
R420
PCH_THERMTRIP 1
DY 2 H_THERMTRIP# [40]

1
R401 Do Not Stuff
[PECI] and [PROCHOT#] Rb 1KR2J-1-GP
TP401 CPU1D 4 OF 20
Impedance control: 50 ohm
Do Not Stuff

2
1 H_CATERR# D63 SKYLAKE_ULT
CATERR#
[24] H_PECI A54 PECI
Do Not Stuff 1 2 R404 H_PROCHOT#_R_R 1 R403 2 H_PROCHOT#_R C65 JTAG
[24,43,44,46] H_PROCHOT# PROCHOT#
499R2F-2-GP PCH_THERMTRIP C63
Ra THERMTRIP#
Do Not Stuff TP402 1SKTOCC# A65 SKTOCC# PROC_TCK B61 XDP_TCLK [99]
[99] XDP_BPM[3:0] CPU MISC PROC_TDI D60 XDP_TDI [99]
XDP_BPM0 C55 A61 XDP_TDO_CPU [99]
XDP_BPM1 BPM#[0] PROC_TDO
#543016 Rev0.7: Ra = 500 ohm / Rb = 1k ohm D55 BPM#[1] PROC_TMS C60 XDP_TMS [99]
#544669 Rev0.52: XDP_BPM2 B54 B59 XDP_TRST# [99]
XDP_BPM3 BPM#[2] PROC_TRST#
Ra = 56 ohm (TO BE CHANGED TO 100 OHMS) / Rb = 62 ohm and 150 ohm C56 BPM#[3]
Do Not Stuff TP403 1 GPP_E3/CPU_GP0 A6 B56 PCH_JTAG_TCK [99]
C GPP_E3/CPU_GP0 PCH_JTAG_TCK C
[24,55] TOUCH_PANEL_INTR# A7 GPP_E7/CPU_GP1 PCH_JTAG_TDI D59 PCH_JTAG_TDI [99]
[24,65] INT_TP# Do Not Stuff 1 2 R2045 TOUCHPAD_INTR# BA5 A56
GPP_B3/CPU_GP2 PCH_JTAG_TDO PCH_JTAG_TDO [99]
TP404 1 GPP_B4/CPU_GP3 AY5 C59 PCH_JTAG_TMS [99]
Do Not Stuff GPP_B4/CPU_GP3 PCH_JTAG_TMS
PCH_TRST# C61 XDP_TRST# [99]
2 1 CPU_POPIRCOMP AT16 A59 XDP_TCK_JTAGX [99]
49D9R2F-GP 2 R412 PCH_POPIRCOMP PROC_POPIRCOMP JTAGX
1 AU16 PCH_OPIRCOMP
49D9R2F-GP R413 H66 OPCE_RCOMP
H65 OPC_RCOMP

SKYLAKE-GP-U

071.SKYLA.000U +VCCSTG = 1.0 V

+VCCSTG

(#543016) PROCHOT# Routing Guidelines

XDP_TMS 1 DY 2
XDP_TDI Do Not Stuff 1 DY 2 R421
Do Not Stuff R422
XDP_TDO_CPU 1 DY 2
B Do Not Stuff R423 B

PCH_JTAG_TDI 1 2
51R2J-2-GP R408
PCH_JTAG_TDO 1 2
51R2J-2-GP R409
PCH_JTAG_TMS 1 2
51R2J-2-GP R416
XDP_TCK_JTAGX 1 DY 2
Do Not Stuff R417

XDP_TRST# R402 2 Do Not Stuff

R406
1 DY
XDP_TCLK 1 2 51R2J-2-GP
PCH_JTAG_TCK R407 1 DY 2 Do Not Stuff

M1,2,3,4,5: <3 inches

M6: 1-11 inches <Core Design>
MCPU: 0.3-1.5 inches
A
Mt <0.3 mils A
Main route(M1+M2+M3+M4+M5+M6+MCPU): 1-12 inches Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU_(JTAG/CPU SIDE BAND)
Size Document Number Rev
Custom A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 4 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

DDR3L ball type: Interleaved Type
[12] M_A_DQ[63:0]
[13] M_B_DQ[63:0]

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CPU1C 3 OF 20
CPU1B 2 OF 20

SKYLAKE_ULT M_A_DQ32 AY39 SKYLAKE_ULT AN45

M_A_DQ0 M_A_DQ33 DDR0_DQ[32]/DDR1_DQ[0] DDR1_CKN[0] M_B_CLK#0 [13]
AL71 AU53 AW39 AN46
M_A_DQ1 DDR0_DQ[0] DDR0_CKN[0] M_A_CLK#0 [12] M_A_DQ34 DDR0_DQ[33]/DDR1_DQ[1] DDR1_CKN[1] M_B_CLK#1 [13]
AL68 AT53 AY37 AP45
M_A_DQ2 DDR0_DQ[1] DDR0_CKP[0] M_A_CLK0 [12] M_A_DQ35 DDR0_DQ[34]/DDR1_DQ[2] DDR1_CKP[0] M_B_CLK0 [13]
AN68 AU55 AW37 AP46
M_A_DQ3 DDR0_DQ[2] DDR0_CKN[1] M_A_CLK#1 [12] M_A_DQ36 DDR0_DQ[35]/DDR1_DQ[3] DDR1_CKP[1] M_B_CLK1 [13]
AN69
DDR0_DQ[3] DDR0_CKP[1]
AT55
M_A_CLK1 [12] M_A_DQ[32:39] BB39
DDR0_DQ[36]/DDR1_DQ[4]
M_A_DQ[0:7] M_A_DQ4 AL70 M_A_DQ37 BA39 AN56
M_A_DQ5 DDR0_DQ[4] M_A_DQ38 DDR0_DQ[37]/DDR1_DQ[5] DDR1_CKE[0] M_B_CKE0 [13]
AL69 BA56 BA37 AP55
M_A_DQ6 DDR0_DQ[5] DDR0_CKE[0] M_A_CKE0 [12] M_A_DQ39 DDR0_DQ[38]/DDR1_DQ[6] DDR1_CKE[1] M_B_CKE1 [13]
AN70 BB56 BB37 AN55
M_A_DQ7 DDR0_DQ[6] DDR0_CKE[1] M_A_CKE1 [12] M_A_DQ40 DDR0_DQ[39]/DDR1_DQ[7] DDR1_CKE[2]
AN71 AW56 AY35 AP53
M_A_DQ8 DDR0_DQ[7] DDR0_CKE[2] M_A_DQ41 DDR0_DQ[40]/DDR1_DQ[8] DDR1_CKE[3]
AR70 AY56 AW35
M_A_DQ9 DDR0_DQ[8] DDR0_CKE[3] M_A_DQ42 DDR0_DQ[41]/DDR1_DQ[9]
AR68 AY33 BB42
M_A_DQ10 DDR0_DQ[9] M_A_DQ43 DDR0_DQ[42]/DDR1_DQ[10] DDR1_CS#[0] M_B_CS#0 [13]
AU71 AU45 AW33 AY42
M_A_DQ11 DDR0_DQ[10] DDR0_CS#[0] M_A_CS#0 [12] M_A_DQ44 DDR0_DQ[43]/DDR1_DQ[11] DDR1_CS#[1] M_B_CS#1 [13]
AU68
DDR0_DQ[11] DDR0_CS#[1]
AU43
M_A_CS#1 [12] M_A_DQ[40:47] BB35
DDR0_DQ[44]/DDR1_DQ[12] DDR1_ODT[0]
BA42
M_B_DIMB_ODT0 [13]
M_A_DQ[8:15] M_A_DQ12 AR71 AT45 M_A_DQ45 BA35 AW42
M_A_DQ13 DDR0_DQ[12] DDR0_ODT[0] M_A_DIMA_ODT0 [12] M_A_DQ46 DDR0_DQ[45]/DDR1_DQ[13] DDR1_ODT[1] M_B_DIMB_ODT1 [13]
AR69 AT43 BA33
M_A_DQ14 DDR0_DQ[13] DDR0_ODT[1] M_A_DIMA_ODT1 [12] M_A_DQ47 DDR0_DQ[46]/DDR1_DQ[14] M_B_A5
AU70 BB33 AY48
M_A_DQ15 DDR0_DQ[14] M_A_A5 M_B_DQ32 DDR0_DQ[47]/DDR1_DQ[15] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] M_B_A9
AU69 BA51 AU40 AP50
M_B_DQ0 DDR0_DQ[15] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] M_A_A9 M_B_DQ33 DDR1_DQ[32]/DDR1_DQ[16] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] M_B_A6
AF65 BB54 AT40 BA48
M_B_DQ1 DDR1_DQ[0]/DDR0_DQ[8]DDR0_DQ[16] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] M_A_A6 M_B_DQ34 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] M_B_A8
AF64 BA52 AT37 BB48
M_B_DQ2 DDR1_DQ[1]/DDR0_DQ[9]DDR0_DQ[17] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] M_A_A8 M_B_DQ35 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] M_B_A7
AK65 AY52 AU37 AP48
M_B_DQ3 DDR1_DQ[2]/DDR0_DQ[10]DDR0_DQ[18] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] M_A_A7 M_B_DQ36 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
AK64
DDR1_DQ[3]/DDR0_DQ[11]DDR0_DQ[19] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
AW52 M_B_DQ[32:39] AR40
DDR1_DQ[36]/DDR1_DQ[20] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
AP52 M_B_BS2 [13]
M_B_DQ[0:7] M_B_DQ4 AF66 AY55 M_B_DQ37 AP40 AN50 M_B_A12
DDR1_DQ[4]/DDR0_DQ[12]DDR0_DQ[20] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] M_A_BS2 [12] DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
M_B_DQ5 AF67 AW54 M_A_A12 M_B_DQ38 AP37 AN48 M_B_A11
M_B_DQ6 DDR1_DQ[5]/DDR0_DQ[13]DDR0_DQ[21]DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] M_A_A11 M_B_DQ39 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] M_B_A15
AK67 BA54 AR37 AN53
M_B_DQ7 DDR1_DQ[6]/DDR0_DQ[14]DDR0_DQ[22]DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] M_A_A15 M_B_DQ40 DDR1_DQ[39]/DDR1_DQ[23] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# M_B_A14
AK66 BA55 AT33 AN52
M_B_DQ8 DDR1_DQ[7]/DDR0_DQ[15]DDR0_DQ[23] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# M_A_A14 M_B_DQ41 DDR1_DQ[40]/DDR1_DQ[24] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
AF70 AY54 AU33
M_B_DQ9 DDR1_DQ[8]/DDR0_DQ[24] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] M_B_DQ42 DDR1_DQ[41]/DDR1_DQ[25] M_B_A13
AF68 AU30 BA43
M_B_DQ10 DDR1_DQ[9]/DDR0_DQ[25] M_A_A13 M_B_DQ43 DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
AH71 AU46 AT30 AY43 M_B_CAS# [13]
M_B_DQ11 DDR1_DQ[10]/DDR0_DQ[26] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] M_B_DQ44 DDR1_DQ[43]/DDR1_DQ[27] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
AH68
DDR1_DQ[11]/DDR0_DQ[27] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
AU48 M_A_CAS# [12] M_B_DQ[40:47] AR33
DDR1_DQ[44]/DDR1_DQ[28] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
AY44 M_B_WE# [13]
M_B_DQ[8:15] M_B_DQ12 AF71 AT46 M_B_DQ45 AP33 AW44
DDR1_DQ[12]/DDR0_DQ[28] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] M_A_WE# [12] DDR1_DQ[45]/DDR1_DQ[29] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] M_B_RAS# [13]
M_B_DQ13 AF69 AU50 M_A_RAS# [12] M_B_DQ46 AR30 BB44 M_B_BS0 [13]
M_B_DQ14 DDR1_DQ[13]/DDR0_DQ[29] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] M_B_DQ47 DDR1_DQ[46]/DDR1_DQ[30] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] M_B_A2
AH70 AU52 M_A_BS0 [12] AP30 AY47
M_B_DQ15 DDR1_DQ[14]/DDR0_DQ[30] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] M_A_A2 M_A_DQ48 DDR1_DQ[47]/DDR1_DQ[31] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
AH69 AY51 AY31 BA44 M_B_BS1 [13]
M_A_DQ16 DDR1_DQ[15]/DDR0_DQ[31] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] M_A_DQ49 DDR0_DQ[48]/DDR1_DQ[32] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] M_B_A10
BB65 AT48 M_A_BS1 [12] AW31 AW46
M_A_DQ17 DDR0_DQ[16]/DDR0_DQ[32] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] M_A_A10 M_A_DQ50 DDR0_DQ[49]/DDR1_DQ[33] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] M_B_A1
AW65 AT50 AY29 AY46
M_A_DQ18 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] M_A_A1 M_A_DQ51 DDR0_DQ[50]/DDR1_DQ[34] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] M_B_A0
C AW63
DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
BB50 M_A_DQ[48:55] AW29
DDR0_DQ[51]/DDR1_DQ[35] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
BA46 C
M_A_DQ[16:23] M_A_DQ19 AY63 AY50 M_A_A0 M_A_DQ52 BB31 BB46 M_B_A3
M_A_DQ20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] M_A_A3 M_A_DQ53 DDR0_DQ[52]/DDR1_DQ[36] DDR1_MA[3] M_B_A4
BA65 BA50 BA31 BA47
M_A_DQ21 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[3] M_A_A4 M_A_DQ54 DDR0_DQ[53]/DDR1_DQ[37] DDR1_MA[4]
AY65 BB52 BA29
M_A_DQ22 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[4] M_A_DQ55 DDR0_DQ[54]/DDR1_DQ[38] M_A_DQS_DN4
BA63 BB29 BA38
M_A_DQ23 DDR0_DQ[22]/DDR0_DQ[38] M_A_DQS_DN0 M_A_DQ56 DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQSN[4]/DDR1_DQSN[0] M_A_DQS_DP4 M_A_DQS4
BB63 AM70 AY27 AY38
M_A_DQ24 DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQSN[0] M_A_DQS_DP0 M_A_DQS0 M_A_DQ57 DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQSP[4]/DDR1_DQSP[0] M_A_DQS_DN5
BA61 AM69 AW27 AY34
M_A_DQ25 DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQSP[0] M_A_DQS_DN1 M_A_DQ58 DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSN[5]/DDR1_DQSN[1] M_A_DQS_DP5 M_A_DQS5
AW61 AT69 AY25 BA34
M_A_DQ26 DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQSN[1] M_A_DQS_DP1 M_A_DQS1 M_A_DQ59 DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSP[5]/DDR1_DQSP[1] M_B_DQS_DN4
BB59
DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQSP[1]
AT70 M_A_DQ[56:63] AW25
DDR0_DQ[59]/DDR1_DQ[43] DDR1_DQSN[4]/DDR1_DQSN[2]
AT38
M_A_DQ[24:31] M_A_DQ27 AW59 AH66 M_B_DQS_DN0 M_A_DQ60 BB27 AR38 M_B_DQS_DP4 M_B_DQS4
M_A_DQ28 DDR0_DQ[27]/DDR0_DQ[43] DDR1_DQSN[0]/DDR0_DQ[2] M_B_DQS_DP0 M_A_DQ61 DDR0_DQ[60]/DDR1_DQ[44] DDR1_DQSP[4]/DDR1_DQSP[2] M_B_DQS_DN5
BB61
DDR0_DQ[28]/DDR0_DQ[44] DDR1_DQSP[0]/DDR0_DQ[2]
AH65 M_B_DQS0 BA27
DDR0_DQ[61]/DDR1_DQ[45] DDR1_DQSN[5]/DDR1_DQSN[3]
AT32
M_A_DQ29 AY61 AG69 M_B_DQS_DN1 M_A_DQ62 BA25 AR32 M_B_DQS_DP5 M_B_DQS5
M_A_DQ30 DDR0_DQ[29]/DDR0_DQ[45] DDR1_DQSN[1]/DDR0_DQ[3] M_B_DQS_DP1 M_A_DQ63 DDR0_DQ[62]/DDR1_DQ[46] DDR1_DQSP[5]/DDR1_DQSP[3] M_A_DQS_DN6
BA59
DDR0_DQ[30]/DDR0_DQ[46] DDR1_DQSP[1]/DDR0_DQ[3]
AG70 M_B_DQS1 BB25
DDR0_DQ[63]/DDR1_DQ[47] DDR0_DQSN[6]/DDR1_DQSN[4]
BA30
M_A_DQ31 AY59 BA64 M_A_DQS_DN2 M_B_DQ48 AU27 AY30 M_A_DQS_DP6 M_A_DQS6
M_B_DQ16 DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQSN[2]/DDR0_DQSN[4] M_A_DQS_DP2 M_A_DQS2 M_B_DQ49 DDR1_DQ[48] DDR0_DQSP[6]/DDR1_DQSP[4] M_A_DQS_DN7 1D35V_S3
AT66 AY64 AT27 AY26
M_B_DQ17 DDR1_DQ[16]/DDR0_DQ[48] DDR0_DQSP[2]/DDR0_DQSP[4] M_A_DQS_DN3 M_B_DQ50 DDR1_DQ[49] DDR0_DQSN[7]/DDR1_DQSN[5] M_A_DQS_DP7 M_A_DQS7
AU66 AY60 AT25 BA26
M_B_DQ18 DDR1_DQ[17]/DDR0_DQ[49] DDR0_DQSN[3]/DDR0_DQSN[5] M_A_DQS_DP3 M_A_DQS3 M_B_DQ51 DDR1_DQ[50] DDR0_DQSP[7]/DDR1_DQSP[5] M_B_DQS_DN6
AP65 BA60 M_B_DQ[48:55] AU25 AR25

1
M_B_DQ19 DDR1_DQ[18]/DDR0_DQ[50] DDR0_DQSP[3]/DDR0_DQSP[5] M_B_DQS_DN2 M_B_DQ52 DDR1_DQ[51] DDR1_DQSN[6] M_B_DQS_DP6 M_B_DQS6
M_B_DQ[16:23] AN65
DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQSN[2]/DDR0_DQSN[6]
AR66 AP27
DDR1_DQ[52] DDR1_DQSP[6]
AR27
M_B_DQ20 AN66
DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQSP[2]/DDR0_DQSP[6]
AR65 M_B_DQS_DP2 M_B_DQS2 M_B_DQ53 AN27
DDR1_DQ[53] DDR1_DQSN[7]
AR22 M_B_DQS_DN7 R505
M_B_DQ21 AP66 AR61 M_B_DQS_DN3 M_B_DQ54 AN25 AR21 M_B_DQS_DP7 M_B_DQS7 470R2F-GP
DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQ[54] DDR1_DQSP[7]
M_B_DQ22 AT65
DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQSP[3]/DDR0_DQSP[7]
AR60 M_B_DQS_DP3 M_B_DQS3 M_B_DQ55 AP25
DDR1_DQ[55]
M_B_DQ23 AU65 M_B_DQ56 AT22 AN43

2
M_B_DQ24 DDR1_DQ[23]/DDR0_DQ[55] M_B_DQ57 DDR1_DQ[56] DDR1_ALERT# DDR1_PAR TP502 Do Not Stuff
AT61 AW50 AU22 AP43 1
M_B_DQ25 DDR1_DQ[24]/DDR0_DQ[56] DDR0_ALERT# DDR0_PAR TP501 Do Not Stuff M_B_DQ58 DDR1_DQ[57] DDR1_PAR SM_DRAMRST# Do Not Stuff
AU61 AT52 1 AU21 AT13 1 2 R504 DDR3_DRAMRST# [12,13]
M_B_DQ26 DDR1_DQ[25]/DDR0_DQ[57] DDR0_PAR M_B_DQ59 DDR1_DQ[58] DRAM_RESET# SM_RCOMP_0
AP60 M_B_DQ[56:63] AT21 AR18 1 R501 2 121R2F-GP
M_B_DQ27 DDR1_DQ[26]/DDR0_DQ[58] M_B_DQ60 DDR1_DQ[59] DDR_RCOMP[0] SM_RCOMP_1
M_B_DQ[24:31] AN60 AY67 V_SM_VREF_CNT [42] AN22 AT18 1 R502 2 80D6R2F-L-GP
M_B_DQ28 DDR1_DQ[27]/DDR0_DQ[59] DDR_VREF_CA M_B_DQ61 DDR1_DQ[60] DDR_RCOMP[1] SM_RCOMP_2
AN61 AY68 M_VREF_DQ_DIM0 [42] AP22 AU18 1 R503 2 100R2F-L1-GP-U
M_B_DQ29 DDR1_DQ[28]/DDR0_DQ[60] DDR0_VREF_DQ M_B_DQ62 DDR1_DQ[61] DDR_RCOMP[2]
AP61 BA67 M_VREF_DQ_DIM1 [42] AP21
M_B_DQ30 DDR1_DQ[29]/DDR0_DQ[61] DDR1_VREF_DQ M_B_DQ63 DDR1_DQ[62] DDR CH - B
AT60 AN21

2
M_B_DQ31 DDR1_DQ[30]/DDR0_DQ[62] DDR1_DQ[63]
AU60
DDR1_DQ[31]/DDR0_DQ[63] DDR_VTT_CNTL
AW67 #543016
DDR CH - A SM_PGCNTL [51]
SKYLAKE-GP-U
SKYLAKE-GP-U DYD502
Do Not Stuff
071.SKYLA.000U Do Not Stuff
071.SKYLA.000U

1
Layout Note:
Design Guideline:
SM_RCOMP keep routing length less than 500 mils.
DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel.
B
Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential close to CPU B
clock pair to clock pair swapping within a channel is not allowed.

M_B_A0 M_B_A[15:0] [13]

M_A_A0 M_A_A[15:0] [12] M_B_A1
PDG: DDR/ODT M_A_A1
M_A_A2
M_B_A2
M_B_A3
M_A_A3 M_B_A4
M_A_A4 M_B_A5
M_A_A5 M_B_A6
M_A_A6 M_B_A7
M_A_A7 M_B_A8
M_A_A8 M_B_A9
M_A_A9 M_B_A10
M_A_A10 M_B_A11
M_A_A11 M_B_A12
M_A_A12 M_B_A13
M_A_A13 M_B_A14
M_A_A14 M_B_A15
M_A_A15

M_A_DQS_DN[7:0] [12] M_B_DQS_DN[7:0] [13]

M_B_DQS_DN0
M_A_DQS_DN0 M_B_DQS_DN1
M_A_DQS_DN1 M_B_DQS_DN2
M_A_DQS_DN2 M_B_DQS_DN3
M_A_DQS_DN3 M_B_DQS_DN4
M_A_DQS_DN4 M_B_DQS_DN5
M_A_DQS_DN5 M_B_DQS_DN6
M_A_DQS_DN6 M_B_DQS_DN7
M_A_DQS_DN7
M_B_DQS_DP[7:0] [13]
M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_A_DQS_DP[7:0] [12]
M_A_DQS_DP0 M_B_DQS_DP3
M_A_DQS_DP1 M_B_DQS_DP4
M_A_DQS_DP2 M_B_DQS_DP5
M_A_DQS_DP3 M_B_DQS_DP6
A M_A_DQS_DP4 M_B_DQS_DP7 A
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(DDR)
Size Document Number Rev
A2 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 5 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

CPU1S 19 OF 20

RESERVED SIGNALS-1
[99] CFG[19:0] SKYLAKE_ULT
CFG0 E68 BB68 RSVD_TP_BB68 1
CFG1
CFG2
B67
D65
Vinafix.com
CFG[0]
CFG[1]
CFG[2]
RSVD_TP_BB68
RSVD_TP_BB69 BB69 RSVD_TP_BB69 1 TP603 Do Not Stuff
TP604 Do Not Stuff
CFG3 D67 AK13 RSVD_TP_AK13 1
CFG4 CFG[3] RSVD_TP_AK13 RSVD_TP_AK12 TP605 Do Not Stuff
D E70 CFG[4] RSVD_TP_AK12 AK12 1 D
CFG5 C68 TP606 Do Not Stuff
CFG6 CFG[5]
D68 CFG[6] RSVD_BB2 BB2
CFG7 C67 BA3
CFG8 CFG[7] RSVD_BA3
F71 CFG[8]
CFG9 G69
CFG10 CFG[9] TP5_AU5
F70 CFG[10] TP5 AU5 1
CFG11 G68 AT5 TP6_AT5 1 TP607 Do Not Stuff
CFG12 CFG[11] TP6 TP608 Do Not Stuff
H70 CFG[12]
CFG13 G71
CFG14 CFG[13]
H69 CFG[14] RSVD_D5 D5
CFG15 G70 D4
CFG[15] RSVD_D4
RSVD_B2 B2
CFG16 E63 C2
CFG17 CFG[16] RSVD_C2
F63 CFG[17]
RSVD_B3 B3
CFG18 E66 A3
CFG19 CFG[18] RSVD_A3
F66 CFG[19]
RSVD_AW1 AW1
49D9R2F-GP 2 1 R601 CFG_RCOMP E60 CFG_RCOMP
RSVD_E1 E1
[99] ITP_PMODE E8 ITP_PMODE RSVD_E2 E2

AY2 RSVD_AY2 RSVD_BA4 BA4

AY1 RSVD_AY1 RSVD_BB4 BB4

D1 RSVD_D1 RSVD_A4 A4
D3 RSVD_D3 RSVD_C4 C4
C K46 BB5 TP4_BB5 1 C
RSVD_K46 TP4 TP609 Do Not Stuff
K45 RSVD_K45
RSVD_A69 A69
AL25 RSVD_AL25 RSVD_B69 B69
AL27 RSVD_AL27
RSVD_AY3 AY3
C71 RSVD_C71
B70 RSVD_B70 RSVD_D71 D71
RSVD_C70 C70
F60 RSVD_F60
RSVD_C54 C54
A52 RSVD_A52 RSVD_D54 D54

1 RSVD_TP_BA70 BA70 AY4 TP1_AY4 1

Do Not Stuff TP601 RSVD_TP_BA68 RSVD_TP_BA70 TP1 TP2_BB3 TP610 Do Not Stuff
1 BA68 RSVD_TP_BA68 TP2 BB3 1
Do Not Stuff TP602 R602 TP611 Do Not Stuff
J71 RSVD_J71 VSS_AY71 AY71 VSS_AY71 1 2 #54469 CRB.
J68 AR56 ZVM# Do Not Stuff 1
RSVD_J68 ZVM# TP616 Do Not Stuff
1 RSVD_F65 F65 AW71 RSVD_TP_AW 71 1
Do Not Stuff TP612 RSVD_G65 VSS_F65 RSVD_TP_AW71 RSVD_AW71 RSVD_TP_AW 70 TP614 Do Not Stuff +VCCST_CPU
1 G65 VSS_G65 RSVD_TP_AW70 RSVD_AW70 AW70 1
Do Not Stuff TP613 TP615 Do Not Stuff
F61 AP56 MSM# 1
RSVD_F61 MSM# PROC_SELECT# 1 TP617 Do Not Stuff
E61 RSVD_E61 PROC_SELECT# C64 2
R603
100KR2J-1-GP

SKYLAKE-GP-U
B B
071.SKYLA.000U
PCH strap pin:
CFG3

CFG TERMINATIONS
1

[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

R604
Do Not Stuff 0 : ENABLED
DY 20140807 david
CFG[3] SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
#544669 Rev0.52 (CRB)
2

1 : DISABLED

(#543016)
CFG4
1

DISPLAY PORT PRESENCE STRAP

R605
1KR2J-1-GP
0 : ENABLED
CFG[4] An external Display Port device is connected to the Embedded Display Port.
2

1 : DISABLED (Default)
No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.

A
SKL(#543016): <Core Design> A

Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(RESERVED)
Size Document Number Rev
A3 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 6 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

CPU1M 13 OF 20
+VCCGT
+VCCGT CPU POWER 2 OF 4
N70 +VDDQ_CPU_CLK 1D35V_S3
VCCGT
A48 N71
VCCGT SKYLAKE_ULT VCCGT
A53 R63
VCCGT VCCGT
A58 R64

1
CPU1L 12 OF 20 VCCGT VCCGT
A62 R65
VCC_CORE VCC_CORE VCCGT VCCGT

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CPU POWER 1 OF 4 A66 R66 DY C722
VCCGT VCCGT Do Not Stuff
AA63 R67

1
VCCGT VCCGT
A30 G32 AA64 R68
VCC_A30 VCC_G32 VCCGT VCCGT C719 +VCCIO
A34 G33 AA66 R69
VCC_A34 SKYLAKE_ULT VCC_G33 VCCGT VCCGT CPU1N 14 OF 20
A39 G35 AA67 R70 SC1U10V2KX-1GP

2
VCC_A39 VCC_G35 VCCGT VCCGT +VCCIO(ICCMAX.=2.73A)
D A44 G37 AA69 R71 CPU POWER 3 OF 4 D
VCC_A44 VCC_G37 VCCGT VCCGT
AK33 G38 AA70 T62
VCC_AK33 VCC_G38 VCCGT VCCGT
AK35 G40 AA71 U65 AU23 AK28
VCC_AK35 VCC_G40 VCCGT VCCGT VDDQ_AU23 VCCIO
AK37 G42 AC64 U68 AU28 AK30
VCC_AK37 VCC_G42 VCCGT VCCGT VDDQ_AU28 SKYLAKE_ULT VCCIO
AK38 J30 AC65 U71 AU35 AL30
VCC_AK38 VCC_J30 VCCGT VCCGT VDDQ_AU35 VCCIO
AK40 J33 AC66 W63 AU42 AL42
VCC_AK40 VCC_J33 VCCGT VCCGT VDDQ_AU42 VCCIO
AL33 J37 AC67 W64 BB23 AM28
VCC_AL33 VCC_J37 VCCGT VCCGT VDDQ_BB23 VCCIO
AL37 J40 AC68 W65 BB32 AM30
VCC_AL37 VCC_J40 VCCGT VCCGT VDDQ_BB32 VCCIO +VCCSA
AL40 K33 AC69 W66 BB41 AM42
VCC_AL40 VCC_K33 VCCGT VCCGT VDDQ_BB41 VCCIO
AM32 K35 AC70 W67 BB47
VCC_AM32 VCC_K35 VCCGT VCCGT +VDDQ_CPU_CLK VDDQ_BB47
AM33 K37 AC71 W68 BB51 AK23
VCC_AM33 VCC_K37 VCCGT VCCGT VDDQ_BB51 VCCSA
AM35 K38 J43 W69 AK25
VCC_AM35 VCC_K38 VCCGT VCCGT SC10U6D3V3MX-GP VCCSA
AM37 K40 J45 W70 2 1 C715 G23
VCC_AM37 VCC_K40 VCCGT VCCGT +VCCST_CPU VCCSA
AM38 K42 J46 W71 AM40 G25
VCC_AM38 VCC_K42 VCCGT VCCGT VDDQC VCCSA
G30 K43 J48 Y62 G27
VCC_G30 VCC_K43 VCCGT VCCGT SC1U10V2KX-1GP 2 VCCSA
J50 1 C716 0.04 A A18 G28
VCCGT +VCCSTG VCCST VCCSA
K32 E32 J52 J22
VCCG0 RSVD_K32 VCC_SENSE VCC_SENSE [46] VCCGT VCCSA
E33 J53 AK42 A22 J23
VSS_SENSE VSS_SENSE [46] VCCGT VCCGTX_AK42 Do Not Stuff VCCSTG_A22 VCCSA
AK32 J55 AK43 2 1 C717 J27
VCCG1 RSVD_AK32 H_CPU_SVIDALRT# VCCGT VCCGTX_AK43 VCCSA
VIDALERT#
B63
H_CPU_SVIDCLK
J56
VCCGT VCCGTX_AK45
AK45 DY 1D35V_S3
AL23
VCCPLL_OC VCCSA
K23
AB62 A63 J58 AK46 K25
VCCOPC_AB62 VIDSCK H_CPU_SVIDDAT +VCCSTG VCCGT VCCGTX_AK46 VCCSA
P62 D64 J60 AK48 K20 K27
VCCOPC_P62 VIDSOUT VCCGT VCCGTX_AK48 SCD1U16V2KX-3GP2 VCCPLL_K20 VCCSA
V62 K48 AK50 1 C718 K21 K28
VCCOPC_V62 VCCGT VCCGTX_AK50 VCCPLL_K21 VCCSA
G20 K50 AK52 K30
Do Not Stuff TP704 VCC_OPC_1P8_H63 VCCSTG_G20 VCCGT VCCGTX_AK52 VCCSA
1 H63 K52 AK53
VCC_OPC_1P8_H63 VCCGT VCCGTX_AK53 +V1.00U_CPU VCCIO_VR_FB
K53 AK55 AM23
Do Not Stuff TP708 VCC_OPC_1P8_H63 VCCGT VCCGTX_AK55 VCCIO_SENSE VSSIO_VR_FB
1 G61 K55 AK56 AM22
VCC_OPC_1P8_G61 VCCGT VCCGTX_AK56 VSSIO_SENSE
K56 AK58
VCCGT VCCGTX_AK58

C720

C721
AC63 K58 AK60 0.12 A H21 VSSSA_SENSE [46]

1
VCCOPC_SENSE VCCGT VCCGTX_AK60 VSSSA_SENSE
AE63 K60 AK70 H20 VCCSA_SENSE [46]
VSSOPC_SENSE VCCGT VCCGTX_AK70 VCCSA_SENSE
L62 AL43
VCCGT VCCGTX_AL43
AE62 L63 AL46

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
2

2
VCCEOPIO VCCGT VCCGTX_AL46 SKYLAKE-GP-U
AG62 L64 AL50
VCCEOPIO VCCGT VCCGTX_AL50 +VCCIO
L65 AL53
VCCGT VCCGTX_AL53
AL63 L66 AL56
AJ62
VCCEOPIO_SENSE
L67
VCCGT VCCGTX_AL56
AL60
071.SKYLA.000U
VSSEOPIO_SENSE VCCGT VCCGTX_AL60
L68 AM48
VCCGT VCCGTX_AM48
L69 AM50
SKYLAKE-GP-U VCCGT VCCGTX_AM50
L70 AM52

1
VCCGT VCCGTX_AM52
L71 AM53
VCCGT VCCGTX_AM53 R733
M62 AM56
C
071.SKYLA.000U N63
VCCGT VCCGTX_AM56
AM58 100R2F-L1-GP-U C
VCCGT VCCGTX_AM58 VCC_CORE
N64 AU58
VCCGT VCCGTX_AU58
N66 AU63 #544669 CRB.

2
VCCGT VCCGTX_AU63
Layout Note: N67
VCCGT VCCGTX_BB57
BB57
N69 BB66 1D35V_S3 +VDDQ_CPU_CLK VCCIO_VR_FB
The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch).

1
VCCGT VCCGTX_BB66
Route the Alert signal between the Clock and the Data signals. R705
R719 VSSIO_VR_FB
[46] VCCGT_SENSE J70 AK62
VCCGT_SENSE VCCGTX_SENSE 100R2F-L1-GP-U
[46] VSSGT_SENSE J69 AL61 1 2

1
VSSGT_SENSE VSSGTX_SENSE
Do Not Stuff R730

2
SKYLAKE-GP-U 100R2F-L1-GP-U

SVID DATA 071.SKYLA.000U

VCC_SENSE [46]
VSS_SENSE [46]

2
1
+VCCST_CPU
SVID_543016: R720 Layout Note:
100R2F-L1-GP-U 1. Place close to CPU
2. VCC_SENSE/ VSS_SENSE

2
impedance=50 ohm
1

CLOSE TO CPU 3. Length match<25mil +VCCSA

R726
100R2F-L1-GP-U #543016
+VCCGT

1
2

R735
H_CPU_SVIDDAT R709 1 2 Do Not Stuff 100R2F-L1-GP-U
VR_SVID_DATA [46]

1
R721

2
100R2F-L1-GP-U
VCCSA_SENSE
VSSSA_SENSE

2
+VCCST_CPU

SVID CLOCK

1
VCCGT_SENSE [46]
VSSGT_SENSE [46] R734
#543016 100R2F-L1-GP-U
1

CLOSE TO VR

1
DY R723

2
Do Not Stuff R722
100R2F-L1-GP-U
B B
2

2
H_CPU_SVIDCLK R732 1 2 Do Not Stuff VR_SVID_CLK [46]

+VCCST_CPU

#543016
1

CLOSE TO CPU
R727
56R2J-4-GP
2

R728
H_CPU_SVIDALRT# 2 1 VR_SVID_ALERT# [46]
220R2J-L2-GP

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(VCC_CORE)
Size Document Number Rev
A2 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 7 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

Vinafix.com
D D

CPU1A 1 OF 20

E55 SKYLAKE_ULT C47

[57] HDMI_DATA2# DDI1_TXN[0] EDP_TXN[0] eDP_TX_CPU_N0 [55]
[57] HDMI_DATA2 F55 DDI1_TXP[0] EDP_TXP[0] C46 eDP_TX_CPU_P0 [55]
[57] HDMI_DATA1# E58 D46
HDMI [57] HDMI_DATA1 F58
DDI1_TXN[1]
DDI1_TXP[1]
EDP_TXN[1]
EDP_TXP[1] C45
eDP_TX_CPU_N1
eDP_TX_CPU_P1
[55]
[55]
[57] HDMI_DATA0# F53 DDI1_TXN[2] EDP_TXN[2] A45
[57] HDMI_DATA0 G53 DDI1_TXP[2] EDP_TXP[2] B45
[57] HDMI_CLK# F56 DDI1_TXN[3] EDP_TXN[3] A47
[57] HDMI_CLK G56 DDI1_TXP[3] EDP_TXP[3] B47

[66] PCH_DPC_N0 C50 DDI2_TXN[0] DDI EDP_AUXN E45 eDP_AUX_CPU_N [55]

3D3V_S0 D50 EDP F45
[66] PCH_DPC_P0
DP to VGA [66] PCH_DPC_N1 C52
DDI2_TXP[0]
DDI2_TXN[1]
EDP_AUXP eDP_AUX_CPU_P [55]

[66] PCH_DPC_P1 D52 B52 EDP_DISP_UTIL 1

RN801 DDI2_TXP[1] EDP_DISP_UTIL
A50 TP801 Do Not Stuff
CPU_DP1_CTRL_DATA DDI2_TXN[2]
2 3 B50 DDI2_TXP[2] DDI1_AUXN G50
1 4 CPU_DP1_CTRL_CLK D51 F50
DDI2_TXN[3] DDI1_AUXP
C51 DDI2_TXP[3] DDI2_AUXN E48 PCH_DPC_AUXN [66]
SRN2K2J-1-GP DDI2_AUXP F48 PCH_DPC_AUXP [66]
DDI3_AUXN G46
DISPLAY SIDEBANDS
DDI3_AUXP F46
C 3D3V_S0 L13 C
HDMI [57] CPU_DP1_CTRL_CLK
[57] CPU_DP1_CTRL_DATA L12
GPP_E18/DDPB_CTRLCLK
GPP_E19/DDPB_CTRLDATA
Strap
GPP_E13/DDPB_HPD0 L9 CPU_DP1_HPD [57]
L7 CPU_DP2_HPD1 1 R805 2
R804 1 CPU_DP2_CTRL_DATA CPU_DP2_CTRL_CLK GPP_E14/DDPC_HPD1 Do Not Stuff CPU_DP2_HPD [66]
2 N7 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 L6 SIO_EXT_SMI#_R [24]
2K2R2J-2-GP CPU_DP2_CTRL_DATA N8 Strap N9 CPU_DP2_HPD3 1 DY 2
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 R807 Do Not Stuff
GPP_E17/EDP_HPD L10 EDP_HPD [55]
R803 1 DY 2 CPU_DP2_CTRL_CLK Check +VCCIO Do Not Stuff N11 GPP_E22/DDPD_CTRLCLK
Do Not Stuff
R801
TP802 1 DDPD_CTRLDATA N12 GPP_E23/DDPD_CTRLDATA
Strap EDP_BKLTEN R12 L_BKLT_EN [24]
EDP_BKLTCTL R11 L_BKLT_CTRL [55]
1 2 EDP_COMP E52 U13 EDP_VDD_EN [55]
EDP_RCOMP EDP_VDDEN
24D9R2F-L-GP SKYLAKE-GP-U

(#543016) eDP_RCOMP Guideline 071.SKYLA.000U

(#543016) The Skylake U/Y processor supports only two DDI ports - Port 1 and Port 2.
Signal Trace Isolation Resistor Length
Width Spacing Value
eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1% Max = 100 mils

3D3V_S0

(#543016) DDI Disabling and Termination Guidelines

Port Strap Enable Port Disable Port SIO_EXT_SMI#_R 1 R802 2 10KR2J-3-GP
B B
PU to 3.3 V with 2.2-k
Port 1 DDPB_CTRLDATA ±5% resistor NC
PU to 3.3 V with 2.2-k
Port 2 DDPC_CTRLDATA ±5% resistor NC CPU_DP2_HPD

1
R806
Strap pin: 100KR2J-1-GP
Port B /
Sampled at rising edge of PCH_PWROK
Port C Detected

2
0 = Port B is not detected.
DDPB_CTRLDATA * 1 = Port B is detected.

0 = Port C is not detected.

DDPC_CTRLDATA * 1 = Port C is detected.

These two signals have weak internal pull-down.

Design Guideline:
Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor.
A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(DISPLAY)
Size Document Number Rev
A3 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 8 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

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D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)
Size Document Number Rev
A4 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 9 of 105
5 4 3 2 1
 D

A00
Wistron Corporation

Rev

105
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

of
CPU_(Power CAP1)

10
Loveland SKL-U
Sheet
Vinafix.com

Tuesday, September 15, 2015

1

1
Document Number
<Core Design>

A2

Date:
Size
Title
2

2
(#543016 PDG)
3

3
PC1098

Do Not Stuff
DY
PC1053

Do Not Stuff 1 2
DY

1 2
PC1097

Do Not Stuff
10U 0603 x 4

DY
PC1052

PC1079

SC22U6D3V3MX-1-GP 1 2 SC22U6D3V3MX-1-GP

1 2 1 2
PC1068

1 2 Do Not Stuff
PC1077 PC1078

SC22U6D3V3MX-1-GP
DY

DY
PC1051

SC22U6D3V3MX-1-GP
EC1005 SCD1U25V2KX-GP
1 2 1 2
22U 0603 x 9

PC1061 Do Not Stuff 1 2

1 2 1 2
PC1067

Do Not Stuff SC22U6D3V3MX-1-GP

DY

EC1002 SCD1U25V2KX-GP
DY

1 2
PC1050

1 2 SC22U6D3V3MX-1-GP 1 2 1 2
PC1096

PC1060 Do Not Stuff Do Not Stuff

PC1075 PC1076

SC22U6D3V3MX-1-GP
EC1004 SC1U10V2KX-1GP
DY

DY

1 2
PC1066

1 2 1 2 Do Not Stuff 1 2
DY

1 2
PC1049

PC1095

PC1059 Do Not Stuff EC1003 SC1U10V2KX-1GP SC22U6D3V3MX-1-GP 1 2 Do Not Stuff

SC22U6D3V3MX-1-GP
DY
1D35V_S3

1 1 2 2 1 2 1 2
PC1065

SC22U6D3V3MX-1-GP
VCCSA

1 2
PC1093 PC1094

Do Not Stuff
PC1058 EC1001 SC10U6D3V3MX-GP SC1U10V2KX-1GP
PC1048

PC1074

SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
DY

DY

1 2
1 2 1 2 1 2
1 2 1 2
PC1057 SC10U6D3V3MX-GP Do Not Stuff Do Not Stuff
PC1047

PC1072 PC1073

SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
PC1064
DY
PC1046

SC22U6D3V3MX-1-GP
DY

1 1 2 2 1 2
1 2 1 2
PC1091 PC1092

Do Not Stuff
PC1056 PC1063 SC10U6D3V3MX-GP Do Not Stuff
1D35V_S3

1 2
SC22U6D3V3MX-1-GP
4

4
DY
PC1054

SC22U6D3V3MX-1-GP
DY

1 1 2 2 1 2
+VCCSA

1 2
PC1055 PC1062 SC10U6D3V3MX-GP Do Not Stuff Do Not Stuff
1 2
PC1070 PC1071

SC22U6D3V3MX-1-GP
DY

1 2
1 2
PC1090

Do Not Stuff
SC22U6D3V3MX-1-GP
DY

1 2
1 2
PC1088 PC1089

Do Not Stuff
PC1069

SC22U6D3V3MX-1-GP
DY

1 2
PC1019 PC1020

SC22U6D3V3MX-1-GP 1 2
SC22U6D3V3MX-1-GP
PC1044

1 2 SC22U6D3V3MX-1-GP
1 2
PC1030

SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
1 2
PC1086 PC1087

SC22U6D3V3MX-1-GP
1 2 1 2
PC1042 PC1043

SC22U6D3V3MX-1-GP 1 2
PC1009

PC1018

PC1029

SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

1 2 SC22U6D3V3MX-1-GP
1 2 1 2 1 2
SC22U6D3V3MX-1-GP 1 2
PC1007 PC1008

PC1016 PC1017

PC1027 PC1028

SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

+VCCPRIM_CORE

PC1085

SC22U6D3V3MX-1-GP
22U 0603 x28

1 2
1 2 1 2 1 2
PC1034 PC1041

1 2 SC22U6D3V3MX-1-GP 1 2
PC1039

SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

PC1083 PC1084

SC22U6D3V5MX-2GP
1 2 SC22U6D3V3MX-1-GP
1 2 1 2 1 2 1 2
SC22U6D3V3MX-1-GP 1 2
PC1005 PC1006

PC1014 PC1015

PC1025 PC1026

PC1038

SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V5MX-2GP

SC22U6D3V3MX-1-GP
22U 0603 x 30

1 2
1 2 1 2 1 2
PC1033

SC22U6D3V3MX-1-GP 1 2
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
PC1081 PC1082

1 2 SC22U6D3V3MX-1-GP
VCCGT

1 2 1 2 1 2
PC1031 PC1032

SC22U6D3V3MX-1-GP
+VCCIO(ICCMAX.=2.73A)

1 2
PC1004

PC1013

PC1024

SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP
1 2
1 2 1 2 1 2
SC22U6D3V3MX-1-GP
Main Func = CPU

1 2
PC1002 PC1003

PC1011 PC1012

PC1022 PC1023

SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

DY
5

5
PC1080

1 2 SC22U6D3V3MX-1-GP
1 2 1 2 1 2 1 2
CORE

1 2
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
PC1037 Do Not Stuff
+VCCGT

1 2 1 2 1 2 1 2
PC1001

PC1010

PC1021

SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP PC1036 SC22U6D3V3MX-1-GP

+VCCIO

1 2 1 2 1 2 1 2
PC1035 SC22U6D3V3MX-1-GP
VCC_CORE

A
 5 4 3 2 1

Main Func = CPU

+VCCGT
VCCIO
+VCCIO

+VCCIO(ICCMAX.=2.73A)

1
C1136 C1138 C1147 C1148 C1149 C1150 1U 0402 x 6

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2

1
SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
C1151 C1152 C1153 C1154

2
SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
D D

PCH DERIVED RAILS

+VCCPGPPA(ICCMAX.=0.05A)
1D0V_S5 +V1.00A_SIP
+V1.8A_SIP +VCCPGPPA
R1117 R1111
1 2
+VCCF24NS_1P0_L
1 DY 2

Do Not Stuff
R1125 1 +V3.3A_SIP Do Not Stuff
2 Do Not Stuff
+VCC24TBT_1P0
R1109
R1122 1 2 Do Not Stuff 1 2
+VCCPRIM_1P0 3D3V_S5_PCH
Do Not Stuff
R1110
R1112 1 2 Do Not Stuff
+VCCF100_1P0_L 1 2 +VCCPRTCPRIM_3P3

R1114 1 2 Do Not Stuff Do Not Stuff 1 R1115 2

+VCCF135_1P0 Do Not Stuff
+VCCPGPPB
R1121 1 2 Do Not Stuff
+VCCFHV 1 R1116 2
Do Not Stuff
R1133 1 2 Do Not Stuff +VCCPGPPC
+VCCMPHYAON_1P0
C 1 R1123 2 C
R1134 1 2 Do Not Stuff Do Not Stuff
+VCCDTS_1P0 +VCCPGPPE

R1130 1 2 Do Not Stuff 1 R1124 2

+VCC19P2_1P0 Do Not Stuff
+VCCPRIM_3P3
R1131 1 2 Do Not Stuff
+VCCF100OC_1P0_L 1 R1127 2
Do Not Stuff
R1132 1 2 Do Not Stuff +VCCPSPI

1 R1126 2
Do Not Stuff

+VCCPGPPG

1 R1128 2
Do Not Stuff

+VCCSA 3 PAD SHARING +VCCPRIM_CORE

+V1.8A_SIP
R1136
R1104
1
DY
2
Do Not Stuff
1 DY 2
+V1.00A_SIP Do Not Stuff
R1105
+VCCMPHYGTAON_1P0(ICCMAX.=3.5A)
1 DY 2
Do Not Stuff

VCCPRIM_CORE

+VCCMPHYGTAON_1P0_LS_SIP +VCCMPHYGTAON_1P0_LS_SIP
1 R1103 2 +VCCAPLLEBB_1P0 +VCCMPHYGTAON_1P0_LS_SIP +VCCSRAM_1P0
R1101 +VCCMPHYGTAON_1P0_LS_SIP +VCCAMPHYPLL_1P0_L
1 2 R1102 1 R1106 2
1

Do Not Stuff C1174 C1182 1 2

1
SC1U10V2KX-1GP

Do Not Stuff

C1180

C1173

C1172
B B
DY

SC1U10V2KX-1GP
0R3J-0-U-GP Do Not Stuff

Do Not Stuff

SC1U10V2KX-1GP
+VCCPRIM_CORE +VCCIO

C1176

C1175
DY 0R3J-0-U-GP

SC1U10V2KX-1GP
2

1
SC22U6D3V3MX-1-GP

SC10U10V5KX-2GP
2

2
C1181
R1107

2
1 DY Do Not
2
Stuff

+V3.3A_SIP +VCCPAZIO

1 R1135 2
Do Not Stuff

+V1.8A_SIP
R1118
1 2
DY
Do Not Stuff

VCC_CORE +VCCAMPHYPLL_1P0_L +VCCAMPHYPLL_1P0 +V1.00A_SIP +VCCAPLL_1P0

R1119 R1120
+V3.3A_SIP +VCCPGPPD_TCH +VCCPGPPD 1 2 1 2
R1108
1 2 0R3J-0-U-GP 0R3J-0-U-GP
R1113
1

1
C1101 C1102 C1103 C1116 C1117 C1184
Do Not Stuff 1 2 SC22U6D3V3MX-1-GP
1U 0402 x 5
2

2
SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

+V1.8A_SIP Do Not Stuff +V1.8A +V1.8A_SIP

A R1129 A

1 DY 2 2 R1139 1
Do Not Stuff
Do Not Stuff

+VCCPGPPD_TCH
<Core Design>
U-line 23e 28W +V1.8A_SIP +VCCPGPPF
IccMax current-10ms max = 34 A
2 R1138 1
Do Not Stuff
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1

Taipei Hsien 221, Taiwan, R.O.C.

C1183
SC10U10V5KX-2GP Title
2

CPU_(Power CAP2)
Size Document Number Rev
A2
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 11 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = DDR SODIMM

DM1

Vinafix.com
[5] M_A_A[15:0]
M_A_A0
M_A_A1
M_A_A2
M_A_A3
98
97
96
95
A0
A1
A2
NP1
NP2
NP1
NP2

110
A3 RAS# M_A_RAS# [5]
D M_A_A4 92 113 D
A4 WE# M_A_WE# [5]
M_A_A5 91 115
A5 CAS# M_A_CAS# [5]
M_A_A6 90
M_A_A7 A6
86 114 M_A_CS#0 [5]
M_A_A8 A7 CS0#
89 121 M_A_CS#1 [5]
M_A_A9 A8 CS1#
85
M_A_A10 A9 SA0_DIMA
107 73 M_A_CKE0 [5]
M_A_A11 A10/AP CKE0 SA1_DIMA
M_A_A12
84
A11 CKE1
74 M_A_CKE1 [5] Note:
83
M_A_A13 A12 SA0 DIM0 = 0, SA1_DIM0 = 0
119 101 M_A_CLK0 [5]

1
M_A_A14 A13 CK0
80 103 M_A_CLK#0 [5] SO-DIMMA SPD Address is 0xA0
M_A_A15 A14 CK0# R1202 R1201
78
A15
SO-DIMMA TS Address is 0x30

Do Not Stuff

Do Not Stuff
79 102 M_A_CLK1 [5]
[5] M_A_BS2 A16/BA2 CK1
104 M_A_CLK#1 [5]
CK1#
109

2
[5] M_A_BS0 BA0
108 11
[5] M_A_BS1 BA1 DM0
Layout Note: [5] M_A_DQ[63:0]
M_A_DQ3 5
DM1
28
46
M_A_DQ1 DQ0 DM2
Place these caps 7
DQ1 DM3
63
M_A_DQ4 15 136
close to VREF_CA M_A_DQ7 DQ2 DM4
M_A_DQ[0:7] 17
DQ3 DM5
153
M_A_DQ2 4 170
M_VREF_CA_DIMMA M_A_DQ6 DQ4 DM6
6 187
M_A_DQ0 DQ5 DM7
16
M_A_DQ5 DQ6
18 200 PCH_SMBDATA [13,18,65,66,67,99]
M_A_DQ9 DQ7 SDA
21 202 PCH_SMBCLK [13,18,65,66,67,99]
M_A_DQ13 DQ8 SCL
23
M_A_DQ14 DQ9 3D3V_S0
33 198
M_A_DQ10 DQ10 EVENT# 1D35V_S3
M_A_DQ[8:15] 35
1

M_A_DQ8 DQ11
22 199
C1201 C1218 C1202 M_A_DQ12 DQ12 VDDSPD
24
M_A_DQ15 DQ13 SA0_DIMA
34 197
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
2

1
M_A_DQ11 DQ14 SA0 SA1_DIMA
36
DQ15 SA1
201 10U 0603 x 3
M_A_DQ20 39 C1203

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
DQ16 1U 0402 x 2

Do Not Stuff
M_A_DQ16

SCD1U16V2KX-3GP

C1207

C1208

C1209
41 77 0.1U 0402 x 5

1
DQ17 NC#1

TC1201
M_A_DQ[16:23] M_A_DQ23 51 122
M_A_DQ19 DQ18 NC#2 1D35V_S3
53 125
M_A_DQ21 40
DQ19 NC#/TEST DY

2
M_A_DQ17 DQ20
42 75
M_A_DQ22 DQ21 VDD1
50 76
M_A_DQ18 DQ22 VDD2
52 81
C
Layout Note: M_A_DQ25 57
DQ23 VDD3
82 C
M_A_DQ28 DQ24 VDD4
Place these caps 59
DQ25 VDD5
87
M_A_DQ[24:31] M_A_DQ26 67 88 ESD A00
close to VREF_DQ M_A_DQ30 DQ26 VDD6
69 93
M_A_DQ24 DQ27 VDD7
56 94
M_VREF_DQ_DIMMA M_A_DQ29 DQ28 VDD8
58 99

SC1U10V2KX-1GP

SC1U10V2KX-1GP
M_A_DQ31 DQ29 VDD9

C1212

C1213
68 100

1
M_A_DQ27 DQ30 VDD10
70 105
M_A_DQ32 DQ31 VDD11
129 106
M_A_DQ33 DQ32 VDD12
131 111

2
M_A_DQ34 DQ33 VDD13
141 112
M_A_DQ35 DQ34 VDD14
M_A_DQ[32:39] 143 117
1

M_A_DQ36 DQ35 VDD15

130 118
M_A_DQ37 DQ36 VDD16
C1205

C1204 DY C1206 132 123

DQ37 VDD17
Do Not Stuff

M_A_DQ38 140 124

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
2

M_A_DQ39 DQ38 VDD18

142
M_A_DQ40 DQ39
147 2
M_A_DQ41 DQ40 VSS
149 3
M_A_DQ46 DQ41 VSS
157 8
M_A_DQ47 DQ42 VSS
M_A_DQ[40:47] 159
DQ43 VSS
9
M_A_DQ44

C1220

C1221

C1222

C1210

C1211
146 13

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
M_A_DQ45 DQ44 VSS
148 14

1
M_A_DQ43 DQ45 VSS
158 19
M_A_DQ42 DQ46 VSS
160 20
M_A_DQ53 DQ47 VSS
163 25

2
M_A_DQ49 DQ48 VSS
Layout Note: M_A_DQ[48:55] M_A_DQ55
165
175
DQ49 VSS
26
31
M_A_DQ54 DQ50 VSS
Place these caps 177
DQ51 VSS
32
M_A_DQ52 164 37
close to VTT1 and M_A_DQ48 DQ52 VSS
166 38
VTT2. M_A_DQ51 DQ53 VSS
174 43
M_A_DQ50 DQ54 VSS
176 44
M_A_DQ61 DQ55 VSS
181 48
M_A_DQ56 183
DQ56 VSS
49
Layout Note:
M_A_DQ62 DQ57 VSS
M_A_DQ[56:63] 191
DQ58 VSS
54 Place these Caps near DIMM1.
M_A_DQ63 193 55
M_A_DQ60 DQ59 VSS
180 60
M_A_DQ57 DQ60 VSS
182 61
M_A_DQ58 DQ61 VSS
192 65
M_A_DQ59 DQ62 VSS
194 66
DQ63 VSS 0D675V_S0
[5] M_A_DQS_DN[7:0] 71
B M_A_DQS_DN0 VSS B
10 72
M_A_DQS_DN1 DQS0# VSS
27 127
M_A_DQS_DN2 DQS1# VSS
45 128
M_A_DQS_DN3 DQS2# VSS
62 133
M_A_DQS_DN4 DQS3# VSS
135 134 1U 0402 x 3

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
M_A_DQS_DN5 DQS4# VSS

C1214

C1215

C1216
152 138

1
M_A_DQS_DN6 DQS5# VSS
169 139
M_A_DQS_DN7 DQS6# VSS
186 144
DQS7# VSS
[5] M_A_DQS_DP[7:0] 145

2
M_A_DQS_DP0 VSS
12 150
M_A_DQS_DP1 DQS0 VSS
29 151
M_A_DQS_DP2 DQS1 VSS
47 155
M_A_DQS_DP3 DQS2 VSS
64 156
M_A_DQS_DP4 DQS3 VSS
137 161
M_A_DQS_DP5 DQS4 VSS
154 162
M_A_DQS_DP6 DQS5 VSS
171 167
M_A_DQS_DP7 DQS6 VSS
188 168
DQS7 VSS
172
M_A_DIMA_ODT0 VSS
116 173
Layout Note: [5] M_A_DIMA_ODT0 M_A_DIMA_ODT1 120
ODT0 VSS
178 Place these Caps near DIMM1.
[5] M_A_DIMA_ODT1 ODT1 VSS
All VREF traces should VSS
179
have width=20mil; M_VREF_CA_DIMMA 126 184
VREF_CA VSS
M_VREF_DQ_DIMMA 1 185
spacing=20 mil VREF_DQ VSS
189
VSS
30 190
[5,13] DDR3_DRAMRST# RESET# VSS
195
VSS
196
VSS
0D675V_S0 203 205
1

C1217 VTT1 VSS

204 206
VTT2 VSS
DY
Do Not Stuff
DYD1217
2

DDR3-204P-252-GP-U
Do Not Stuff
Do Not Stuff
1

62.10017.I31
close to dimm

close to dimm
A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3-SODIMM1
Size Document Number Rev
A2 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 12 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = DDR SODIMM

DM2
[5] M_B_A[15:0]
M_B_A0 98 NP1
M_B_A1 A0 NP1
97 NP2
M_B_A2 A1 NP2 3D3V_S0
96
M_B_A3 A2
95 110 M_B_RAS# [5]
M_B_A4 A3 RAS#
92 113 M_B_WE# [5]
M_B_A5 A4 WE#
91 115 M_B_CAS# [5]

1
M_B_A6 A5 CAS#

Vinafix.com
90
M_B_A7 A6 R1302
86 114 M_B_CS#0 [5]
M_B_A8 A7 CS0# 10KR2J-3-GP
89 121 M_B_CS#1 [5]
M_B_A9 A8 CS1#
85
M_B_A10 A9
107 73 M_B_CKE0 [5]

2
M_B_A11 A10/AP CKE0
D 84 74 M_B_CKE1 [5] D
M_B_A12 A11 CKE1
83
M_B_A13 A12
119 101 M_B_CLK0 [5]
M_B_A14 A13 CK0 SA1_DIMB
80 103 M_B_CLK#0 [5]
M_B_A15 A14 CK0#
78
A15 SA0_DIMB
79 102 M_B_CLK1 [5]
[5] M_B_BS2 A16/BA2 CK1
104 M_B_CLK#1 [5]
CK1#
109

1
[5] M_B_BS0 BA0
108 11
[5] M_B_BS1 BA1 DM0 R1301
[5] M_B_DQ[63:0]
M_B_DQ10 DM1
28
Do Not Stuff
Note:
5 46
M_B_DQ11 DQ0 DM2 SO-DIMMB SPD Address is 0xA4
M_VREF_CA_DIMMB Layout Note: M_B_DQ[8:15] M_B_DQ13
7
15
DQ1 DM3
63
136 SO-DIMMB TS Address is 0x34

2
M_B_DQ15 DQ2 DM4
Place these caps 17
DQ3 DM5
153
M_B_DQ9 4 170
close to VREF_CA M_B_DQ14 DQ4 DM6
6 187
M_B_DQ12 DQ5 DM7
16
M_B_DQ8 DQ6
18 200 PCH_SMBDATA [12,18,65,66,67,99]
M_B_DQ4 DQ7 SDA
21 202 PCH_SMBCLK [12,18,65,66,67,99]
1

M_B_DQ0 DQ8 SCL

23
C1308 C1306 C1309 M_B_DQ2 DQ9 3D3V_S0
33 198
M_B_DQ3 DQ10 EVENT#
M_B_DQ[0:7] 35
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
2

M_B_DQ1 DQ11
22 199
M_B_DQ5 DQ12 VDDSPD
24

1
M_B_DQ6 DQ13 SA0_DIMB
34 197
M_B_DQ7 DQ14 SA0 SA1_DIMB C1311
36 201
DQ15 SA1

SCD1U16V2KX-3GP
M_B_DQ16 39

2
M_B_DQ17 DQ16
41 77
M_B_DQ18 DQ17 NC#1
M_B_DQ[16:23] 51
DQ18 NC#2
122
1D35V_S3
M_B_DQ19 53 125
M_B_DQ20 DQ19 NC#/TEST
40
M_B_DQ21 DQ20 1D35V_S3
42 75
M_B_DQ22 DQ21 VDD1
50 76
M_B_DQ23 DQ22 VDD2
52 81
M_B_DQ31 DQ23 VDD3
57 82
M_B_DQ25 DQ24 VDD4
Layout Note: 59
DQ25 VDD5
87 ESD A00 10U 0603 x 3
M_VREF_DQ_DIMMB M_B_DQ[24:31] M_B_DQ29 67 88

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
DQ26 VDD6 1U 0402 x 2
M_B_DQ27

C1317

C1318

C1323
Place these caps 69 93 0.1U 0402 x 5

1
M_B_DQ24 DQ27 VDD7
close to VREF_DQ 56 94
M_B_DQ28 DQ28 VDD8
58 99
M_B_DQ26 DQ29 VDD9
68 100

2
M_B_DQ30 DQ30 VDD10
C 70 105 C
M_B_DQ33 DQ31 VDD11
129 106
1

M_B_DQ36 DQ32 VDD12

131 111
M_B_DQ34 DQ33 VDD13
C1305

C1302 DY C1310 141 112

DQ34 VDD14
Do Not Stuff

M_B_DQ[32:39] M_B_DQ39 143 117

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
2

M_B_DQ37 DQ35 VDD15

130 118
M_B_DQ32 DQ36 VDD16
132 123
M_B_DQ35 DQ37 VDD17
140 124
M_B_DQ38 DQ38 VDD18
142

SC1U10V2KX-1GP

SC1U10V2KX-1GP
M_B_DQ45 DQ39

C1322

C1321
147 2

1
M_B_DQ41 DQ40 VSS
149 3
M_B_DQ42 DQ41 VSS
157 8
M_B_DQ43 DQ42 VSS
M_B_DQ[40:47] 159 9

2
M_B_DQ40 DQ43 VSS
146 13
M_B_DQ44 DQ44 VSS
148 14
M_B_DQ46 DQ45 VSS
158 19
M_B_DQ47 DQ46 VSS
160 20
M_B_DQ51 DQ47 VSS
163 25
M_B_DQ49 DQ48 VSS
165 26
M_B_DQ55 DQ49 VSS
M_B_DQ[48:55] 175
DQ50 VSS
31
M_B_DQ48 177 32
M_B_DQ52 DQ51 VSS
164 37
M_B_DQ53 DQ52 VSS
166 38
M_B_DQ54 DQ53 VSS

C1315

C1314

C1316

C1312

C1313
174 43

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
M_B_DQ50 DQ54 VSS
176 44

1
M_B_DQ58 DQ55 VSS
181 48
M_B_DQ56 DQ56 VSS
183 49
M_B_DQ60 DQ57 VSS
M_B_DQ[56:63] 191 54

2
M_B_DQ59 DQ58 VSS
193 55
M_B_DQ57 DQ59 VSS
180 60
M_B_DQ61 DQ60 VSS
182 61
M_B_DQ62 DQ61 VSS
192 65
M_B_DQ63 DQ62 VSS
194 66
DQ63 VSS
[5] M_B_DQS_DN[7:0] 71
M_B_DQS_DN1 VSS
10 72
M_B_DQS_DN0 DQS0# VSS
27 127
M_B_DQS_DN2 45
DQS1# VSS
128
Layout Note:
M_B_DQS_DN3 DQS2# VSS
62
DQS3# VSS
133 Place these Caps near DIMM2.
M_B_DQS_DN4 135 134
M_B_DQS_DN5 DQS4# VSS
152 138
M_B_DQS_DN6 DQS5# VSS
169 139
B M_B_DQS_DN7 DQS6# VSS B
186 144
DQS7# VSS
[5] M_B_DQS_DP[7:0] 145
M_B_DQS_DP1 VSS
12 150
M_B_DQS_DP0 DQS0 VSS
29 151
M_B_DQS_DP2 DQS1 VSS
47 155
M_B_DQS_DP3 DQS2 VSS
64 156
M_B_DQS_DP4 DQS3 VSS
137 161
M_B_DQS_DP5 DQS4 VSS
154 162
M_B_DQS_DP6 DQS5 VSS
171 167
M_B_DQS_DP7 DQS6 VSS
188 168
DQS7 VSS 0D675V_S0
172
VSS
116 173
[5] M_B_DIMB_ODT0 ODT0 VSS
120 178
Layout Note: [5] M_B_DIMB_ODT1 ODT1 VSS
179
VSS
All VREF traces should M_VREF_CA_DIMMB 126
VREF_CA VSS
184
1 185 1U 0402 x 3

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
have width=20mil; M_VREF_DQ_DIMMB VREF_DQ VSS

C1307

C1304

C1303
189

1
spacing=20 mil VSS
30 190
[5,12] DDR3_DRAMRST# RESET# VSS
195
VSS
196

2
VSS
0D675V_S0 203 205
2

VTT1 VSS
204 206
1

VTT2 VSS

DY C1301
Do Not Stuff DYD1319
2

Do Not Stuff DDR3-204P-259-GP

Do Not Stuff
1

62.10024.S11

Place these Caps near DIMM2.

close to dimm
close to dimm

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DDR3-SODIMM2
Size Document Number Rev
A2 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 13 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C
(Blanking) C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)_SODIMM _SODIMM4
Size Document Number Rev
A4 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 14 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

CPU1I 9 OF 20
3D3V_S0
SKYLAKE_ULT

Vinafix.com
CSI-2
R1503
A36 C37 W IFI_RF_EN 2 1
B36
CSI2_DN0 CSI2_CLKN0
D37
DY
CSI2_DP0 CSI2_CLKP0 Do Not Stuff
D C38 CSI2_DN1 CSI2_CLKN1 C32 D
D38 CSI2_DP1 CSI2_CLKP1 D32
C36 CSI2_DN2 CSI2_CLKN2 C29
D36 CSI2_DP2 CSI2_CLKP2 D29 DC resistance < 0.5ohm.
A38 CSI2_DN3 CSI2_CLKN3 B26
B38 CSI2_DP3 CSI2_CLKP3 A26
R1501
C31 E13 CSI2_COMP 1 2 100R2F-L1-GP-U
CSI2_DN4 CSI2_COMP
D31 CSI2_DP4 GPP_D4/FLASHTRIG B7 W IFI_RF_EN [61]
C33 CSI2_DN5
D33 CSI2_DP5 EMMC
A31 CSI2_DN6
B31 CSI2_DP6 GPP_F13/EMMC_DATA0 AP2
A33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP1 [#545659 Rev0.7]
B33 CSI2_DP7 GPP_F15/EMMC_DATA2 AP3
GPP_F16/EMMC_DATA3 AN3 GPP_F: VCCPGPPF = 1.8V Only
A29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN1
B29 CSI2_DP8 GPP_F18/EMMC_DATA5 AN2
C28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM4
D28 CSI2_DP9 GPP_F20/EMMC_DATA7 AM1
A27 CSI2_DN10
B27 CSI2_DP10 GPP_F21/EMMC_RCLK AM2
C27 CSI2_DN11 GPP_F22/EMMC_CLK AM3
D27 CSI2_DP11 GPP_F12/EMMC_CMD AP4 R1502
AT1 EMMC_RCOMP 1 2
EMMC_RCOMP
SKYLAKE-GP-U 200R2F-L-GP
C C
071.SKYLA.000U

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(CS-2/EMMC)
Size Document Number Rev
A3 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 15 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

#543016:
CPU1H 8 OF 20 (#545659) The xHCI controller supports USB Debug port on all USB3.0 capable ports.
220 nF nominal capacitors are recommended for Gen 3.
100 nF nominal capacitors are recommended for Gen 2. SKYLAKE_ULT
SSIC / USB3
PCIE/USB3/SATA
H8 USB30_RX_CPU_N1 [36]
USB3_1_RXN
G8 USB30_RX_CPU_P1 [36]
USB3_1_RXP
[73] CPU_RXN_C_dGPU_TXN0 H13 C13 USB30_TX_CPU_N1 [36]
PCIE1_RXN/USB3_5_RXN USB3_1_TXN USB1 (USB3.0 Port1)
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[73] CPU_RXP_C_dGPU_TXP0 SCD22U10V2KX-1GP G13 D13 USB30_TX_CPU_P1 [36]
C1606 1 PEG_TX_CPU_N0 PCIE1_RXP/USB3_5_RXP USB3_1_TXP
[73] dGPU_RXN_C_CPU_TXN0 2OPS B17
C1605 1 PEG_TX_CPU_P0 PCIE1_TXN/USB3_5_TXN
[73] dGPU_RXP_C_CPU_TXP0 2OPS A17 J6 USB30_RX_CPU_N2 [36]
SCD22U10V2KX-1GP PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN
H6
[73] CPU_RXN_C_dGPU_TXN1 G11
PCIE2_RXN/USB3_6_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
B13
USB30_RX_CPU_P2 [36]
USB30_TX_CPU_N2 [36] USB2 (USB3.0 Port2)
[73] CPU_RXP_C_dGPU_TXP1 SCD22U10V2KX-1GP F11 A13 USB30_TX_CPU_P2 [36]
D C1608 1 PEG_TX_CPU_N1 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP D
[73] dGPU_RXN_C_CPU_TXN1 2OPS D16
C1607 1 PEG_TX_CPU_P1 PCIE2_TXN/USB3_6_TXN
[73] dGPU_RXP_C_CPU_TXP1 2OPS C16 J10
SCD22U10V2KX-1GP PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN
H10
USB3_3_RXP/SSIC_2_RXP
[73] CPU_RXN_C_dGPU_TXN2 H16 B15
GPU [73] CPU_RXP_C_dGPU_TXP2 SCD22U10V2KX-1GP G16
PCIE3_RXN
PCIE3_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
A15
[73] dGPU_RXN_C_CPU_TXN2 C1610 1 2OPS PEG_TX_CPU_N2 D17
C1609 1 PEG_TX_CPU_P2 PCIE3_TXN
[73] dGPU_RXP_C_CPU_TXP2 2OPS C17 E10
SCD22U10V2KX-1GP PCIE3_TXP USB3_4_RXN
F10
USB3_4_RXP
[73] CPU_RXN_C_dGPU_TXN3 G15 C15
SCD22U10V2KX-1GP PCIE4_RXN USB3_4_TXN
[73] CPU_RXP_C_dGPU_TXP3 F15 D15
C1612 1 PEG_TX_CPU_N3 PCIE4_RXP USB3_4_TXP
[73] dGPU_RXN_C_CPU_TXN3 2OPS B19
C1611 1 PEG_TX_CPU_P3 PCIE4_TXN
[73] dGPU_RXP_C_CPU_TXP3 2OPS A19 AB9 USB_CPU_PN0 [36]
SCD22U10V2KX-1GP PCIE4_TXP USB2N_1
USB2P_1
AB10 USB_CPU_PP0 [36]
USB1 (USB3.0 port1)
[61] PCIE_RX_CPU_N5 F16
SCD1U16V2KX-3GP PCIE5_RXN
[61] PCIE_RX_CPU_P5 E16 AD6 USB_CPU_PN1 [36]
WLAN [61] PCIE_TX_CON_N5 C1601 1 2 PCIE_TX_CPU_N5 C19
PCIE5_RXP
PCIE5_TXN
USB2N_2
USB2P_2
AD7 USB_CPU_PP1 [36] USB2 (USB3.0 Port2)
[61] PCIE_TX_CON_P5 C1602 1 2 PCIE_TX_CPU_P5 D19
SCD1U16V2KX-3GP PCIE5_TXP
AH3 USB_CPU_PN2 [37]
[31] PCIE_RX_CPU_N6 G18
PCIE6_RXN
USB2N_3
USB2P_3
AJ3 USB_CPU_PP2 [37]
USB3 (IO BD/USB2.0 Port3)
[31] PCIE_RX_CPU_P6 SCD1U16V2KX-3GP F18
C1603 1 PCIE_TX_CPU_N6 PCIE6_RXP
[31] PCIE_TX_CON_N6 2 D20 AD9 USB_CPU_PN3 [92]
LAN [31] PCIE_TX_CON_P6 C1604 1 2 PCIE_TX_CPU_P6 C20
PCIE6_TXN
PCIE6_TXP
USB2N_4
USB2P_4
AD10 USB_CPU_PP3 [92] Finger Print (USB2.0 Port4)
SCD1U16V2KX-3GP
[60] SATA_RX_CPU_N0 F20 AJ1 USB_CPU_PN4 [55]
[60] SATA_RX_CPU_P0 E20
PCIE7_RXN/SATA0_RXN USB2N_5
AJ2 USB_CPU_PP4 [55]
CAMERA (USB2.0 Port5)
HDD1 [60] SATA_TX_CPU_N0 B21
PCIE7_RXP/SATA0_RXP
PCIE7_TXN/SATA0_TXN
USB2
USB2P_5
[60] SATA_TX_CPU_P0 A21 AF6 USB_CPU_PN5 [33]
PCIE7_TXP/SATA0_TXP USB2N_6
USB2P_6
AF7 USB_CPU_PP5 [33] Card Reader (USB2.0 Port6)
G21
PCIE8_RXN/SATA1A_RXN
F21 AH1 USB_CPU_PN6 [55]
D21
PCIE8_RXP/SATA1A_RXP
PCIE8_TXN/SATA1A_TXN
USB2N_7
USB2P_7
AH2 USB_CPU_PP6 [55]
Touch Panel (USB2.0 Port7)
C21
PCIE8_TXP/SATA1A_TXP
AF8 USB_CPU_PN7 [61]
E22
PCIE9_RXN
USB2N_8
USB2P_8
AF9 USB_CPU_PP7 [61]
WLAN (USB2.0 Port8)
1. Trace Width: 4 mils min (breakout) 12-15 mils (trace) E23
PCIE9_RXP
B23 AG1
Layout Note: Note: Must maintain low DC resistance routing (<0.1 ohm).
A23
PCIE9_TXN USB2N_9
AG2
2. Isolation Spacing: At least 12 mils to any adjacent PCIE9_TXP USB2P_9
DC resistance < 0.5ohm.
high speed I/O. F25 AH7
PCIE10_RXN USB2N_10
E25 AH8
PCIE10_RXP USB2P_10
D23
PCIE10_TXN USBCOMP
C23 AB6 1 R1603 2 113R2F-GP
PCIE10_TXP USB2_COMP
AG3
PCIE_RCOMPN USB2_ID
F5 AG4
R1604 1 PCIE_RCOMPP PCIE_RCOMPN USB2_VBUSSENSE
2 E5
100R2F-L1-GP-U PCIE_RCOMPP
A9 USB_OC0# [35]
GPP_E9/USB2_OC0#
[99] XDP_PRDY# D56 C9 USB_OC1# [35]
PROC_PRDY# GPP_E10/USB2_OC1#
[99] XDP_PREQ# D61 D9 USB_OC2# [35]
PIRQA# PROC_PREQ# GPP_E11/USB2_OC2#
C BB11 B9 USB_OC3# [24]
C
GPP_A7/PIRQA# GPP_E12/USB2_OC3#
E28
PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0
J1 HDD_DEVSLP [60] (#543016) When used as DEVSLP, no external pull-up or pull-down
E27 J2 SIO_EXT_SCI#_R termination required from SATA Host DEVSLP.
PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 SIO_EXT_SCI#_R [24]
D24 J3 LOM_CABLE_DETECT# [31]
PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
C24
3D3V_S0 PCIE11_TXP/SATA1B_TXP GPP_E0/SATAXPCIE0/SATAGP0
E30 H2 1
PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 TP1601 Do Not Stuff 3D3V_S5_PCH
F30
PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1
H3 1 (#543611)
A25 G4 GPP_E2/SATAXPCIE2/SATAGP2 1 TP1602 Do Not Stuff The SATALED# signal is open-collector and requires a weak
10KR2J-3-GP 2 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
1 R1607 PIRQA# B25 TP1603 Do Not Stuff RN1602
external pull-up (8.2 kΩ to 10 kΩ) to Vcc3_3.
PCIE12_TXP/SATA2_TXP USB_OC2#
H1 SATA_LED# [64] 8 1
GPP_E8/SATALED# USB_OC0# 7 2
USB_OC3# 6 3 3D3V_S0
SKYLAKE-GP-U USB_OC1# 5 4

PCIE Table USB 2.0 Table 071.SKYLA.000U SRN10KJ-6-GP SATA_LED# 2 R1606 1

10KR2J-3-GP
Port Device Share BUS Pair Device

1 N/A USB3.0_3 0 USB3.0 port1 LOM_CABLE_DETECT# 2 R1609 1

10KR2J-3-GP

2 N/A USB3.0_4 1 USB3.0 Port2

(#543016) Unused SATAGP[2:0]/GPP_E[2:0] pins must be terminated to either 3.3 V rail or GND SIO_EXT_SCI#_R 2 R1608 1
using 8.2 KΩ to 10 KΩ on the motherboard. 10KR2J-3-GP
3 WLAN 2 USB2.0 Port3 (IOBD) Do not use both pull-up and pull-down. Either pull-up or pull-down is acceptable.

4 LAN 3 Fringer print

5(L0~L3) GPU 4 CAMERA

6(L3) HDD SATA0 5 Card Reader

6(L2) N/A 6 Touch Panel

6(L0~L1) N/A 7 WLAN

#545659 (SKL_PCH_U_Y_EDS Rev0.7)

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(PCIE/SATA/USB)
Size Document Number Rev
Custom A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 16 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

3D3V_S5

R1709
1 2 AC_PRESENT +V3.3A_SIP +VCCPDSW_3P3

1 R1712 2
10KR2J-3-GP Do Not Stuff
R1714 DY
1 2 PCIE_WLAN_WAKE# 3D3V_S5 AC_PRESENT

Vinafix.com
1 R1711 2 EC1707

1
10KR2J-3-GP
DY
Do Not Stuff

Do Not Stuff
2
Layout note: 3 PAD SHARING [24,31,40,55,61,68,73,91] PLT_RST# 1 R1713 2 PCH_PLTRST#
D
+VCCPDSW_3P3 Do Not Stuff D

1
R1703

1
+VCCPRIM_3P3 R1715 C1701
1 2 PCH_WAKE# Do Not Stuff DY DY Do Not Stuff
1KR2J-1-GP [#543016 Rev0.7]

2
EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k

2
R1723

1
pull-down that is active during the early portion of the power up sequence
1 2 PCH_BATLOW# R1701
10KR2J-3-GP 3KR2J-2-GP CPU1K 11 OF 20
RTC_AUX_S5
SYSTEM POWER MANAGEMENT

2
R1730 #544669 (CRB): 330k. AT11 SIO_SLP_S0#
SKYLAKE_ULT GPP_B12/SLP_S0# SIO_SLP_S0# [24,27,40,51,52,54]
330KR2J-L1-GP AP15 SIO_SLP_S3# [24,27,40,51,52,54]
SM_INTRUDER# PCH_PLTRST# GPD4/SLP_S3#
1 2 AN10 BA16 SIO_SLP_S4# [24,40,51]
XDP_DBRESET# GPP_B13/PLTRST# GPD5/SLP_S4# SIO_SLP_S5# TP1703
[99] XDP_DBRESET# B5 AY16 1
SYS_RESET# GPD10/SLP_S5# Do Not Stuff
[99] PM_RSMRST# AY17
RSMRST#
AN15 SIO_SLP_SUS# [24,40,53,54]
R1710 Do Not Stuff H_CPUPWRGD SLP_SUS# SLP_LAN# TP1704
1 2 A68 AW15 1
#544669 Rev0.52 CRB: [40] H_THERMTRIP_EN H_VCCST_PWRGD_R DY 1 2 60D4R2F-GP H_VCCST_PWRGD B65
PROCPWRGD SLP_LAN#
BB17 AUX_EN_WOWL_R Do Not Stuff 1 2 R1721
No PL resistor on THERMTRIP#. R1734 VCCST_PWRGD GPD9/SLP_WLAN#
AN16 SIO_SLP_A# 1 TP1706 DY
Do Not Stuff
AUX_EN_WOWL [24,40,53,54]
SYS_PWROK GPD6/SLP_A# Do Not Stuff
[24] SYS_PWROK B6
H_CPUPWRGD R1706 PM_PCH_PWROK SYS_PWROK
[24,26,40] RESET_OUT# 1 2 Do Not Stuff BA20 BA15 SIO_PWRBTN# [24,99]
PM_RSMRST# PCH_DPWROK PCH_PWROK GPD3/PWRBTN# AC_PRESENT 3D3V_S5_PCH
1 R1704 2 BB20 AY15 AC_PRESENT [76]
Do Not Stuff DSW_PWROK GPD1/ACPRESENT PCH_BATLOW#
AU13
ME_SUS_PWR_ACK_R AR13 GPD0/BATLOW#

1
R1733 1 10KR2J-3-GP PM_RSMRST# [20] ME_SUS_PWR_ACK_R SUSACK#_R GPP_A13/SUSWARN#/SUSPWRDNACK
2 AP11 R1731
R1732 1 10KR2F-2-GP PM_PCH_PWROK R405 GPP_A15/SUSACK# PME#
2 AU11 1
PCIE_WAKE# R1705 PCH_WAKE# GPP_A11/PME# SM_INTRUDER# EXT_PWR_GATE#
DY Do Not Stuff 1 2 Do Not Stuff BB15 AP16 TP1707 Do Not Stuff 2 1
R1707 GPD2/LAN_WAKE# WAKE# INTRUDER#
+VCCPDSW_3P3 1 2 10KR2J-3-GP AM15 20KR2J-L2-GP
R1717 SYS_PWROK GPD2/LAN_WAKE# EXT_PWR_GATE#
2 DY 1 Do Not Stuff 2 AW17 AM10
GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# GPP_B2/VRALERT#
AT15
GPD7/USB2_WAKEOUT# GPP_B2/VRALERT#
AM11 1 BATLOW#:
TP1708 Do Not Stuff Pull-up required even if not implemented.
(PDG#543016)
WAKE#: Ensure that WAKE# signal Trise (Maximum) is <100 ns. SKYLAKE-GP-U
R1736 1 2 GPD2/LAN_WAKE#
[24] EC_WAKE#
Do Not Stuff DY 071.SKYLA.000U D1703
RB751V-40H-GP

A K PWR_CHG_ACOK [24,44]
C C
3D3V_S5 Q1702
U1702
83.R2004.G8FAC_PRESENT
4 3
+VCCMPHYGTAON_1P0 D1702 3D3V_AUX_S5
5NON PM_RSMRST#_R
1 R1720 PM_RSMRST#
1
NC#1 VCC
5 R1737 DS3
2 2
[31] PCIE_LAN_WAKE# 2
C1703 3D3V_S5 PM_RSMRST#_M Do Not Stuff
[24,40] SIO_SLP_S3# 2
DY 1 NON DS3
2 6 1

1
A

Do Not Stuff

SCD1U16V2KX-3GP
3 PCIE_WAKE#
SKL: 1.0V 3
GND Y
4
DY C1702
+VCCSTG
100KR2J-1-GP 2N7002KDW-GP
+VCCMPHYGTAON_1P0(ICCMAX.=3.5A) [61] PCIE_WLAN_WAKE# 1 84.2N702.A3F

1
2nd = 84.2N702.E3F
BAW56-9-GP Do Not Stuff 3rd = 75.00601.07C
1D0V_S5 +VCCMPHYGTAON_1P0_LS_SIP 4th = 84.DMN66.03F
75.00056.07D Do Not Stuff

2
D1701

1
1 R1724 2 K A U1701 R1722
1KR2J-1-GP
1N4148WS-7-F-GP 1 5
Do Not Stuff NC#1 VCC

2
1

2
1 R1735 2 C1704 For EMI Reserved [24,40] ALL_SYS_PWRGD A
SC10U10V5KX-2GP 3 4 H_VCCST_PWRGD_R
PM_PCH_PWROK
H_CPUPWRGD
2

GND Y
Do Not Stuff EC1708

1
74LVC1G07GW-GP
73.01G07.0HG DY

Do Not Stuff
2
1 DY 2
2

R1716
EC1710 DY EC1713 DY Do Not Stuff

1
VCCST_PWRGD / HWM201:
1

1
Do Not Stuff

Do Not Stuff

R1719

1
Do Not Stuff
EC1709
DY
DY
Do Not Stuff

2
B B
Layout Note:
close to CPU1

XDP_DBRESET#
SYS_PWROK
PLT_RST#
RESET_OUT#
DS3 BOM Option
ME_SUS_PWR_ACK_R 1 R1708 2 SUSACK#_R
1

Do Not Stuff PCH_DPWROK R1718 1 DS3 2 Do Not Stuff DY DY DY DY

3V_5V_POK [40,45,53,54]
RN1702 EC1706 EC1702 EC1703 EC1704
2 3 SUSACK#_R
[24] SUSACK# DS3
2

2
2

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

1 4 ME_SUS_PWR_ACK_R
[24] ME_SUS_PWR_ACK
DS3 R1725
Do Not Stuff Do Not Stuff

#543016 Rev0.7
1

1. VCCST_PWRGD is only 1.0 V tolerant.

3D3V_AUX_S5 R1727
2. VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST
100KR2J-1-GP
1 2
NON DS3
2

R1726
10KR2J-3-GP

1KR2J-1-GP
Q1701
1

R1702
4 3 PM_RSMRST# 1 2 PCH_RSMRST# [24]
3V_5V_POK# 5 2 3V_5V_POK_C 1 R1728 2
3V_5V_POK [40,45,53,54]
Do Not Stuff
6 1 EC1711 EC1712
1

DY DY
2N7002KDW-GP DS3
Do Not Stuff

Do Not Stuff

A R1729 1 SIO_SLP_SUS# A
2
2

Do Not Stuff

84.2N702.A3F
2nd = 84.2N702.E3F <Core Design>
3rd = 75.00601.07C
4th = 84.DMN66.03F
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU_(POWER MANAGEMENT)
Size Document Number Rev
A2 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 17 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH PCH strap pin: PCH Prim

PCH strap pin: PCH Prim
eSPI or LPC Sampled at rising edge of RSMRST# 3D3V_S5_PCH
BOOT HALT 3D3V_S5_PCH
SML0ALERT# / This signal has a weak internal pull-down. 3D3V_S5_PCH

1
0 = LPC Is selected for EC. SPI0_MOSI 0 = ENABLED
GPP_C5

1
1 = eSPI Is selected for EC. DY R1822 1 = DISABLED
Do Not Stuff WEAK INTERNAL PU DY R1824 RN1807
This signal has a weak internal pull-down. Do Not Stuff SML1_SMBDATA 8 1
This signal has a weak internal pull-up. SML1_SMBCLK 7 2

2
SML0_SMBDATA
PCH strap pin: 6 3

2
GPP_C5/SML0ALERT# SML0_SMBCLK 5 4
SPI_SI_CPU

Vinafix.com

1
SRN2K2J-4-GP
No Reboot Sampled at rising edge of PCH_PWROK

1
DY R1823
Do Not Stuff DY R1825
Do Not Stuff SMBALERT# / 0 = Disable Intel ME Crypto Transport Layer Security R1820
D (TLS) cipher suite (no confidentiality). GPP_B23/SML1ALERT# 2 1 150KR2F-L-GP D
GPP_C2

2
1 = Enable Intel ME Crypto Transport Layer Security

2
3D3V_S5_PCH (TLS) cipher suite (with confidentiality). Must be R1821
3D3V_S5_PCH PLACE WITHIN 1.1 INCH OF PCH pulled up to support Intel AMT with TLS and Intel GPP_C2/SMBALERT# 1 2 2K2R2J-2-GP
(#543016)Optional, can be left as OPEN/No-Connect. SBA (Small Business Advantage) with TLS.
R1826
1

1 2 SPI_SI_CPU The signal has a weak internal pull-down. SRN2K2J-1-GP

[99] SPI0_MOSI_XDP
1

R1835 DY Do Not Stuff

R1834 1KR2J-1-GP MEM_SMBCLK 3 2
1KR2J-1-GP R1827 MEM_SMBDATA 4 1
1 DY 2 SPI_WP_CPU
2

[99] XDP_SPI0_IO2
RN1811
2

SPI_HOLD_CPU Do Not Stuff LPC_LAD[3..0] 20140820 DAIVD

[24,68] LPC_LAD[3..0]
RN1806
1

LPC_LAD0 8 1 LPC_LAD0_R
R1836 LPC_LAD2 7 2 LPC_LAD2_R
SPI_WP_CPU LPC_LAD1 LPC_LAD1_R
DY Do Not Stuff
LPC_LAD3
6 3
LPC_LAD3_R
5 4
2

SRN0J-7-GP-U
3D3V_S0 CPU1E 5 OF 20
Resister value will check later
SPI - FLASH
SMBUS, SMLINK
R2021 SKYLAKE_ULT 3D3V_S5_PCH
10R2F-L-GP 1 2 R1806 SPI_CLK_CPU AV2 R7 MEM_SMBCLK
[24,25,91] SPI_CLK_ROM SPI0_CLK GPP_C0/SMBCLK
1 2 SIO_RCIN# 10R2F-L-GP 1 2 R1807 SPI_SO_CPU AW3 R8 MEM_SMBDATA
[24,25,91] SPI_SO_ROM SPI0_MISO GPP_C1/SMBDATA
10KR2J-3-GP 10R2F-L-GP 1 2 R1808 SPI_SI_CPU AV3 Strap R10 GPP_C2/SMBALERT#
[24,25,91] SPI_SI_ROM SPI0_MOSI
R2032 [25] SPI_WP_ROM
10R2F-L-GP 1 2 R1809 SPI_WP_CPU AW2
SPI0_IO2 Strap GPP_C2/SMBALERT# R1814 3D3V_S0
10R2F-L-GP 1 2 R1811 SPI_HOLD_CPU AU4 R9 SML0_SMBCLK SUS_STAT#/LPCPD# 2 DY 1
[25] SPI_HOLD_ROM SPI0_IO3 GPP_C3/SML0CLK
1 2 SERIRQ Do Not Stuff 1 2 R1812 SPI_CS_CPU_N0 AU3 W2 SML0_SMBDATA
[24,25] SPI_CS_ROM_N0 SPI0_CS0# GPP_C4/SML0DATA
10KR2J-3-GP Do Not Stuff 1 2 R1828 SPI_CS_CPU_N1 AU2 W1 GPP_C5/SML0ALERT# Do Not Stuff RN1810
[25] SPI_CS_ROM_N1
[91] SPI_CS2#_R Do Not Stuff 1
DY 2 R1816 PCH_SPI_CS2# AU1
SPI0_CS1# Strap GPP_C5/SML0ALERT# 3D3V_S0 3 2 3D3V_S0
SPI0_CS2# R1818
SERIRQ PH: GPP_C6/SML1CLK
W3 SML1_SMBCLK [24,26,76] 4 1
PDG: 8.2k V3 8K2R2F-1-GP
SPI - TOUCH GPP_C7/SML1DATA SML1_SMBDATA [24,26,76]
AM7 GPP_B23/SML1ALERT# CLKRUN#_R 1 2 SRN10KJ-5-GP
CRB: 10k Do Not Stuff TP1801 CPU_D1_TP GPP_B23/SML1ALERT#/PCHHOT#
1 M2 2N7002KDW-GP
GPP_D1/SPI1_CLK
[67] HDD_FALL_INT M3
GPP_D2/SPI1_MISO MEM_SMBDATA
[67] HDD_PWR_EN J4 6 1 PCH_SMBDATA [12,13,65,66,67,99]
Do Not Stuff TP1804 CPU_D4_TP GPP_D3/SPI1_MOSI
1 V1
Do Not Stuff TP1805 CPU_D5_TP GPP_D21/SPI1_IO2
1 V2
GPP_D22/SPI1_IO3 84.2N702.A3F 5 2
Do Not Stuff TP1806 1 CPU_D6_TP M1 LPC AY13 LPC_LAD0_R 2nd = 84.2N702.E3F
GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0 LPC_LAD1_R
C
GPP_A2/LAD1/ESPI_IO1
BA13 3rd = 75.00601.07C 4 3 C
BB13 LPC_LAD2_R 4th = 84.DMN66.03F
C LINK GPP_A3/LAD2/ESPI_IO2 LPC_LAD3_R
AY12 Q1801
GPP_A4/LAD3/ESPI_IO3 LPC_LFRAME#_R R1801 1
[61] CL_CLK G3 BA12 2 LPC_LFRAME# [24,68]
CL_CLK GPP_A5/LFRAME#/ESPI_CS# SUS_STAT#/LPCPD# Do Not Stuff
[61] CL_DATA G2 BA11
CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET#
[61] CL_RST# G1 PCH_SMBCLK [12,13,65,66,67,99]
CL_RST#
AW9 PCI_CLK_LPC0
GPP_A9/CLKOUT_LPC0/ESPI_CLK PCI_CLK_LPC1 MEM_SMBCLK
RCIN#: [24] SIO_RCIN# AW13
GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1
AY9
Frequency to Avoid: 33 MHz AW11 CLKRUN#_R 1 R1819 2
GPP_A8/CLKRUN# CLKRUN# [24]
[24] SERIRQ AY11 Do Not Stuff
GPP_A6/SERIRQ

SKYLAKE-GP-U

071.SKYLA.000U
1

Do Not Stuff
EC1805

DY PCI_CLK_LPC0 R1804 1 LPC 2 Do Not Stuff CLK_PCI_LPC [68]

PCI_CLK_LPC1 R1805 1 2 22R2J-2-GP CLK_PCI_LPC_MEC [24]
2

EC1801
Do Not Stuff

EC1802
Do Not Stuff
1

1
DY DY

2
3D3V_S0 RTC_X1
C1801
1 2 RTC_X2 XTAL24_IN 1 R1810 2 XTAL24_IN_R 2 1
1 R1817 2 CLKREQ_PEG#0 R1815 10MR2J-L-GP Do Not Stuff
10KR2J-3-GP
CLKREQ_PCIE#1 SC15P50V2JN-2-GP
1 R1829 2 X1802

1
B 10KR2J-3-GP B
1 R1830 2 CLKREQ_PCIE#2 X1801

1
10KR2J-3-GP 4 1 XTAL-24MHZ-81-GP
1 R1831 2 CLKREQ_PCIE#3 R1802
10KR2J-3-GP 1MR2J-1-GP 82.30004.841

1
1 R1832 2 CLKREQ_PCIE#4 C1804 C1803

4
10KR2J-3-GP SC5P50V2CN-2GP 3 2 SC5P50V2CN-2GP

2
C1802
1 R1833 2 CLKREQ_PCIE#5

2
10KR2J-3-GP XTAL24_OUT 2 1
CPU1J 10 OF 20
SC15P50V2JN-2-GP
CLOCK SIGNALS
XTAL-32D768KHZ-68-GP
[73] CLK_PCIE_VGA# D42
CLKOUT_PCIE_N0 SKYLAKE_ULT
GPU [73] CLK_PCIE_VGA C42
CLKOUT_PCIE_P0 82.30001.G01
[73] CLKREQ_PEG#0 AR10
GPP_B5/SRCCLKREQ0#
B42
WLAN [61] PEG_CLK1_CPU#
[61] PEG_CLK1_CPU A42
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1 CLKOUT_ITPXDP#
F43 PCIE_CLK_XDP_N [99]
SUSCLK_R
CLKREQ_PCIE#1 AT7 E43
[61] CLKREQ_PCIE#1 PCIE_CLK_XDP_P [99]

2
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P RTC_AUX_S5
D41 BA17 SUSCLK_R 1 R1813 2 DY EC1803
[31] PEG_CLK2_CPU# CLKOUT_PCIE_N2 GPD8/SUSCLK SUS_CLK [24]
C41 Do Not Stuff
LAN [31] PEG_CLK2_CPU

1
CLKOUT_PCIE_P2 +VCCF24NS_1P0_L

Do Not Stuff
AT8 E37 XTAL24_IN
[31] CLKREQ_PCIE#2 GPP_B7/SRCCLKREQ2# XTAL24_IN
E35 XTAL24_OUT +V1.05S_AXCK_LCPLL

2
1
XTAL24_OUT
D40
CLKOUT_PCIE_N3 XCLK_BIASREF
C40 E42 1 R1803 2 RN1901
CLKREQ_PCIE#3 CLKOUT_PCIE_P3 XCLK_BIASREF 2K7R2F-GP
AT10 SRN20KJ-1-GP
GPP_B8/SRCCLKREQ3# RTC_X1
AM18
RTCX1 RTC_X2 Intel recommend: 2.71k ohm 5%
B40 AM20
CLKOUT_PCIE_N4 RTCX2
A40

3
4
CLKREQ_PCIE#4 CLKOUT_PCIE_P4 SRTC_RST#
AU8 AN18
GPP_B9/SRCCLKREQ4# SRTCRST# RTC_RST# Q1901
AM16
RTCRST#
E40 [24] RTCRST_ON G
CLKOUT_PCIE_N5 SRTC_RST#
E38
1
CLKREQ_PCIE#5 CLKOUT_PCIE_P5 RTC_RST#
AU7 D
GPP_B10/SRCCLKREQ5# R1902

SC1U10V2KX-1GP

2
10KR2J-3-GP S

1
C1901
G1901
1

1
Do Not Stuff

2N7002K-2-GP C1902
2

1
EC1808

Do Not Stuff

Do Not Stuff

Do Not Stuff
SKYLAKE-GP-U SC1U10V2KX-1GP
DY 84.2N702.J31

2
A A

EC1806

EC1807
2ND = 84.2N702.031 DY DY
2

2
071.SKYLA.000U 3rd = 84.07002.I31

2
(#514849)

<Core Design>
Layout: Place at the open door area.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
CPU_(LPC/SPI/SMBUS/CL/CLK)
Document Number Rev
A2 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 18 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

PCH strap pin:
Vinafix.com
Flash Descriptor Security Overide/
D D
Intel ME Debug Mode CPU1G 7 OF 20
Low = Default *
HDA_SDOUT High = Enable AUDIO
SKYLAKE_ULT
The internal pull-down is disabled after HDA_SYNC BA22
HDA_BITCLK HDA_SYNC/I2S0_SFRM
PLTRST# deasserts AY22 HDA_BLK/I2S0_SCLK
HDA_SDOUT BB22 SDIO/SDXC
HDA_SDO/I2S0_TXD
[27] HDA_SDIN0 BA21 HDA_SDI0/I2S0_RXD
AY21 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB11
HDA_RST# AW22 AB13
HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0
J5 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 AB12
AY20 I2S1_SFRM GPP_G3/SD_DATA2 W12
AW20 I2S1_TXD GPP_G4/SD_DATA3 W11
GPP_G5/SD_CD# W10
AK7 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W8 KB_LED_BL_DET [65]
AK6 GPP_F0/I2S2_SCLK GPP_G7/SD_WP W7
AK9 GPP_F2/I2S2_TXD
AK10 GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BA9
BB9 CPU_A16_TP 1 TP1902
C Do Not Stuff GPP_A16/SD_1P8_SEL Do Not Stuff C
[55] DMIC_PCH_CLK R1910 1 DY 2 DMIC_PCH_CLK_R H5 AB7 SD_RCOMP 1 R1901 2
R1913 1 DY DMIC_PCH_DATA_R D7 GPP_D19/DMIC_CLK0 SD_RCOMP
[55] DMIC_PCH_DATA 2 GPP_D20/DMIC_DATA0
Do Not Stuff 200R2F-L-GP
D8 GPP_D17/DMIC_CLK1 GPP_F23 AF13
[24,82,83] DGPU_PWROK DGPU_PWROK C8 GPP_D18/DMIC_DATA1
[27] SPKR SPKR AW5 GPP_B14/SPKR

SKYLAKE-GP-U

071.SKYLA.000U
PCH strap pin: 3D3V_S0

R2006 1 2 Do Not Stuff SPKR

DY R1907 HDA_BITCLK
NO REBOOT [27] HDA_CODEC_BITCLK 1 2 33R2J-2-GP
B B
[27] HDA_CODEC_SYNC R1908 1 2 HDA_SYNC
Low = Enable (Default) R1904 1 UMA2 Do Not Stuff DGPU_PWROK Do Not Stuff
HDA_SPKR
* R1911 1 2 HDA_RST#
High = Disable [27] HDA_CODEC_RST#
Do Not Stuff
EC1901 1 Do Not Stuff HDA_CODEC_BITCLK
The internal pull-down is disabled after DY2
R1912 1 2 33R2J-2-GP HDA_SDOUT
PLTRST# deasserts EC1902 2 Do Not Stuff HDA_CODEC_RST#
[27] HDA_CODEC_SDOUT
DY1 R1909
[24,98] ME_FWP_EC 1 2 1KR2J-1-GP

EC1903 2 DY1 Do Not Stuff DGPU_PWROK

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(AUDIO/SDIO/SDXC)
Size Document Number Rev
A4 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 19 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH PCH strap pin:

No Reboot Sampled at rising edge of PCH_PWROK

GSPI1_MOSI / This field determines the destination of accesses to the

GPP_B22 BIOS memory range. Also controllable using Boot BIOS
Destination bit (Chipset Configuration Registers: Offset
3410h:Bit 10). This strap is used in conjunction with Boot
EC2002 2 1 BIOS Destination Selection 0 strap.

Vinafix.com
DGPU_HOLD_RST# [73]
Bit 10 Boot BIOS Destination (PDG#543016) Ensure that all I2C interface on-board terminations are pulled up
SC1KP50V2KX-1GP 0 SPI to the same voltage rail as the device/end point.
RN2009 1 LPC
D 1 4 DGPU_HOLD_RST# D
DGPU_PWR_EN CPU1F 6 OF 20
2 OPS 3
The signal has a weak internal pull-down. LPSS ISH
SRN10KJ-5-GP
SKYLAKE_ULT

[76] GPU_EVENT# R2003 1GC6_202 Do Not Stuff GPU_EVENT_MCP# AN8 P2 USB_UART_SEL_D9 1 TP2006 Do Not Stuff
R2004 GPP_B15/GSPI0_CS# GPP_D9/ISH_SPI_CS#
[75,76,83] GC6_FB_EN 1GC6_202 Do Not Stuff GC6_FB_EN_MCP AP7 P3 DGPU_HOLD_RST#
VRAM_ID1 GPP_B16/GSPI0_CLK GPP_D10/ISH_SPI_CLK
AP8 P4
GPP_B18/GSPI0_MOSI GPP_B17/GSPI0_MISO GPP_D11/ISH_SPI_MISO RTC_DET#
AR7 P1 RTC_DET# [25]
GPP_B18/GSPI0_MOSI GPP_D12/ISH_SPI_MOSI
3D3V_S0
Strap
[55] DBC_PANEL_EN AM5 M4 I2C0_SDA
GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA I2C0_SCL
AN7 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL N3
AP5 GPP_B21/GSPI1_MISO
[66] SD_READ_MODE# AN5 N1 I2C1_SDA
51KR2J-1-GP R2048 LPSS_UART2_RXD GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA I2C1_SCL
2 1 Strap GPP_D8/ISH_I2C1_SCL
N2
51KR2J-1-GP 2 1 R2049 LPSS_UART2_TXD AB1
GPP_C8/UART0_RXD
[61] BLUETOOTH_EN AB2 AD11 1.8V Only
51KR2J-1-GP R2046 LPSS_UART2_CTS# GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA
2 1 [55] LCD_CBL_DET# W4 AD12
BOARD_ID2 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
AB3
10KR2J-3-GP GPP_C11/UART0_CTS#
2 1 R2009 KB_DET#
LPSS_UART2_RXD AD1 U1 DGPU_PWR_EN [82,83]
LPSS_UART2_TXD GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA UART0_TXD
AD2 GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK U2 1 TP2012 Do Not Stuff
3D3V_S0 AD3 U3 UART0_RTS# 1
[55] SIO_EXT_WAKE# GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# TP2013 Do Not Stuff
LPSS_UART2_CTS# AD4 U4 UART0_CTS# 1 TP2014 Do Not Stuff
GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
AC1 UART1_RXD 1 TP2015 Do Not Stuff
R2002 1 GPP_C12/UART1_RXD/ISH_UART1_RXD
2 Do Not Stuff BLUETOOTH_EN
DY PTP [65] I2C0_SDA_TCH_PAD
[65] I2C0_SCL_TCH_PAD
U7
U6
GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD
AC2
AC3 UART1_RTS# 1
FFS_INT2 [67]
GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# TP2016 Do Not Stuff
R2043 1 2 10KR2J-3-GP DBC_PANEL_EN AB4 UART1_CTS# 1
GPP_C15/UART1_CTS#/ISH_UART1_CTS# TP2017 Do Not Stuff
[60] HDD_DET# U8
R2044 1 GPP_C18/I2C1_SDA
2 10KR2J-3-GP HDD_DET# U9 AY8 PROJECT_ID1
GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 PROJECT_ID2
GPP_A19/ISH_GP1 BA8
R2047 1 2 10KR2J-3-GP LCD_CBL_DET# AH9 BB7 KB_DET# [65]
GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BOARD_ID3
AH10 GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 BA7
R2050 1 2 Do Not Stuff SD_READ_MODE#
C
DY AH11
GPP_A22/ISH_GP4
AY7
AW7 VRAM_ID2
IR_CAMERA_DET# [20] C

R2051 1 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5

2 10KR2J-3-GP IR_CAMERA_DET# AH12 GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6 AP13 PANEL_SIZE_ID [55]

AF11 GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL (PDG#543016) If the UART/GPIO functionality is also not used,
3D3V_S5_PCH the signals can be left as no-connect.
SKYLAKE-GP-U

R2039 1 2 Do Not Stuff

R2040 1 DY 2 10KR2J-3-GP RTC_DET# ME_SUS_PWR_ACK_R [17] 071.SKYLA.000U
R2041 1 2 10KR2J-3-GP SIO_EXT_WAKE# PCH Prim
3D3V_S0 3D3V_S0 GPP_A19 GPP_A18
3D3V_S5_PCH BIOS strap pin:
3D3V_S0
PCH strap pin: BIOS VRAM Size Strap pin PROJECT_ID2 PROJECT_ID1
1

Do Not Stuff

1
DY R2007 RN2007
No Reboot Sampled at rising edge of PCH_PWROK R2015 R2017
Do Not Stuff Iris2 0 0 I2C0_SCL 1 4
10KR2J-3-GP Do Not Stuff I2C0_SDA
0 = Disable “No Reboot” mode. DY 2 DY 3
GSPI0_MOSI / Loveland
2

GPP_B18 1 = Enable “No Reboot” mode (PCH will disable the TCO Loveland 0 1 RN2008

2
Timer system reboot feature). This function is useful GPP_B18/GSPI0_MOSI PROJECT_ID1 PROJECT_ID2
I2C1_SCL 1 4
when running ITP/XDP.
1

Tulip 0 0 I2C1_SDA 2 DY 3

1
DY R2019
The signal has a weak internal pull-down. Do Not Stuff R2016 R2018
Do Not Stuff Do Not Stuff Do Not Stuff
DY
Iris2
2

2
For debug USB/UART:
B B

3D3V_S0
5V_S5
5

DB2 3D3V_S0

1
1 R2025
N16V-GM
1

GPP_C11 10KR2J-3-GP GPP_A21

LPSS_UART2_TXD 2 R2005 BIOS strap pin: BIOS strap pin:
LPSS_UART2_RXD 3 20.F1897.004
OPS 10KR2J-3-GP

2
4 BIOS UMA/DIS Strap pin BOARD_ID2 BIOS UMA/DIS Strap pin BOARD_ID3
1LPSS_UART2_CTS# BOARD_ID3
2

TP2009 BOARD_ID2 UMA 0 N15V-GM-S 0

6

1
Do Not Stuff
ACES-CON4-37-GP R2026
1

DIS 1 Do Not Stuff N16V-GM 1

R2008 N15V-GM
Do Not Stuff
UMA

2
2

Intel has removed EHCI controller from BDW

and proposed to use UART interface for Win7 debug.
3D3V_S0 3D3V_S0
1

R2033 R2023 GPP_A23 GPP_B17

VRAM_4G Do Not Stuff VRAM_2G 10KR2J-3-GP BIOS strap pin:
BIOS VRAM Size Strap pin VRAM_ID2 VRAM_ID1
2

A A
VRAM_ID2 VRAM_ID1
1G 0 0
<Core Design>
1

R2034 R2024 2G 0 1
VRAM_1G / 2G10KR2J-3-GP VRAM_1G / 4G Do Not Stuff Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
4G 1 0 Taipei Hsien 221, Taiwan, R.O.C.
2

Title

CPU_(LPSS/ISH)
Size Document Number Rev
Custom A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 20 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

+VCCPRIM_1P0
CPU1O 15 OF 20
Vinafix.com CPU POWER 4 OF 4

AB19 VCCPRIM_1P0
D AB20 VCCPRIM_1P0 VCCPGPPA AK15 +VCCPGPPA D
+VCCPRIM_CORE P18 SKYLAKE_ULT AG15
VCCPRIM_1P0 VCCPGPPB +VCCPGPPB
VCCPGPPC Y16 +VCCPGPPC
2.57A AF18 VCCPRIM_CORE VCCPGPPD Y15 +VCCPGPPD
AF19 VCCPRIM_CORE VCCPGPPE T16 +VCCPGPPE
V20 VCCPRIM_CORE 1.8V Only VCCPGPPF AF16 +VCCPGPPF
V21 VCCPRIM_CORE VCCPGPPG AD15 +VCCPGPPG
+VCCDSW _1P0
C2120 AL1 V19 RTC_AUX_S5
DCPDSW_1P0 VCCPRIM_3P3_V19 +VCCPRIM_3P3
1

+VCCMPHYAON_1P0
K17 T1 +VCCDTS_1P0 C2119 C2118
VCCMPHYAON_1P0 VCCPRIM_1P0_T1

Do Not Stuff

SCD1U16V2KX-3GP
L1
2

VCCMPHYAON_1P0

1
+VCCMPHYGTAON_1P0_LS_SIP
SC1U10V2KX-1GP

AA1 +V1.8A_SIP DY C2117

VCCATS_1P8

SC1U10V2KX-1GP
N15 VCCMPHYGT_1P0_N15 +VCCPRTCPRIM_3P3
N16 AK17

2
VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +VCCPRTC_3P3
N17 VCCMPHYGT_1P0_N17
P15 VCCMPHYGT_1P0_P15 VCCRTC_AK19 AK19
+VCCAMPHYPLL_1P0 P16 BB14
VCCMPHYGT_1P0_P16 VCCRTC_BB14
K15 VCCAMPHYPLL_1P0 DCPRTC BB10 VCCRTCEXT C2112 1 2 SCD1U16V2KX-3GP
L15 VCCAMPHYPLL_1P0
+VCCAPLL_1P0 A14
V15
VCCCLK1 +VCC19P2_1P0 CAP need close to VCCRTC
+V1.00A_SIP VCCAPLL_1P0
VCCCLK2 K19 +VCCF100_1P0_L
AB17 VCCPRIM_1P0_AB17
Y18 VCCPRIM_1P0_Y18 VCCCLK3 L21 +VCCF135_1P0
+VCCPDSW _3P3
AD17 VCCDSW_3P3_AD17 VCCCLK4 N20 +VCCF100OC_1P0_L
AD18 VCCDSW_3P3_AD18
C +VCCPAZIO AJ17 L19 C
VCCDSW_3P3_AJ17 VCCCLK5 +VCCF24NS_1P0_L
AJ19 VCCHDA VCCCLK6 A10 +VCC24TBT_1P0

+VCCPSPI AJ16 VCCSPI GPP_B0/CORE_VID0 AN11 V0.85A_VID0 1 TP2101 Do Not Stuff

GPP_B1/CORE_VID1 AN13 V0.85A_VID1 1 TP2102 Do Not Stuff
+VCCSRAM_1P0 AF20 VCCSRAM_1P0
AF21 VCCSRAM_1P0
T19 VCCSRAM_1P0
T20 VCCSRAM_1P0
+VCCPRIM_3P3
AJ21 VCCPRIM_3P3_AJ21
+VCCFHV
AK20 +VCCPRTC_3P3
VCCPRIM_1P0_AK20 RTC_AUX_S5
+VCCAPLLEBB_1P0 N18 VCCAPLLEBB

SKYLAKE-GP-U 1 R2106 2
Do Not Stuff
071.SKYLA.000U

+VCCPRIM_1P0 +VCCPRIM_CORE +VCCDSW _1P0 +VCCMPHYAON_1P0 +VCCPRIM_3P3 +VCCPGPPC +VCCPGPPE +V1.8A_SIP +VCCPRTCPRIM_3P3 +VCC24TBT_1P0
B B
C2101

C2102

C2103

C2104

C2105

C2106

C2107

C2108

C2109

C2116
1

1
Do Not Stuff

Do Not Stuff

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
DY DY C2110 C2111

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
2

2
+VCCF100_1P0_L +VCCF24NS_1P0_L +VCCF100OC_1P0_L
SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

C2113 C2115 C2114

1

1
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(POWER1)
Size Document Number Rev
A3 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 21 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

Vinafix.com
D D

CPU1T 20 OF 20
SKYLAKE_ULT
SPARE

AW69 RSVD_AW69 RSVD_F6 F6

AW68 RSVD_AW68 RSVD_E3 E3
AU56 RSVD_AU56 RSVD_C11 C11
AW48 RSVD_AW48 RSVD_B11 B11
C7 RSVD_C7 RSVD_A11 A11
U12 RSVD_U12 RSVD_D12 D12
U11 RSVD_U11 RSVD_C12 C12
H11 RSVD_H11 RSVD_F52 F52

C SKYLAKE-GP-U C

071.SKYLA.000U

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(RSVD)
Size Document Number Rev
A4 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 22 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

CPU1P 16 OF 20

Do Not Stuff
GND 1 OF 3

SKYLAKE_ULT
Vinafix.com CPU1Q 17 OF 20 CPU1R 18 OF 20
TP2307 1NCTF_A5 A5 AL65
VSS VSS GND 2 OF 3
D A67 VSS VSS AL66 GND 3 OF 3 D
TP2301 1NCTF_A70 A70 AM13 F8 L18
VSS VSS SKYLAKE_ULT VSS VSS
AA2 VSS VSS AM21 AT63 VSS VSS BA49 G10 VSS VSS L2
AA4 AM25 AT68 BA53 G22 SKYLAKE_ULT L20
Do Not Stuff VSS VSS VSS VSS VSS VSS
AA65 VSS VSS AM27 AT71 VSS VSS BA57 G43 VSS VSS L4
AA68 VSS VSS AM43 AU10 VSS VSS BA6 G45 VSS VSS L8
AB15 VSS VSS AM45 AU15 VSS VSS BA62 G48 VSS VSS N10
AB16 VSS VSS AM46 AU20 VSS VSS BA66 G5 VSS VSS N13
AB18 AM55 AU32 BA71 NCTF_BA71 1 TP2303 G52 N19
VSS VSS VSS VSS VSS VSS
AB21 VSS VSS AM60 AU38 VSS VSS BB18 G55 VSS VSS N21
AB8 AM61 AV1 BB26 Do Not Stuff G58 N6
VSS VSS VSS VSS VSS VSS
AD13 VSS VSS AM68 AV68 VSS VSS BB30 G6 VSS VSS N65
AD16 VSS VSS AM71 AV69 VSS VSS BB34 G60 VSS VSS N68
AD19 VSS VSS AM8 AV70 VSS VSS BB38 G63 VSS VSS P17
AD20 VSS VSS AN20 AV71 VSS VSS BB43 G66 VSS VSS P19
AD21 VSS VSS AN23 AW10 VSS VSS BB55 H15 VSS VSS P20
AD62 VSS VSS AN28 AW12 VSS VSS BB6 H18 VSS VSS P21
AD8 VSS VSS AN30 AW14 VSS VSS BB60 H71 VSS VSS R13
AE64 VSS VSS AN32 AW16 VSS VSS BB64 J11 VSS VSS R6
AE65 AN33 AW18 BB67 Do Not Stuff J13 T15
VSS VSS VSS VSS NCTF_BB70 1 TP2304 VSS VSS
AE66 VSS VSS AN35 AW21 VSS VSS BB70 J25 VSS VSS T17
AE67 AN37 AW23 C1 NCTF_C1 1 TP2308 J28 T18
VSS VSS VSS VSS VSS VSS
AE68 VSS VSS AN38 AW26 VSS VSS C25 J32 VSS VSS T2
AE69 AN40 AW28 C5 Do Not Stuff J35 T21
VSS VSS VSS VSS VSS VSS
AF1 VSS VSS AN42 AW30 VSS VSS D10 J38 VSS VSS T4
AF10 VSS VSS AN58 AW32 VSS VSS D11 J42 VSS VSS U10
AF15 VSS VSS AN63 AW34 VSS VSS D14 J8 VSS VSS U63
AF17 VSS VSS AP10 AW36 VSS VSS D18 K16 VSS VSS U64
AF2 VSS VSS AP18 AW38 VSS VSS D22 K18 VSS VSS U66
C AF4 AP20 D25 K22 U67 C
VSS VSS VSS VSS VSS
AF63 VSS VSS AP23 AW41 VSS VSS D26 K61 VSS VSS U69
AG16 VSS VSS AP28 AW43 VSS VSS D30 K63 VSS VSS U70
AG17 VSS VSS AP32 AW45 VSS VSS D34 K64 VSS VSS V16
AG18 VSS VSS AP35 AW47 VSS VSS D39 K65 VSS VSS V17
AG19 VSS VSS AP38 AW49 VSS VSS D44 K66 VSS VSS V18
AG20 VSS VSS AP42 AW51 VSS VSS D45 K67 VSS VSS W13
AG21 VSS VSS AP58 AW53 VSS VSS D47 K68 VSS VSS W6
AG71 VSS VSS AP63 AW55 VSS VSS D48 K70 VSS VSS W9
AH13 VSS VSS AP68 AW57 VSS VSS D53 K71 VSS VSS Y17
AH6 VSS VSS AP70 AW6 VSS VSS D58 L11 VSS VSS Y19
AH63 VSS VSS AR11 AW60 VSS VSS D6 L16 VSS VSS Y20
AH64 VSS VSS AR15 AW62 VSS VSS D62 L17 VSS VSS Y21
AH67 VSS VSS AR16 AW64 VSS VSS D66
AJ15 VSS VSS AR20 AW66 VSS VSS D69
AJ18 VSS VSS AR23 AW8 VSS VSS E11
AJ20 VSS VSS AR28 AY66 VSS VSS E15
AJ4 AR35 B10 E18 SKYLAKE-GP-U
VSS VSS VSS VSS
AK11 VSS VSS AR42 B14 VSS VSS E21
AK16 AR43 B18 E46
AK18
VSS VSS
AR45 B22
VSS VSS
E50
071.SKYLA.000U
VSS VSS VSS VSS
AK21 VSS VSS AR46 B30 VSS VSS E53
AK22 VSS VSS AR48 B34 VSS VSS E56
AK27 VSS VSS AR5 B39 VSS VSS E6
AK63 VSS VSS AR50 B44 VSS VSS E65
AK68 VSS VSS AR52 B48 VSS VSS E71
AK69 VSS VSS AR53 B53 VSS VSS F1
AK8 VSS VSS AR55 B58 VSS VSS F13
AL2 VSS VSS AR58 B62 VSS VSS F2
B Do Not Stuff B
AL28 VSS VSS AR63 B66 VSS VSS F22
AL32 AR8 TP2302 1NCTF_B71 B71 F23
VSS VSS TP2305 VSS VSS
AL35 VSS VSS AT2 1NCTF_BA1 BA1 VSS VSS F27
AL38 AT20 Do Not Stuff BA10 F28
VSS VSS VSS VSS
AL4 VSS VSS AT23 BA14 VSS VSS F32
AL45 VSS VSS AT28 BA18 VSS VSS F33
AL48 AT35 TP2306 1NCTF_BA2 BA2 F35
VSS VSS Do Not Stuff VSS VSS
AL52 VSS VSS AT4 BA23 VSS VSS F37
AL55 VSS VSS AT42 BA28 VSS VSS F38
AL58 VSS VSS AT56 BA32 VSS VSS F4
AL64 VSS VSS AT58 BA36 VSS VSS F40
F68 VSS VSS F42
BA45 VSS VSS BA41
SKYLAKE-GP-U

071.SKYLA.000U SKYLAKE-GP-U

071.SKYLA.000U

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(VSS)
Size Document Number Rev
A3 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 23 of 105
5 4 3 2 1
 5 4 3 2 1

3D3V_S5
Main Func = KBC Board_ID_DET(GPIO153) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
3D3V_S5 Reserved 100.0K 10.0K 3.0V
3D3V_S5 3D3V_S5_KBC 3D3V_S5_KBC R2442 MODEL_ID_DET(GPIO153) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

1
Reserved 100.0K 17.8K 2.75V Do Not Stuff
Love_land_UMA_X01 100.0K 4.99K(64.49925.6DL) 3.143V

1
1D0V_S5 R2443 Reserved 100.0K 33.0K 2.48V Love_land_UMA_X02 100.0K 16.2K(64.16225.6DL) 2.840V
3D3V_S5
MODEL_ID
1 R2446 2 Do Not Stuff Love_land_UMA_A00 100.0K 28.7K(64.28725.6DL) 2.564V
1 R2402 2 EC_VTT Do Not Stuff PCB_REV Reserved 100.0K 47.0K 2.24V Reserved 100.0K 43K(64.43025.6DL) 2.307V

2
1

2
Do Not Stuff Reserved 100.0K 59K(64.59025.6DL) 2.075V
C2406 Reserved 100.0K 64.9K 2.0V MODEL_ID_C Love_land_DIS_X01 100.0K 76.8K(64.76825.6DL) 1.866V

2
R2462 Love_land_DIS_X02 100.0K 100K(64.10035.6DL) 1.650V

1
SCD1U16V2KX-3GP
+VCCSTG Do Not Stuff BOARD_ID_C Reserved 100.0K 76.8K 1.87V Love_land_DIS_A00 100.0K 130K(64.13035.6DL) 1.435V
R2440

2
C2407 R2441 Reserved 100.0K 169K(64.16935.6DL) 1.227V

1
1 DY 2 Reserved 100.0K 100.0K 1.65V 100KR2F-L1-GP Reserved 100.0K 226K(64.22635.6DL) 1.012V

SCD1U16V2KX-3GP
C2408
DYR2444

1
2
Do Not Stuff Do Not Stuff Reserved 100.0K 143.0K 1.358V
DY
Vinafix.com

2
+V1.00U_CPU If don't need RTC alarm wake up,
R2492

Do Not Stuff
can change to 3D3V_AUX_S5 Reserved 100.0K 174.0K 1.204V

C2420

C2412

C2411

C2410

C2414

C2413

C2417

2
1

1
1 DY 2

C2421

C2416

C2415
1

1
DY Reserved 100.0K 215.0K 1.048V EC_AGND
Do Not Stuff DY

SCD1U16V2KX-3GP 2

SCD1U16V2KX-3GP 2

SCD1U16V2KX-3GP 2

SCD1U16V2KX-3GP 2

SCD1U16V2KX-3GP 2

SCD1U16V2KX-3GP 2

Do Not Stuff 2
Layout Note:

SCD1U16V2KX-3GP 2

SCD1U16V2KX-3GP 2

2
EC_AGND

C2423
D D

1
3D3V_AUX_S5 RTC_AUX_S5

Do Not Stuff
Need very close to EC

SCD1U16V2KX-3GP2
2

2
3D3V_S5_KBC

3D3V_AUX_KBC_33
3D3V_S5_KBC DY R2472
R2473 BOARD_ID 1 2 R2494 AC_IN_KBC#
Do Not Stuff
Do Not Stuff (To EC) DY
Do Not Stuff U2401
R2493

1
1AC_IN_KBC#_R
RN2412 ECVBAT BOARD_ID 1 2 R2495 BOARD_ID_C
[43] AC_IN_KBC# 2
DY
Do Not Stuff
1
2
A2 SEL
6
5
ALL_SYS_PWRGD [17,40]

1 8 KSI0 (To EC) DY

Do Not Stuff MODEL_ID_C 3
GND DY VDD
4 MODEL_ID 3D3V_S5_KBC

1
KSI3 3D3V_S5_KBC EC_AGND A1 DA
2 7 (To EC) RN2402
3 6 KSI1 C2428 R2499
4 5 KSI5 3D3V_S5_KBC 1 2 AUX_EN_WOWL Do Not Stuff SMBCLK1 3 2

2
RN2403 SCD1U16V2KX-3GP Do Not Stuff SMBDA1 4 1
1 8 KSO10 R2497

122

103
SRN10KJ-6-GP KSO11 MODEL_ID MODEL_ID_C SRN4K7J-8-GP

43
82

19
65
2 7 1 2

5
RN2411 3 6 KSO14 KBC24 ALL_SYS_PWRGD de-assert, (To EC) Do Not Stuff
1 8 KSI2 4 5 KSO13 R2450 54 PCH_ALW_ON R2496 1 DS3 2 Do Not Stuff

VBAT

VTR
VTR
VTR
VTR
VTR
VTR
KSI4 VTR_33_18 delay 100ms; SYS_PWROK assert.
2 7 100KR2J-1-GP [65] KSO[0..16]
3 6 KSI6
4 5 KSI7 SRN100KJ-5-GP KSO0 2 3D3V_S0
1 KSO1 GPIO027/KSO00/PVT_IO1 SMBDA1 3D3V_S5_KBC
RN2404 14 8 SMBDA1 [43,44]
KSO15 KSO9 KSO2 GPIO015/KSO01/PVT_CS# GPIO007/SMB01_DATA/SMB01_DATA18 SMBCLK1
1 8 15 9 SMBCLK1 [43,44]
SRN10KJ-6-GP KSO16 KSO3 GPIO016/KSO02/PVT_SCLK GPIO010/SMB01_CLK/SMB01_CLK18 SMBDA2
2 7 16 11

2
KSO12 KSO4 GPIO017/KSO03/PVT_IO0 GPIO012/SMB02_DATA/SMB02_DATA18 SMBCLK2
RN2410 3 6 37 12
2

KSO6 KSO0 KSO5 GPIO045/BCM_INT1#/KSO04 GPIO013/SMB02_CLK/SMB02_CLK18 SYS_PWROK R2430 PBAT_PRES# R2415 1

1 8 4 5 38 89 SYS_PWROK [17] 2 10KR2J-3-GP
KSO7 R2449 KSO6 GPIO046/BCM_DAT1/KSO05 GPIO130/SMB03_DATA/SMB03_DATA18 L_BKLT_EN_EC
2 7 39 91 10KR2J-3-GP
GPIO047/BCM_CLK1/KSO06 GPIO131/SMB03_CLK/SMB03_CLK18 R2411 1
3 6 KSO4 DY Do Not Stuff KSO7 50 96 SIO_SLP_SUS# [17,40,53,54] SIO_EXT_SCI# 2 Do Not Stuff SIO_EXT_SCI#_R [16]
KSO5 SRN100KJ-5-GP KSO8 GPIO025/KSO07/PVT_IO2 GPIO141/SMB04_DATA/SMB04_DATA18 PBAT_PRES# D2403
4 5 46 97 PBAT_PRES# [43,44]

1
KSO9 GPIO055/PWM2/KSO08/PVT_IO3 GPIO142/SMB04_CLK/SMB04_CLK18 SIO_EXT_SMI# R2412 1
68 2 Do Not Stuff SIO_EXT_SMI#_R [8]
1

KSO10 GPIO102/KSO09/CR_STRAP FAN1_TACH

72 40 A K FAN_TACH1 [26]
SRN100KJ-5-GP KSO11 GPIO106/KSO10 GPIO050/TACH0 R2457 1
74 41 DY 2 Do Not Stuff
RN2409 EC2401 2 DY1 DGPU_PWROK KSO12 75
GPIO110/KSO11 MEC1404 GPIO051/TACH1 LID_CL_SIO# [64] USB_OC3# [16]
KSO2 KSO13 GPIO111/KSO12
1 8 76
GPIO112/PS2_CLK1A/KSO13 GPIO053/PWM0
44 BKLGT_PWM [65] 83.R2004.G8F RB751V-40H-GP 3D3V_S5
2 7 KSO1 Do Not Stuff KSO14 77 45 BEEP [27]
KSO3 R2510 CLKRUN# KSO15 GPIO113/PS2_DAT1A/KSO14 GPIO054/PWM1 R2427
3 6
KSO8
2 DY 1
Do Not Stuff KSO16
86
GPIO125/KSO15 DGPU_PWROK_KBC
4 5 92
GPIO132/KSO16 GPIO056/PWM3
47 1 OPS 2 DGPU_PWROK [19,82,83]

2
CAP_LED# 93 34 0R2J-2-GP SUSACK# [17]
C2402 PCH_PLTRST#_EC GPIO140/KSO17 GPIO030/BCM_INT0#/PWM4 R2484
SRN100KJ-5-GP
1 DY2 [65] KSI[0..7]
KSI0 GPIO031/BCM_DAT0/PWM5
35 EC_WAKE# [17]
98 36 PS_ID [43] 100KR2J-1-GP
Do Not Stuff KSI1 GPIO143/KSI0/DTR# GPIO032/BCM_CLK0/PWM6 PWR_LED#
99 4 Q2412
KSI2 GPIO144/KSI1/DCD# GPIO002/PWM7
6

1
KSI3 GPIO005/SMB00_DATA/SMB00_DATA18/KSI2 BAT1_LED# BAT1_LED#
7 1 S
KSI4 GPIO006/SMB00_CLK/SMB00_CLK18/KSI3 GPIO157/LED0/TST_CLK_OUT BAT2_LED#
104 106
KSI5 GPIO147/KSI4/DSR# GPIO156/LED1 3D3V_AUX_S5
105 70 SIO_SLP_S3# [17,27,40,51,52,54] D BATT_WHITE_LED# [64]
KSI6 GPIO150/KSI5/RI# GPIO104/LED2
107
KSI7 GPIO151/KSI6/RTS# 2N7002K-2-GP
108 80 ME_FWP_EC [19,98] 3D3V_S5 G
GPIO152/KSI7/CTS# GPIO116/TFDP_DATA/UART_RX

1
GPIO117/TFDP_CLK/UART_TX
81 HOST_DEBUG_TX [61] 84.2N702.J31
78 R2467
[65] CLK_TP_SIO GPIO114/PS2_CLK0 PTP_DIS# 1KR2J-1-GP 3D3V_S5 2ND = 84.2N702.031
[65] DAT_TP_SIO 79 90
GPIO115/PS2_DAT0 GPIO035/SB-TSI_CLK PECI_EC 3rd = 84.07002.I31
[17,99] SIO_PWRBTN# 52 94 1 2 H_PECI [4]
GPIO026/PS2_CLK1B GPIO033/PECI_DAT/SB_TSI_DAT

Do Not Stuff
[17] PCH_RSMRST# 88 R2437 4th = 84.2N702.W31

2
GPIO127/PS2_DAT1B

2
C2405
95 EC_VTT 43R2J-GP ECVBAT +3VLP
[18,68] LPC_LAD[3..0]

1
C
LPC_LAD0 VREF_CPU R2488 C
59 Need very close to EC

1
LPC_LAD1 GPIO040/LAD0 ICSP_CLOCK
LPC_LAD2
60
GPIO041/LAD1 GPIO145/ICSP_CLOCK
101
ICSP_DATA
DY R2454
100KR2J-1-GP
61 102 Q2413

2
LPC_LAD3 GPIO042/LAD2 GPIO146/ICSP_DATA ICSP_CLR 100KR2J-1-GP
62 87

1
GPIO043/LAD3 ICSP_MCLR BAT2_LED#
[18,68] LPC_LFRAME# 58 S
R2410 1 PCH_PLTRST#_EC GPIO044/LFRAME# EC_MUTE# R2452
[17,31,40,55,61,68,73,91] PLT_RST# 2 56 119 EC_MUTE# [27]

2
Do Not Stuff GPIO064/LRESET# BGPO/GPIO004 +3VLP 100KR2J-1-GP
[18] CLK_PCI_LPC_MEC 57 120 D CHG_AMBER_LED# [64]
GPIO034/PCI_CLK SYSPWR_PRES/GPIO003 ALWON
[18] CLKRUN# 63 121 ALWON [40]

1
GPIO067/CLKRUN# VCI_OUT/GPIO036 VCI_IN1# 3D3V_S5_KBC
[18] SERIRQ 55 126 3D3V_S5 G
SIO_EXT_SMI# GPIO063/SER_IRQ VCI_IN1#/GPIO162 POWER_SW_IN# 2N7002K-2-GP
10 127
TP_EN# GPIO011/SMI#/EMI_INT# VCI_IN0#/GPIO163 ACAV_IN
[65] TP_EN# 49 128 2 R2469 1 PWR_CHG_ACOK [17,44] 84.2N702.J31
GPIO060/KBRST VCI_OVRD_IN/GPIO164 Do Not Stuff
[18] SIO_RCIN# 53 2ND = 84.2N702.031

2
SIO_EXT_SCI# GPIO061/LPCPD#
66 23 MASK_BASE_LEDS# [64]
GPIO100/EC_SCI# GPIO160/DAC_0 R2424 3D3V_S5 3rd = 84.07002.I31
24 FAN1_DAC_1 [26]
GPIO161/DAC_1
[18,25,91] SPI_CLK_ROM
R2485 1 2 10R2F-L-GP EC_SPI_CLK 32
GPIO126/SHD_SCLK DAC_VREF
22 3D3V_S5_KBC 20KR2F-L-GP Vref = 1.117 4th = 84.2N702.W31
R2486 1 2 10R2F-L-GP EC_SPI_MOSI 28 C2429 1 2 temp around 85
[18,25,91] SPI_SI_ROM

2
R2487 GPIO133/SHD_IO0
[18,25,91] SPI_SO_ROM 1 2 10R2F-L-GP EC_SPI_MISO 29 85 CMP_VOUT0 SCD1U16V2KX-3GP CMP_VOUT0 [26]

1
GPIO134/SHD_IO1 GPIO124/CMP_VOUT0 CMP_VIN0
[64] LED_SATA_DIAG_OUT# 30 20 2 R2470 1 CMP_VIN0_R [26] R2489
GPIO135/SHD_IO2 GPIO020/CMP_VIN0 VCREF0 Do Not Stuff
[18] RTCRST_ON 31 25 100KR2J-1-GP
GPIO136/SHD_IO3 GPIO165/CMP_VREF0
[18,25] SPI_CS_ROM_N0 1 R2490 2 EC_SPI_CS0# 27
Do Not Stuff GPIO123/SHD_CS# CMP_VOUT1
83
Layout Note:

1
GPIO120/CMP_VOUT1 CAP_LED#
[17,40,51] SIO_SLP_S4# 67 21 OVER_CURRENT_P8# [76] S

1
GPIO101/SPI_CLK GPIO021/CMP_VIN1 LCD_TST
Need very close to EC [43] AC_DIS 69 26

1
GPIO103/SPI_IO0 GPIO166/CMP_VREF1/UART_CLK R2448 C2409
[41] PCH_ALW_ON 71 D CAP_LED#_S [65]
GPIO105/SPI_IO1 CMP_STRAP0 10KR2F-2-GP SCD01U50V2KX-1GP
[17] ME_SUS_PWR_ACK 42 118
GPIO052/SPI_IO2 GPIO024/CMP_STRAP0
[4,65] INT_TP# 1 R2431 2 Do Not Stuff PTP_INT#_EC 33 117 PANEL_BKEN_EC [55] 3D3V_S5 G

2
GPIO062/SPI_IO3 GPIO023/ADC6/A20M
[31] PM_LAN_ENABLE 2 R2491 1 Do Not Stuff LAN_EN 3 116 SIO_EXT_WAKE# [20] 2N7002K-2-GP

2
R2401 2 GPIO001/SPI_CS#/32KHZ_OUT GPIO022/ADC5 Q2414
1 Do Not Stuff 109 MODEL_ID R2421 84.2N702.J31
[31] AUX_EN_WOWL DY USB_EN# 13
GPIO153/ADC4
110 I_ADP 2 1 AD_IA [44]
3D3V_S5 2ND = 84.2N702.031
R2481 1 Do Not Stuff RUNPWROK RESET_IN#/GPIO014 GPIO154/ADC3 BOARD_ID
[17,40] ALL_SYS_PWRGD 2 48 111 3rd = 84.07002.I31
VSS_VBAT

GPIO057/VCC_PWRGD GPIO155/ADC2 I_SYS 330R2J-3-GP

[17,26,40] RESET_OUT# 73 113 4th = 84.2N702.W31

2
GPIO107/RESET_OUT# VR_CAP GPIO122/ADC1

SC2200P50V2KX-2GP
114 I_BATT Need very close to EC

1
GPIO121/ADC0
AVSS

R2422 R2428 2 DY 1 Do Not Stuff XTAL2 125 115 R2498

C2435
VSS
VSS
VSS
VSS
VSS

[18] SUS_CLK XTAL2 ADC_VREF 3D3V_S5_KBC

I_SYS 2 1 P_SYS [44,46] XTAL1 123 100KR2J-1-GP
XTAL1
ALL_SYS_PWRGD assert,

2
330R2J-3-GP MEC1404-NU-GP 3D3V_S5
delay 10ms; RESET_OUT# assert.
124

84
51
17
64
100

112

18

1
2
SC2200P50V2KX-2GP

PWR_LED# S
1

071.01404.000E C2422
C2427

1
SCD1U16V2KX-3GP
R2458 EC_AGND D PWR_LED#_S [64]
EC_AGND

Do Not Stuff R2434

VR_CAP
2

100KR2J-1-GP 3D3V_S5 G
1

2
2N7002K-2-GP
R2479 Q2416 84.2N702.J31

2
USB_EN# 1 2 3D3V_S5 2ND = 84.2N702.031
USB_PWR_EN# [35]
EC_AGND Do Not Stuff 3rd = 84.07002.I31
X2401 XTAL_KBC_2 4th = 84.2N702.W31
1

R2423 C2418 LID_CL_SIO# R2433 1 2 100KR2J-1-GP

I_BATT 2 1 boost_mon [44] 1 2 EC_AGND
SC1U10V2KX-1GP MASK_BASE_LEDS# R2438 1 2 10KR2J-3-GP
2

330R2J-3-GP L_BKLT_EN_EC 2 R2435 1 L_BKLT_EN [8]

SC2200P50V2KX-2GP

XTAL-32D768KHZ-83-GP Do Not Stuff TP_EN# R2409 1 2 100KR2J-1-GP

C2441

1
082.30003.0131 eDP backlight Control from PCH
R2436 3D3V_S0
100KR2J-1-GP
2

C2425 C2424 D2402

B SC10P50V2JN-4GP SC10P50V2JN-4GP TOUCH_PANEL_INTR# R2429 1 2 Do Not Stuff B
Layout Note: DY

2
1 R2445 2 LID_CL_SIO# K A TOUCH_PANEL_INTR# [4,55]
1

Need very close to EC Do Not Stuff Touch Panel PH internally.

EC_AGND 1 R2419 2 3D3V_S5_KBC
LCD_TST_EN [55]
Do Not Stuff RB751V-40H-GP 83.R2004.G8F
CMP_STRAP0 R2420 1 2 10KR2J-3-GP
Layout Note: LCD_TST LCD_TST [55]
'CMP_STRAP0' pull high to enable D2405
EC_AGND Connect GND and AGND planes via either
Microchip: Use CL=9p Xtal，C = 10p Comparator function 11/24 PTP_DIS#
0R resistor or connect directly. K A TP_LOCK# [65]
Power Switch Logic(PSL) ECVBAT
RB751V-40H-GP 83.R2004.G8F
2

R2451
100KR2J-1-GP
R2432
1

[64] KBC_PWRBTN# 1 2 POWER_SW_IN#

C2426
1

1KR2J-1-GP
SC1U10V2KX-1GP
R2482
2

SMBDA2 1 2 SML1_SMBDATA
Do Not Stuff

R2483
SMBCLK2 1 2 SML1_SMBCLK
Do Not Stuff

3D3V_S5_KBC 3D3V_S5_KBC 3D3V_S5_PCH

EC_GPIO47 High Active
3D3V_S5_KBC

2
1
3D3V_S5_KBC
R2418 R2478 RN2603
Do Not Stuff Do Not Stuff
1 DY 2 DB3 DS3Do Not Stuff
2

7
2

DB3 R2476 2 DB3 1 Do Not Stuff 3D3V_AUX_KBC_R 1 Do Not Stuff

3
4
Do Not Stuff

Q2408
R2414

CMP_VOUT1 G DY ICSP_CLOCK R2463 2 DB3 1 Do Not Stuff ICSP_CLK_R 2 SMBDA2 6 1 SML1_SMBDATA [18,26,76]
ICSP_DATA R2464 2 DB3 1 Do Not Stuff ICSP_DATA_R 3 DB3
1

H_PROCHOT#_EC 1 R2416 2 Do Not Stuff

D H_PROCHOT# [4,43,44,46] 4 5
DS3 2
1
1

Do Not Stuff HOST_DEBUG_TX R2466 2 DB3 1 Do Not Stuff E51_TXD_R 5 2nd = 84.2N702.E3F
R2417 S ICSP_CLR R2465 2 DB3 1 Do Not Stuff ICSP_CLR_R 6 3rd = 75.00601.07C 4 3
1

Do Not Stuff DY C2403 8 4th = 84.DMN66.03F

2N7002K-2-GP DY Do Not Stuff Q2604
84.2N702.J31 Do Not Stuff
2

A 2ND = 84.2N702.031 SMBCLK2 A

3rd = 84.07002.I31 Do Not Stuff
4th = 84.2N702.W31
SML1_SMBCLK [18,26,76]

Reserved for DS3 circuit

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
KBC SMSC 1404
Size Document Number Rev
Custom
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 24 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = SPI Flash

SPI Flash ROM(16M) for PCH 3D3V_S5_PCH 3D3V_S5_PCH

3D3V_S5_PCH
Vinafix.com
SKT25

1
D C2501 D
SPI_CS_ROM_N0 1 8 Do Not Stuff C2502
DY

4
3
SPI_SO_ROM_R 2 7 SPI_HOLD_ROM_R
DY SCD1U16V2KX-3GP

2
SPI_W P_ROM_R 3 6 SPI_CLK_ROM_R R2501 RN2501
4 5 SPI_SI_ROM_R 4K7R2J-2-GP
DY Do Not Stuff

Do Not Stuff

1
Do Not Stuff

1
2
SPI25 3D3V_S5_PCH

[18,24] SPI_CS_ROM_N0 1 CS# VCC 8

[18,24,91] SPI_SO_ROM R2507 1 2 10R2F-L-GP SPI_SO_ROM_R 2 7 SPI_HOLD_ROM_R R2503 1 2 10R2F-L-GP
DO/IO1 HOLD#/RESET#/IO3 SPI_HOLD_ROM [18]
R2508 1 2 10R2F-L-GP SPI_W P_ROM_R 3 6 SPI_CLK_ROM_R R2505 1 2 10R2F-L-GP SPI_CLK_ROM [18,24,91]
[18] SPI_W P_ROM WP#/IO2 CLK
4 5 SPI_SI_ROM_R R2506 1 2 10R2F-L-GP SPI_SI_ROM [18,24,91]
GND DI/IO0

1
W 25Q128FVSIG-GP
EC2502 DY EC2501 DY DY EC2503
Do Not Stuff Do Not Stuff Do Not Stuff
72.25128.0A1

2
SPI Flash ROM(8M) for PCH 3D3V_S5_PCH 3D3V_S5_PCH

C C

3D3V_S5_PCH
SKT26

1
C2505
SPI_CS_ROM_N1 1 8 Do Not Stuff DY DY C2504
2

4
3
SPI1_SO_ROM_R 2 7 SPI1_HOLD_ROM_R
DY Do Not Stuff

2
SPI1_W P_ROM_R 3 6 SPI1_CLK_ROM_R R2515 RN2502
4 5 SPI1_SI_ROM_R Do Not Stuff DY
DY Do Not Stuff

Do Not Stuff
1

Do Not Stuff
1
2

SPI252 3D3V_S5_PCH

[18] SPI_CS_ROM_N1 1 CS# VCC 8

[18,24,91] SPI_SO_ROM R2513 1 DY 2 Do Not Stuff SPI1_SO_ROM_R 2 7 SPI1_HOLD_ROM_R R2509 1 DY 2 Do Not Stuff
DO/IO1 HOLD#/IO3 SPI_HOLD_ROM [18]
R2514 1 DY 2 Do Not Stuff SPI1_W P_ROM_R 3 6 SPI1_CLK_ROM_R R2511 1 DY 2 Do Not Stuff SPI_CLK_ROM [18,24,91]
[18] SPI_W P_ROM WP#/IO2 CLK
4 5 SPI1_SI_ROM_R R2512 1 DY 2 Do Not Stuff
GND DY DI/IO0 SPI_SI_ROM [18,24,91]
1

1
Do Not Stuff
EC2504 DY Do Not Stuff EC2506 DY DY EC2505
Do Not Stuff Do Not Stuff Do Not Stuff
2

2
B B

Main Func = RTC

+RTC_VCC 3D3V_AUX_S5 RTC_AUX_S5

AFTP2502 1 +RTC_VCC
D2501
1

RTC1 R2502 3
3 1KR2J-1-GP
1 2 1 RTC_PW R 2
1

2 C2503
4
BAS40C-2-GP DY Do Not Stuff
2

75.00040.07D
ACES-CON2-11-GP-U
AFTP2501
2nd = 75.00040.C7D
1
20.F0772.002 3rd = 75.00040.A7D

Q2505
A G <Core Design> A
1

D RTC_DET# [20]
R2504
10MR2J-L-GP S Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2N7002K-2-GP Taipei Hsien 221, Taiwan, R.O.C.
2

84.2N702.J31
2ND = 84.2N702.031 Title
3rd = 84.07002.I31
4th = 84.2N702.W31 Flash/RTC
Size Document Number Rev
A3 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 25 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Thermal Sensor Fan controller1

3D3V_S0 3D3V_S0 5V_S0
R2605 FAN261
Do Not Stuff
1 DY 2 FON# 1 8

SC4D7U6D3V3KX-GP
FON# GND

C2611
5V_S0 2 VIN GND 7

1
2
FAN_VCC1 3 6

SCD1U16V2KX-3GP
VOUT GND

1
C2605
RN2602 4 5
Vinafix.com T8 Do Not Stuff
[24] FAN1_DAC_1 VSET GND

2
AP2113MTR-G1-GP
D
3D3V_S0 Do Not Stuff D

4
3
6 1 THM_SML1_DATA 74.02113.0E1
[18,24,76] SML1_SMBDATA Layout Note:

C2601
Do Not Stuff 5 2 Need 10 mil trace width.

Do Not Stuff
2nd = 84.2N702.E3F T8
1

1
3rd = 75.00601.07C 4 3
DY T8 C2602 4th = 84.DMN66.03F
Do Not Stuff Q2601
2

2
THM_SML1_CLK 6

FAN_VCC1 4
[18,24,76] SML1_SMBCLK 3

C2603
D2601 FAN_TACH1_C 2

SC2200P50V2KX-2GP
K
1

1
Do Not Stuff
Do Not Stuff C2604 1
Layout Note: Do Not Stuff DY DY
NCT7718_DXP Signal Routing Guideline: 5

2
Q2603 THM26 Trace width = 15mil

A
Do Not Stuff

R2606 FAN1
C

1 8 THM_SML1_CLK ACES-CON4-17-GP-U1
VDD SCL

Do Not Stuff
T8 B DY C2606 T8 C2607 2 7 THM_SML1_DATA Do Not Stuff
Do Not Stuff Do Not Stuff 3
D+ SDA
T8 ALERT# 6 NCT7718_ALERT# 1 20.F1621.004
2

1
T_CRIT# D-
4 5
E

T_CRIT# GND

1
Do Not Stuff

Do Not Stuff
C2608

C2609
NCT7718_DXN
DY DY [24] FAN_TACH1 AFTP2803
2.System Sensor, Put on palm rest Do Not Stuff

2
Do Not Stuff
C C
1

FAN_TACH1
R2601
DY Do Not Stuff FAN_VCC1
Q2602
Layout Note: [17,24,40] RESET_OUT# G EC2602 EC2601
2

1
C2812 close U2801 DY AFTP2802 1FAN_TACH1_C
D AFTP2801 1FAN_VCC1

SC10P50V2JN-4GP

Do Not Stuff
PURE_HW _SHUTDOW N# [40,76]

2
THERM_SYS_SHDN# S

Do Not Stuff
C2610
1 DY 2 CMP_VOUT0
Layout Note: 2N7002K-2-GP
DY R2612 Do Not Stuff
Both DXN and DXP routing 10 mil trace width and 10 mil spacing. 84.2N702.J31

2
2ND = 84.2N702.031
3rd = 84.07002.I31 need to check with NTD team Barkley 1404 test result
4th = 84.2N702.W31
3D3V_S0

R2603 1 T8 2 Do Not Stuff NCT7718_ALERT#

R2604 2 Do Not Stuff T_CRIT# 3D3V_S5_KBC

1 T8
R2607 1 2
10KR2J-3-GP
R2602
THERM_SYS_SHDN# 1 2 CMP_VOUT0 [24]
B Do Not Stuff B

Close to KBC
Close to Thermal sensor VD_IN1 for system thermal sensor
3D3V_AUX_S5 3D3V_S5_KBC
1

1
Do Not Stuff
R2609

DY R2608
25K5R2F-GP
2

CMP_VIN0_R [24]
1

C2612
1

1
R2610 SCD1U16V2KX-3GP
NTC-100K-8-GP C2613
2

2
SC100P50V2JN-3GP
2

VD_IN1_C 1 R2611 2
Do Not Stuff
A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

THERMAL NCT7718W/Fan
Size Document Number Rev
A3
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 26 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Audio

Audio Codec Chip (ALC3234 & ALC3246 co-lay)

1 R2731 2
Do Not Stuff
+3V_AVDD
Vinafix.com [29] LINE1_VREFO_R MIC2_VREFO [29]
D D
3D3V_S0 25mA [29] LINE1_VREFO_L AUD_AGND
moat
R2725 Reserved for ALC3234
1 3234 2 ALC3234 and ALC3246

SC2D2U10V3KX-1GP

SC4D7U6D3V3KX-GP
Do Not Stuff [29] AUD_HP1_JACK_L
1D8V_S0 CPVDD EC2707 Do Not Stuff
1 2 DY

1
[29] AUD_HP1_JACK_R EC2706 SC1KP50V2KX-1GP
1 2

1 C2705
1 R2726 2 R2711 EC2705 1 2 SCD1U25V2KX-GP
Do Not Stuff EC2704 DY Do Not Stuff
100KR2J-1-GP moat 1 2

C2702
C2714 C2704 EC2703 1 2 SCD1U25V2KX-GP

1
1 2

SCD1U16V2KX-3GP

2
1
C2701
SC4D7U6D3V3KX-GP SC1U10V2KX-1GP +5V_AVDD 5V_S0

2
Close pin36 AUD_AGND

2
1
C2703 CPVDD 1 R2703

AUD_VREF
2

LDO1_CAP
1.5A +5V_AVDD

CPVEE
SC1U10V2KX-1GP Do Not Stuff

CBN
5V_S0 +5V_PVDD C2710
AUD_AGND

1
C2711 1 R2706 2
Do Not Stuff
Layout Note:

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP
1 R2702 2 1 R2727 2

2
Place close to Pin 26 Do Not Stuff

36

35

34

33

32

31

30

29

28

27

26

25
C2706 C2707 C2708 C2709 HDA27 1 R2730 2
1

1
Do Not Stuff Do Not Stuff
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

CPVEE

HPOUT-L_PORT-I-L

LINE1-VREFO-L

MIC2-VREFO

LDO1-CAP

AVDD1

AVSS1
CPVDD

CBN

HPOUT-R_PORT-I-R

LINE1-VREFO-R

VREF
1 R2704 2
2

2
Do Not Stuff CBP 37 24 AUD_AGND AUD_AGND Layout Note:
CBP LINE2-L_PORT-E-L
Tied at point only under
AUD_AGND 38 23 moat Codec or near the Codec
AVSS2 LINE2-R_PORT-E-R
C2712 1 2 SC10U6D3V3MX-GP LDO2_CAP 39 22
AUD_AGND LDO2-CAP LINE1-L_PORT-C-L LINE1_L [29] 3D3V_S5

Layout Note: Layout Note: +3V_1D5V_AVDD 40

AVDD2 LINE1-R_PORT-C-R
21
LINE1_R [29]
Close pin41 Close pin46 41 20 V3D3_STB R2712 1 2 Do Not Stuff
+5V_PVDD PVDD1 VD33STB
moat AUD_SPK_L+ 42 19 MIC_CAP C2713 1 2 SC10U6D3V3MX-GP Width>40mil, to improve Headpohone Crosstalk noise
[29] AUD_SPK_L+ SPK-OUT-L+ MIC2-CAP AUD_AGND
1D8V_S0 Layout Note: AUD_SPK_L- 43 18
Change it to sharp will be better.
+3V_1D5V_AVDD Speaker trace width >40mil @ 2W4ohm speaker power [29] AUD_SPK_L- SPK-OUT-L-
071.03246.0003
MIC2-R_PORT-F-R/SLEEVE SLEEVE [29] Layout Note: Add 2 vias (>0.5A) when trace layer change.
C AUD_SPK_R- 44 17 C
[29] AUD_SPK_R- SPK-OUT-R- MIC2-L_PORT-F-L/RING2 RING2 [29]
3D3V_S0 1D5V_S0 R2713 1 2
[29] AUD_SPK_R+
AUD_SPK_R+ 45
SPK-OUT-R+
(71.03234.003)
PCBEEP
16 AUD_PC_BEEP_3246 1 R2723 2 AUD_PC_BEEP_R moat
Do Not Stuff Do Not Stuff
R2705 1 JDREF R2707 1 2 Do Not Stuff
3234 2
Do Not Stuff R2708
+5V_PVDD 46
PVDD2 SPDIFO/FRONT-JD_JD3/GPIO3
15 DY AUD_AGND
1

R2710 1DY 2 Do Not Stuff 1 2 PD# 47 14

C2715 C2721 [24] EC_MUTE# PDB MIC2/LINE2-JD_JD2
Do Not Stuff 48 13 AUD_SENSE_A 1 2 AUD_SENSE
SCD1U16V2KX-3GP
SC4D7U6D3V3KX-GP

+3V_AVDD
2

SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN HP/LINE1-JD_JD1 AUD_SENSE [29]

AVDD2: R2709

GPIO0/DMIC-DATA12
R2724 49 200KR2F-L-GP R2722
+1.8VD@3246
Close pin40 1 2
TP2702 GND Layout Note:
+1.5VD@3234 +3V_AVDD DY AUD_SENSE_A

GPIO1/DMIC-CLK
1 COMBO-GPI Place close to Pin 13 2 1
AUD_AGND Do Not Stuff

SDATA-OUT
Do Not Stuff moat 100KR2J-1-GP

LDO3-CAP

SDATA-IN

I2C-DATA
DVDD-IO
DC_DET

I2C-CLK
+3.3VD@3234

DVDD

SYNC
BCLK
follow Pin1 Power setting@3246

Azalia I/F EMI

ALC3246-CG-GP-U

10

11

12
+3V_AVDD +3V_AVDD

1 DVSS
HDA_CODEC_SDOUT AUD_PC_BEEP R2715 1 3234 2AUD_PC_BEEP_R

LDO3_CAP

RESETB@3234
Do Not Stuff

PCBEEP@3234
HDA_CODEC_BITCLK Do Not Stuff

DMIC_DATA_R

C2718

C2719
EC2708 EC2709 C2717
1

1
EC2701
SC10P50V2JN-4GP

R2732
C2716
SC4D7U6D3V3KX-GP DY

SCD1U16V2KX-3GP
1

1
SC22P50V2JN-4GP

SC22P50V2JN-4GP
2

HDA_CODEC_RST#_R
2

2
SCD1U16V2KX-3GP
SC4D7U6D3V3KX-GP
D2701
RN2701 HDA_SPKR_R 2
[19] SPKR 2 3 C2720
1 4 3 AUD_PC_BEEP_C 1 2AUD_PC_BEEP_R
[24] BEEP
22R2J-2-GP1 R2714 2 DMIC_DATA_R
[55] DMIC_DATA SRN0J-6-GP KBC_BEEP_R SCD1U16V2KX-3GP
1
22R2J-2-GP1 R2716 2 DMIC_CLK_R

1
B [55] DMIC_CLK B
BAT54C-7-F-3-GP

Do Not Stuff
3234
CODEC_SDOUT_R

R2721
Do Not Stuff 1 R2719 2 R2717
2

[19] HDA_CODEC_SDOUT 1KR2J-1-GP

C2723 22R2J-2-GP1 R2720 CODEC_BITCLK_R
75.00054.E7D
2
[19] HDA_CODEC_BITCLK
SC22P50V2JN-4GP 2nd = 83.R2003.W81
1

2
22R2J-2-GP1 R2718 2 HDA_CODEC_SDIN0
[19] HDA_SDIN0
HDA_CODEC_SYNC
3rd = 75.00054.A7D
Close pin3 [19] HDA_CODEC_SYNC
4th = 83.R2003.V81
HDA_CODEC_RST#
[19] HDA_CODEC_RST#

1D8V_S5 1D8V_S0
Q4008
DMP2130L-7-GP
150mA 3246
S
D

D
1

G
3246C4029
1

1
R2729 3246 R4046 C4030

Do Not Stuff
1 2 10KR2J-3-GP 3246 C4028 DY
3D3V_S0 DY
SCD1U16V2KX-3GP
2

SCD22U10V2KX-1GP
2

2
Q4009_G

Do Not Stuff R4047

2

1D8V_EN_R#
1 3246 2

4K7R2J-2-GP 84.02130.031
1D8V_EN#

Q4009
[17,24,40,51,52,54] SIO_SLP_S3# 1 R2728 2 G 3246 2nd = 84.00102.031
Do Not Stuff
D 3rd = 84.03413.B31
A A
S

2N7002K-2-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Audio Codec ALC3234

Size Document Number Rev
A2
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 27 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 28 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Audio

Layout Note: Speaker

Speaker trace width >40mil @ 2W4ohm speaker power
Vinafix.com SPK1
5
PBY160808T-121Y-GP 2 L2904 1 AUD_SPK_L+_C 1
[27] AUD_SPK_L+
D D
PBY160808T-121Y-GP 2 L2903 1 AUD_SPK_L-_C 2
[27] AUD_SPK_L- PBY160808T-121Y-GP 2 L2902 AUD_SPK_R+_C
[27] AUD_SPK_R+ 1 3
PBY160808T-121Y-GP 2 L2901 1 AUD_SPK_R-_C 4 CONN Pin Net name
[27] AUD_SPK_R-
6
Pin1 SPK_R+
ACES-CON4-29-GP
Pin2 SPK_R-
20.F1639.004
Pin3 SPK_L+

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
2nd = 20.F1804.004

2
EC2901

EC2902

EC2903

EC2904
Pin4 SPK_L-
3rd = 20.F1352.004

1
AUD_SPK_L-_C 1 AFTP2901
AUD_SPK_L+_C 1 AFTP2902
AUD_SPK_R-_C 1 AFTP2903
AUD_SPK_R+_C 1 AFTP2904

C C

RN2901
[27] MIC2_VREFO 2 3 A00 08/17
1 4

SRN2K2J-1-GP HPMIC1
[27] SLEEVE Do Not Stuff 2 R2906 1 SLEEVE_HPMIC1 3
R2908 1 2 10R2F-L-GP AUD_HP1_JACK_L1 Do Not Stuff 2 R2907 1 AUD_PORTA_L_HPMIC1 1
[27] AUD_HP1_JACK_L C2907 1
[27] LINE1_L 2 LINE1-L_C R2922 1 2 1KR2J-1-GP
SC4D7U6D3V3KX-GP R2912 1 2 4K7R2J-2-GP JACK_PLUG 5
[27] LINE1_VREFO_L JACK_PLUG_DET 6
Shift Issue
R2910 1 2 10R2F-L-GP AUD_HP1_JACK_R1 Do Not Stuff 2 R2909 1 AUD_PORTA_R_HPMIC1 2
[27] AUD_HP1_JACK_R C2908 1
[27] LINE1_R 2 LINE1-L_R R2921 1 2 1KR2J-1-GP Do Not Stuff 2 R2911 1 RING2_HPMIC1 4
SC4D7U6D3V3KX-GP R2913 1 2 4K7R2J-2-GP MS
[27] LINE1_VREFO_R

SC100P50V2JN-3GP
EC2908

SC100P50V2JN-3GP
EC2907

SC100P50V2JN-3GP

EC2906

SC100P50V2JN-3GP

EC2905
Audio(IP/NK comb)

1
Do Not Stuff
R2920

Do Not Stuff
R2919
[27] RING2 PAD-AUDIO-JK509-GP-U-1

1
DY AUD_AGND ZZ.00PAD.IB1

2
DY HPMIC1
2

2
Layout Note: Main Source : 022.10002.0981
Width>40mil, to improve Headpohone Crosstalk noise 2nd : 022.10002.00D1
Change it to sharp will be better. 3rd : 022.10002.00P1
Add 2 vias (>0.5A) when trace layer change.
B B

AUD_AGND AUD_AGND

JACK_PLUG 10 mils 1 R2923 2 10 mils

Do Not Stuff AUD_SENSE [27]
AUD_PORTA_R_HPMIC1
AUD_PORTA_L_HPMIC1
RING2_HPMIC1
JACK_PLUG
JACK_PLUG_DET JACK_PLUG_DET
10 mils SLEEVE_HPMIC1
1

R307
Do Not Stuff
1

1
AZ5125-01H-R7G-GP

ED304

AZ5125-01H-R7G-GP

ED303

AZ5125-01H-R7G-GP

ED306
AZ5125-01H-R7G-GP

ED305
AZ5125-01H-R7G-GP

ED301
AZ5125-01H-R7G-GP

ED302
2

AUD_AGND
moat
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Audio IO
Size Document Number Rev
A3
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 29 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Audio

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)
Size Document Number Rev
A4
Loveland SKL-USheet A00
Date: Tuesday, September 15, 2015 30 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = LAN

Layout: C3114: colse to Pin8 Layout:

R3112 C3109
* Place C3114 to C3117 close to each VDD10 pin--3, 8, 22, 30 C3115 close to Pin30
C3116: close to Pin3 Vinafix.com * Place C3105 and C3106 close to each VDD33 pin-- 11, 32
C3105: close to Pin32 1
2K49R2F-GP
2
PCIE_RX_CON_P6
PCIE_RX_CON_N6
1
1
2 SCD1U16V2KX-3GP
2 SCD1U16V2KX-3GP
PCIE_RX_CPU_P6 [16]
PCIE_RX_CPU_N6 [16]
C3117: close to Pin22 C3111
C3106: close to Pin11 PCIE_TX_CON_P6
D PCIE_TX_CON_P6 [16] D
PCIE_TX_CON_N6
3D3V_LAN_S5 VDDREG PCIE_TX_CON_N6 [16]
REGOUT 1 R3101 2 VDD10
C3002,R3001: Do Not Stuff
Only for PEG_CLK2_CPU [18]
RTL8111 LDO mode. 40 mils 1 R3105 2
PEG_CLK2_CPU# [18]

3D3V_LAN_S5
C3114 C3115 C3116 C3117 Do Not Stuff LED1 1 R3114 2 LOM_CABLE_DETECT# [16]

LANXOUT
1

1
C3102 C3105 C3106 Do Not Stuff

LANXIN
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

VDD10
LED0 1 TP3103 Do Not Stuff

RSET
LED1
2

2
LED2 1 TP3101 Do Not Stuff

32
31
30
29
28
27
26
25
LOM31

AVDD33

AVDD10
CKXTAL2
CKXTAL1
LED0

(LED1) LED2
(GPO) LED1/GPO
RSET
33 GND

3D3V_LAN_S5 C3113 1 2
1 (NC) REGOUT 24 REGOUT SC1U10V2KX-1GP
[32] LAN_MDI0P MDIP0 VDDREG C3118 1
[32] LAN_MDI0N 2 MDIN0 (DVDD33) VDDREG 23 2 SCD1U16V2KX-3GP
C3103 C3104 3D3V_LAN_S5 VDD10 3 22 VDD10 3D3V_S0
AVDD10 (NC) (NC) DVDD10
[32] LAN_MDI1P 4 MDIP1 LANWAKE# 21 PCIE_LAN_W AKE# [17]
1

5 20 ISOLATE# 2 1
[32] LAN_MDI1N MDIN1 ISOLATE# PLT_RST#_LAN R3106
DY [32] LAN_MDI2P 6 MDIP2 (NC) 71.08111.U03 PERST# 19

1
2

1
7 18 PCIE_RX_CON_P6 1KR2J-1-GP
MDIN2 (NC)
2

[32] LAN_MDI2N HSON

SC4D7U6D3V3KX-GP

Do Not Stuff

VDD10 8 17 PCIE_RX_CON_N6 R3107

C RN3101 AVDD10 HSOP 15KR2J-1-GP C
DY

AVDD33 (NC)
Do Not Stuff

MDIP3 (NC)
MDIN3 (NC)

REFCLK_N
REFCLK_P
CLKREQ#

2
Layout:
BQ402_1 4
3

HSIN
HSIP
C3103: close to Pin32 RTL8111G-CGT
C3104: close to Pin11
Do Not Stuff RTL8111G-CGT-1-GP-U2

9
10
11
12
13
14
15
16
71.08111.U03 RTL8111G-CGT (71.08111.U03/LDO Mode): 10/100/1000M < 252 mW.
Q3103 Do Not Stuff
E DY C PLT_RST#_LAN
[17,24,40,55,61,68,73,91] PLT_RST# LDO mode
3D3V_LAN_S5 rise time must be controlled
between 0.5 mS and 100 mS. [32] LAN_MDI3P
10/100/1000M 3D3V_S5
[32] LAN_MDI3N
1 R3108 2
Do Not Stuff 3D3V_LAN_S5 R3113
CLK_LAN_REQ4#_R PCIE_LAN_W AKE#
1 2
PCIE_TX_CON_P6
PCIE_TX_CON_N6 10KR2J-3-GP
PEG_CLK2_CPU
3D3V_S5 3D3V_LAN_S5 PEG_CLK2_CPU#
Q3104
DMP2130L-7-GP 3D3V_LAN_S5
3D3V_LAN_S5
85mA
S
D
D
1

1
G
1

B C3108 R3109 R3102 B

DY
G

10KR2J-3-GP C3110 84.02130.031 C3112 Do Not Stuff

SCD1U16V2KX-3GP
2

1
Do Not Stuff
SC1U10V2KX-1GP
R3110 DY
2

2nd = 84.00102.031 C3107 R3103

2

2
PM_LAN_ENABLE_C LANXOUT DY Do Not Stuff

CLK_LAN_REQ#_EN
1 2 1 2
LAN_ENABLE_R_C

3rd = 84.03413.B31 SC15P50V2JN-2-GP

2
20KR2J-L2-GP

Q3101

3
[24] PM_LAN_ENABLE G
X3101
1

D XTAL-25MHZ-181-GP

B
R3111 Do Not Stuff
100KR2J-1-GP S Q3102 Do Not Stuff
[18] CLKREQ_PCIE#2 C E CLK_LAN_REQ4#_R

2
2N7002K-2-GP 82.30020.G71 DY
2

1 R3104 2
Do Not Stuff

C3101
LANXIN 1 2

SC15P50V2JN-2-GP

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LAN RTL8111
Size Document Number Rev
A3
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 31 of 105

5 4 3 2 1
 5 4 3 2 1

Main Func = LAN

Vinafix.com
D
LAN TransFormer (10/100/1000M) U3201 D

LAN_MDI0P 1 10 LAN_MDI0P
MCT0 LAN_MDI0N LINE_1 NC#10 LAN_MDI0N
2 LINE_2 NC#9 9
MCT1 3 8
XF3103 MCT2 LAN_MDI1P 4
GND DY GND
7 LAN_MDI1P
MCT3 LAN_MDI1N LINE_3 NC#7 LAN_MDI1N
5 LINE_4 NC#6 6
[31] LAN_MDI3N 2 23 MDO3-
1
EC3108 DY2Do Not Stuff 1 24 MCT0 Do Not Stuff

MDO3+
Do Not Stuff
[31] LAN_MDI3P 3 22

4
3
2
1
1
EC3107 DY2Do Not Stuff 1CT:1CT
MDO2- RN3201
2nd = 75.00107.073
[31] LAN_MDI2N 5 20
1
EC3106 DY2Do Not Stuff 4 21 MCT1
SRN75J-1-GP
U3202

[31] LAN_MDI2P 6 19 MDO2+ LAN_MDI2P 1 10 LAN_MDI2P

5
6
7
8
LAN_MDI2N LINE_1 NC#10 LAN_MDI2N
1 2 1CT:1CT 2 9
EC3105 DY Do Not Stuff 8 17 MDO1- 3
LINE_2 NC#9
8
[31] LAN_MDI1N GND DY GND

MCT
1 2 LAN_MDI3P 4 7 LAN_MDI3P
EC3104 DY Do Not Stuff 7 18 MCT2 LAN_MDI3N 5
LINE_3 NC#7
6 LAN_MDI3N
LINE_4 NC#6
[31] LAN_MDI1P 9 16 MDO1+

1
1 Do Not Stuff
[31] LAN_MDI0N EC3103 DY2Do Not Stuff 11
1CT:1CT
14 MDO0- C3201 Do Not Stuff
1 SC100P3KV8JN-2-GP
DY2Do Not Stuff

2
EC3102 10 15 MCT3 2nd = 75.00107.073
78.1013N.1AL
C
[31] LAN_MDI0P 12 13 MDO0+ C
1 2 1CT:1CT
EC3101 Do Not Stuff
DY XFORM-24P-101-GP
068.IH219.3001 RJ45
9 CHASSIS#9 A00 08/17
MDO0+ 1 MDO0+
Layout note:
Layout note: MDO0-
LOM_TCT

2
30 mil spacing between MDI differential pairs. MDO1+ 3
MDO0-
30 mil spacing between MDI differential pairs. MDO2+ 4
MDO1+
MDO2- MDO2+
5
MDO1- 6
MDO2- Shift Issue
MDO3+ MDO1-
7 MDO3+
MDO3- 8 MDO3-
10 CHASSIS#10
RJ45
1

C3119 PAD-RJ45-8P-186-1-GP
SCD01U50V2KX-1GP

ZZ.00PAD.IA1
2

Follow Reference Schematic 0.01uF~0.4uF

RJ45
Main : 022.10001.0D41
2nd : 022.10001.0C41
B B

Layout:
Place near RJ45
Do Not Stuff AFTP3107 1 MDO0+
Do Not Stuff AFTP3102 1 MDO0-
Do Not Stuff AFTP3101 1 MDO1+
Do Not Stuff AFTP3103 1 MDO2+
Do Not Stuff AFTP3104 1 MDO2-
Do Not Stuff AFTP3106 1 MDO1-
Do Not Stuff AFTP3105 1 MDO3+
Do Not Stuff AFTP3108 1 MDO3-

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

XFOM&RJ45
Size Document Number Rev
A3
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 32 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Card Reader

Vinafix.com
D D

14291-SD A00

TR3301
[16] USB_CPU_PN5 1 2 USB_PN5_C [66]

[16] USB_CPU_PP5 4 3 USB_PP5_C [66]

FILTER-4P-137-GP
68.01012.20B

Layout Note:
C Close to CON1 C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
Card Reader-RTS5170
Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 33 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = USB3.0 Port1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 34 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = USB3.0 Port1

Vinafix.com USB3.0 Port1 Layout Note: Close USB1

USB30_VCCC
D
2A D

USB30_VCCC
5V_S5
U3501

C3508
C3507
1

1
5 1 TC3501

SC1U10V2KX-1GP
IN OUT C3512 C3513
GND 2 DY Do Not Stuff
1

4 3 Do Not Stuff

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
[24] USB_PW R_EN# USB_OC0# [16]

2
C3510 EN# OC#

SCD1U16V2KX-3GP
Active Low
SC1U10V2KX-1GP
2

SY6288DAAC-GP
074.06288.009B

Main Func = USB3.0 Port2

USB3.0 Port2
USB30_VCCB USB30_VCCB
C 5V_S5 Layout Note: Close USB2 C
U3502 2A
5 IN OUT 1
GND 2
1

1
[24] USB_PW R_EN# 4 3 USB_OC1# [16] TC3502
C3511 EN# OC# C3509 C3516 C3514 C3519
Active Low DY Do Not Stuff

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
SC1U10V2KX-1GP Do Not Stuff
2

2
SCD1U16V2KX-3GP

SC1U10V2KX-1GP
SY6288DAAC-GP
074.06288.009B

Main Func = USB2.0 Port3

B USB2.0 Port3 (IO Board) B

USB20_VCCA

5V_S5 2A
Support 2A USB20_VCCA Layout Note: Close CON1
U3503

C3517

C3518
SC1U10V2KX-1GP
1

1
5 IN OUT 1
2 C3515 DY
GND
4 3
2

2
Do Not Stuff
[24] USB_PW R_EN# EN# OC# USB_OC2# [16]

SCD1U16V2KX-3GP
Active Low
1

C3504 SY6288DAAC-GP
074.06288.009B
2

SCD1U16V2KX-3GP

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB switch
Size Document Number Rev
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 35 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = USB3.0 Port1

Stuff for ESD R2 spec USB3.0 Port1
U3601

USB3_PRX_CTX_N1_C 1 10 USB3_PRX_CTX_N1_C USB1

USB3_PRX_CTX_P1_C LINE_1 NC#10 USB3_PRX_CTX_P1_C
2 LINE_2 NC#9 9
3 8 1 2 USB_PN0_C
Vinafix.com USB3_PTX_CRX_N1_C
USB3_PTX_CRX_P1_C
4
5
GND
LINE_3
LINE_4
GND
NC#7
NC#6
7
6
USB3_PTX_CRX_N1_C
USB3_PTX_CRX_P1_C
USB30_VCCC VBUS D-
D+ 3 USB_PP0_C

USB3_PRX_CTX_N1_C 5
USB3_PRX_CTX_P1_C STDA_SSRX-
D 6 STDA_SSRX+ GND_DRAIN 7 D
TR3601 AZ1045-04F-R7G-GP
[16] USB_CPU_PN0 1 2 USB_PN0_C 75.01045.073 USB3_PTX_CRX_N1_C 8
USB3_PTX_CRX_P1_C STDA_SSTX-
9 STDA_SSTX+ GND 10
[16] USB_CPU_PP0 4 3 USB_PP0_C 2nd = 75.00107.073 11
GND
12 CHASSIS#12 GND 4
FILTER-4P-137-GP 13 CHASSIS#13 AFTP6217
Stuff for ESD R2 spec 1
68.01012.20B EU3601 SKT-USB13-18-GP-U

USB_PN0_C USB30_VCCC 22.10339.331

1 I/O1 I/O4 6
2nd = 22.10339.S21
2 GND VDD 5
3rd = 22.10339.S31

1
USB_PP0_C 3 4
I/O2 I/O3 C3603
DY 4th = 22.10341.D61
Do Not Stuff

2
AZC099-04S-2-GP
075.09904.0A7C

C3602

1 2 USB3_PTX_CRX_P1_R 2 R3605 1 USB3_PTX_CRX_P1_C [16] USB30_RX_CPU_P1 2 R3607 1 USB3_PRX_CTX_P1_C

[16] USB30_TX_CPU_P1 Do Not Stuff Do Not Stuff
SCD1U16V2KX-3GP

C C
USB30_VCCC 1 AFTP3401
USB_PN0_C 1 AFTP3402
C3601 USB_PP0_C 1 AFTP3403

1 2 USB3_PTX_CRX_N1_R 2 R3606 1 USB3_PTX_CRX_N1_C

[16] USB30_TX_CPU_N1 Do Not Stuff [16] USB30_RX_CPU_N1 2 R3608 1 USB3_PRX_CTX_N1_C
SCD1U16V2KX-3GP Do Not Stuff

Main Func = USB3.0 Port2

Stuff for ESD R2 spec
U3602 USB3.0 Port2
USB3_PRX_CTX_N2_C 1 10 USB3_PRX_CTX_N2_C USB2
USB3_PRX_CTX_P2_C LINE_1 NC#10 USB3_PRX_CTX_P2_C
2 LINE_2 NC#9 9
3 8 USB30_VCCB 1 2 USB_PN1_C
USB3_PTX_CRX_N2_C GND GND USB3_PTX_CRX_N2_C VBUS D- USB_PP1_C
4 LINE_3 NC#7 7 D+ 3
TR3602 USB3_PTX_CRX_P2_C 5 6 USB3_PTX_CRX_P2_C
USB_PN1_C LINE_4 NC#6 USB3_PRX_CTX_N2_C
[16] USB_CPU_PN1 1 2 5 STDA_SSRX-
USB3_PRX_CTX_P2_C 6 7
USB_PP1_C STDA_SSRX+ GND_DRAIN
[16] USB_CPU_PP1 4 3 AZ1045-04F-R7G-GP
B USB3_PTX_CRX_N2_C B
FILTER-4P-137-GP
75.01045.073 USB3_PTX_CRX_P2_C
8 STDA_SSTX-
9 STDA_SSTX+ GND 10
68.01012.20B 2nd = 75.00107.073 GND 11
12 CHASSIS#12 GND 4
13 CHASSIS#13
Stuff for ESD R2 spec 1 AFTP6244

EU3602 SKT-USB13-18-GP-U

USB_PN1_C USB30_VCCB 22.10339.331

1 I/O1 I/O4 6
2nd = 22.10339.S21
2 GND VDD 5
3rd = 22.10339.S31

1
USB_PP1_C 3 4
I/O2 I/O3 C3618
DY 4th = 22.10341.D61
Do Not Stuff

2
AZC099-04S-2-GP

075.09904.0A7C
C3605

1 2 USB3_PTX_CRX_P2_R 2 R3609 1 USB3_PTX_CRX_P2_C [16] USB30_RX_CPU_P2 2 R3611 1 USB3_PRX_CTX_P2_C

[16] USB30_TX_CPU_P2 Do Not Stuff Do Not Stuff USB30_VCCB AFTP3404
1
SCD1U16V2KX-3GP USB_PN1_C 1 AFTP3405
USB_PP1_C 1 AFTP3406

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
C3604
2 R3612 1 USB3_PRX_CTX_N2_C Title
[16] USB30_RX_CPU_N2
1 2 USB3_PTX_CRX_N2_R 2 R3610 1 USB3_PTX_CRX_N2_C Do Not Stuff
[16] USB30_TX_CPU_N2 Do Not Stuff USB30
SCD1U16V2KX-3GP Size Document Number Rev
A3
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 36 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = USB2.0 Port3

Vinafix.com
D D

USB3 (USB2.0) CMC

14291-SD A00

TR3406
[16] USB_CPU_PN2 1 2 USB_PN2_C
USB_PN2_C [66]

[16] USB_CPU_PP2 4 3 USB_PP2_C

USB_PP2_C [66]
FILTER-4P-137-GP
C
68.01012.20B Layout Note: C
Close to CON1

USB ESD Diode

Stuff for ESD R2 spec
EU3404 USB20_VCCA

USB_PP2_C 1 6 USB_PN2_C
I/O1 I/O4
B 2 GND VDD 5 B

3 I/O2 I/O3 4

1
C3406

SCD1U16V2KX-3GP
AZC099-04S-2-GP

2
075.09904.0A7C Layout Note:
Close to CON1

ESD A00

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB20
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 37 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = USB3.0 Port1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 38 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = USB3.0 Port1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 39 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Power Plane & Sequence

Power Good
3D3V_S0

3D3V_AUX_S5

ROSA Run Power

1
PS_S3CNTRL R4005
1 DY 2
1KR2J-1-GP
R4004 [51] 1D35V_VTT_PWRGD 1 R4011 2

Vinafix.com
Do Not Stuff Do Not Stuff

2
D G S
D4002 1 ALL_SYS_PWRGD [17,24]

4
5V_S5
Q4001 5V_S5 5V_S0 RSMRST_PWRGD# 3 Do Not Stuff
D Do Not Stuff
Do Not Stuff
DY
4
U4001

13
5V_S0 DY
2
Do Not Stuff
1 R4002 2
Do Not Stuff
VR_EN [46,52] D

3
2nd = 84.2N702.E3F S G VBIAS OUT1#13
D 14

1
OUT1#14 3V5V_CT1 3D3V_S0
3rd = 75.00601.07C CT1
12 5V_S0 Comsumption

C4005
SC10U10V5KX-2GP
1 3D3V_S5 3D3V_S5_KBC
4th = 84.DMN66.03F 2
IN1#1
8 Peak current 5A

2
IN1#2 OUT2#8
[17,24,27,51,52,54] SIO_SLP_S3# 1 R4010 2 3V5V_S0_ON 3 9 [#543016] Optional, Added for addition system robustness

[17,24,26] RESET_OUT#
Do Not Stuff EN1 OUT2#9
CT2
10 3V5V_CT2
3D3V_S0

1
R4032

C4002
SC470P50V2KX-3GP

C4001
SC470P50V2KX-3GP
3D3V_S5 6 R4031

1
IN2#6 100KR2J-1-GP Do Not Stuff
7
IN2#7 GND
11 3D3V_S0 Comsumption

C4004
SC10U10V5KX-2GP
5
EN2 GND
15
Peak current 2.5A DY

2
NON DS3: PH 3V_5V_POK to 3D3V_AUX_S5 at page17

2
G5016KD1U-GP
R4029 1 2 Do Not Stuff RSMRST_PWRGD#
[53] 1D0V_S5_PWRGD
074.05016.0093 [54] 1D8V_S5_PWROK R4030 1 2 Do Not Stuff

[17,45,53,54] 3V_5V_POK R4033 1 DY 2

Do Not Stuff
H_THERMTRIP# [4]
3D3V_S0

1
Q4002
Do Not Stuff R4020

E
H_THERMTRIP_EN
Do Not Stuff DY Do Not Stuff
VCCSTG_EN
[17] H_THERMTRIP_EN B DY 3D3V_S5

2
R4008 U4003

C
1 DY 2 VCCSTG_EN R4028 1 Do Not Stuff PM_SLP_S0_STG#
DY 2 1 5

VCCSTG_EN_D
R4007 [17] SIO_SLP_S0# A VCC
C4003

1
Do Not Stuff Do Not Stuff R4021 1 2 Do Not Stuff PM_SLP_S3_STG# Do Not Stuff
[17,24,31,55,61,68,73,91] PLT_RST# 1 DY 2
[17,24,27,51,52,54] SIO_SLP_S3#
2
B DY
DY VCCSTG_EN
3 4

2
D4004
1

Do Not Stuff GND Y

1
R4003 RISING TIME2 Do Not Stuff
Do Not Stuff
A DY K
R4019
DY DY
C
Do Not Stuff
VCCIO and VCCSTG Do Not Stuff C
2

1
C4006 1 R4022 2

2
Do Not Stuff DY Do Not Stuff
+VCCIO +VCCSTG

2
D4001 +VCCIO(ICCMAX = 2.73A)
U4002
[45] 3V_5V_EN A K PURE_HW_SHUTDOWN# [26,76] +VCCSTG(ICCMAX.=0.16A)
RISING TIME2 1 8 1 R4048 2 Trise=10US < TR < 65US
VCCSTG_EN VCCSTG_EN_R GATE VOUT#8
1 R4012 2 2 7 Do Not Stuff
1

Do Not Stuff EN VOUT#7

RB751V-40H-GP 3 6
1

C4009 R4006 GND VOUT#6

4 5
VBIAS VOUT#5
20KR2J-L2-GP

SC4D7U6D3V3KX-GP 5V_S5
83.R2004.G8F
VIL > 0.7 V, VIH < 2 V 9 1D0V_S5
2

VIN
Rds(on) = 11 mΩ @ VDD = 4 V VCCSTG should only ramp up equal to or after VCCST.
2

1
SC10U10V5KX-2GP
Ids(max) 10 A

Do Not Stuff
1 R4009 2 ALWON [24] M5938ARD1U-GP-U C4016 C4007

1
C4032 SC10U10V5KX-2GP
074.05938.0093

2
4K7R2J-2-GP DY

2
EOPIO and EDRAM
Need to Check V1.8A
1D8V_S5 +V1.8A

B B

R4037
1 2

C4017 C4021 Do Not Stuff

1
1D8V_S5
Q4003

SC22U6D3V3MX-1-GP

SC1U10V2KX-1GP
Do Not Stuff

2
950mA
S DS3
D

D
1

G
DS3 C4019

1
DS3 R4039 C4020

Do Not Stuff
Do Not Stuff DS3 C4018 DY

Do Not Stuff
Do Not Stuff

MANAGEMENT RAIL POWER GENERATION

2
R4040
VCCST, VCCSTG, and VCCPLL can remain powered during S4 and S5 power states for board VR optimization.

2
1D8A_EN_R#
1 DS3 2

Do Not Stuff

1D8A_EN#
Q4004 Do Not Stuff
3D3V_S5
[17,24,53,54] SIO_SLP_SUS# G DS3 2nd = 84.00102.031
SCD1U16V2KX-3GP

D 3rd = 84.03413.B31
VCCST
1

C4014 C4008
3D3V_S5 Do Not Stuff DY S
1

Do Not Stuff
+V1.00U_CPU_LS
2

+V1.00U_CPU
1

U4006
U4005 R4026
R4025
10KR2J-3-GP RISING TIME 1 8
VCCSTU_EN VCCSTU_EN_R GATE VOUT#8
1 5 1 R4024 2 2 7 1 2
NC#1 VCC Do Not Stuff 3
EN VOUT#7
6
V1.8S
2

GND VOUT#6
[17,24,51] SIO_SLP_S4# 2 4 5
A VBIAS VOUT#5 Do Not Stuff
3 4 VCCSTU_EN R4013 9 1D0V_S5
1

GND Y VCCSTU_EN_R VIN

1
DY 2
VCCSTU_EN_D

EC4001 5V_S5 C4012

1

A 74LVC1G07GW-GP Do Not Stuff M5938ARD1U-GP-U SC10U10V5KX-2GP A

DY
2

73.01G07.0HG C4013
Do Not Stuff

SC10U10V5KX-2GP

074.05938.0093
2

D4005
+VCCSTG +VCCST_CPU
1

R4023 A K RISING TIME VIL > 0.7 V, VIH < 2 V

1 DY 2
DY DY C4031 Rds(on) = 11 mΩ @ VDD = 4 V 0.04 A
Do Not Stuff <Core Design>
Ids(max) 10 A
2

Do Not Stuff
Do Not Stuff

R4045
1 DY 2

Do Not Stuff
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
+V1.00U_CPU
Title

1 R4036 2
Do Not Stuff
Power Plane Enable
Size Document Number Rev
A2
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 40 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Power Plane & Sequence

Vinafix.com
3D3V_S5 3D3V_S5_PCH
D D
1 R4101 2

Do Not Stuff

3D3V_S5
Obs reason:
For new project,
pls help to use cost down version
SY6288C10CAC for instead.
C4102

1
3D3V_S5_PCH

Do Not Stuff
2

DS3 U4101
C C
1 GND OUT#8 8
2 IN#2 OUT#7 7
DS3 3 IN#3 OUT#6 6
[24] PCH_ALW_ON 1 2 DS3_PWRCTL 4 EN DS3 OC# 5
R4102 C4101

1
Do Not Stuff

Do Not Stuff
Do Not Stuff
Do Not Stuff (OBS)

2
DS3
RdsON: 100m ohm

DS3

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Connected_Standby(1/2)+DS3
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 41 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = DIMM1

Main Func = DIMM2

Vinafix.com Layout Note:

Place Close DIMM1
D D

VREF CIRCUITRY DDR_VREF_S3 1D35V_S3

1
R4210
Do Not Stuff R4201
1K8R2F-GP
DY

2
1 R4202 2
Layout Note: [5] M_VREF_DQ_DIM0
2R2F-GP
M_VREF_DQ_DIMMA
Place Close DIMMs

1
DDR_VREF_S3 C4202 R4209
1D35V_S3 SCD022U16V2KX-3GP 1K8R2F-GP

2
+V_VREF_PATH1

2
1

1
1
R4204 R4211
Do Not Stuff R4206 24D9R2F-L-GP
1K8R2F-GP
DY
SA_DIMM_VREFDQ
2

2
2
2R2F-GP
1 R4208 2
C DIMM1 M_VREF_CA_DIMMA V_SM_VREF_CNT [5]
C

1
C4201
SCD022U16V2KX-3GP Layout Note:

2
1
Place Close DIMM2
R4203 +V_VREF_PATH3

1
1K8R2F-GP
R4207
24D9R2F-L-GP DDR_VREF_S3 1D35V_S3
2

2
1

1
R4205 R4212
Do Not Stuff Do Not Stuff R4216
1K8R2F-GP
DY
SA_DIMM_VREFDQ
2

2
R4213
1 2
DIMM2 M_VREF_CA_DIMMB [5] M_VREF_DQ_DIM1
2R2F-GP
M_VREF_DQ_DIMMB

1
C4203 R4214
SCD022U16V2KX-3GP 1K8R2F-GP

2
+V_VREF_PATH2

2
1
R4215
B 24D9R2F-L-GP B

2
A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Connected_Standby(2/2)
Size Document Number Rev
A3
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 42 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = ADT Input 5V_S5

1
PR4302 3D3V_S5
PQ4302 84.T3904.H11
15KR2F-GP PR4303

E
10KR2J-3-GP

1
PQ3802_1 B LMBT3904LT1G-GP 3D3V_S5

1
2
2
PD4302

1
PR4309 PSID_DISABLE#_R_C LBAV99LT1G-1-GP

Vinafix.com
100KR2J-1-GP PR4304
75.00099.O7D 2K2R2J-2-GP
Layout Note: 2nd = 75.00099.K7D

G
1

3
PSID Layout width > 25mil

2
84.05067.031 3rd = 75.00099.Q7D
PR4305
D
PS_ID_R 1 PR4317 2 PS_ID_R2 D S PS_ID_R1 1 2
4th = 75.00099.D7D D
PS_ID [24]
Do Not Stuff
33R2J-2-GP
PQ4301

1
DMN5L06K-7-GP
DY PD4303 PR4306
Do Not Stuff 1 DY 2

Do Not Stuff

3
DCIN1 60ohm@100MHz
8
DCR=0.02 ohm
6 1 AFTP3806 Max current = 6000mA
5 1 AFTP3803
4 +DC_IN AD+
3 PU4301
2 1 S D 8
S D

PC4305

PC4303

PC4304

PC4306
2 7

SC10U25V5KX-GP
SCD01U50V2KX-1GP
1

Do Not Stuff

Do Not Stuff
1 +DC_IN PC4302 PC4301 S D

240KR3-GP
3 6

K
1

1
EC4301 EC4302 EC4303 EC4304 PR4314 SCD1U50V3KX-GP G D

PR4307
7 4 5

SC1U50V5ZY-1-GP-U
PD4301 DY DY
SC10U25V5KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

3K3R6J-GP P6SBMJ24APT-GP
2

2
ACES-CON6-63-GP

2
20.F2132.006 SI7121DN-T1-GE3-GP

A
1

1 PR4319 2
2nd = 20.F2505.006 PR4312 PQ3809_D Do Not Stuff
100KR2J-1-GP 84.2N702.A3F PQ4305

1
R2
2nd = 84.2N702.E3F PQ4304 E Id=-9.6A

PU4301_G
3rd = 75.00601.07C C AD_OFF_L B PR4308
2

4th = 84.DMN66.03F B R1
R1
C AD_OFF_R 47KR3J-L-GP Qg=-25nC
PQ4306
E Rdson=18~30mohm
3 4 R2 PDTA124EU-1-GP

2
PDTC124EU-1-GP 84.00124.K1K
AC_IN#_G 2 5 84.00124.H1K 2nd = 84.05124.A11
2nd = 84.05124.011
C 1 6 C

2N7002KDW-GP
1

1
PR4313 PR4310
100KR2J-1-GP PC4308
1 2 DY PQ4308
Do Not Stuff Do Not Stuff PR4315

2
G PQ3808G 1 DY 2
2

3D3V_S5 Do Not Stuff

PQ3808D D
DY

1
AC_IN_KBC# S PC4309
[24] AC_IN_KBC#
DY PR4311 DY

Do Not Stuff
DT MODE Do Not Stuff

2
Do Not Stuff
Do Not Stuff

1
PWR_CHG_AD_OFF_R
[24] AC_DIS

Do Not Stuff
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F
PBAT_PRES# [24,44]
AFTP3801 1 +DC_IN
PQ4303
AFTP3802 1 PS_ID_R
AFTP3805 1 +DC_IN 1 6
AFTP3807 1 +DC_IN PR4316 PC4310
2 DY 1 2 DY 5 PQ4303_5 1 DY2Do Not Stuff
Do Not Stuff 3 4

1
[4,24,44,46] H_PROCHOT# Do Not Stuff DY PR4318
B Do Not Stuff B

2
Main Func = M-BAT Input
Placement: Close to Batt Connector

BT+

SMBCLK1
PBAT_PRES#

SMBDA1
K
1

EC4308 EC4307 EC4311 EC4312 EC4313 EC4314

Batt Connecter
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

DY PD4304
SC1U25V3KX-1-GP

Do Not Stuff
2

BATT1 D4304 D4305 D4306

9 LBAV99LT1G-1-GP LBAV99LT1G-1-GP LBAV99LT1G-1-GP

RN4302
1 75.00099.O7D 75.00099.O7D 75.00099.O7D
4 5 2
1

3 6 PBAT_SMBCLK1 3
[24,44] SMBCLK1
2 7 PBAT_SMBDAT1 4
[24,44] SMBDA1
1 8 PBAT_PRES1# 5
[24,44] PBAT_PRES#
6

SRN100J-4-GP
7 2nd = 75.00099.K7D 2nd = 75.00099.K7D 3D3V_S5_KBC
8 2nd = 75.00099.K7D
10 3rd = 75.00099.Q7D 3rd = 75.00099.Q7D
A SYN-CON8-9-GP-U
3rd = 75.00099.Q7D A
4th = 75.00099.D7D 4th = 75.00099.D7D
20.81153.008 4th = 75.00099.D7D
2

EC4309 EC4310 EC4306

1

1
Do Not Stuff

Do Not Stuff

Do Not Stuff

DY 2nd = 20.81157.008
DY DY
1

<Core Design>
2

1 AFTP3906
1 AFTP3909
1 AFTP3910 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
PBAT_PRES1# 1 AFTP3902 Taipei Hsien 221, Taiwan, R.O.C.
PBAT_SMBDAT1 1 AFTP3903
PBAT_SMBCLK1 1 AFTP3904 Title
BT+ 1 AFTP3905
BT+
BT+
1
1
AFTP3908
AFTP3907 Size Document Number
DCIN Rev
A2 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 43 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Charger

AD+ +SDC_IN DCBATOUT

PU4402
8 D S 1 PR4402 1 2
7 D S 2 D01R3721F-GP-U
6 D S 3
5 D G 4

1
PG4402 PG4403

PR4403
SI7121DN-T1-GE3-GP Do Not Stuff Do Not Stuff

100KR2J-1-GP
84.07121.037

2
2
Vinafix.com

1
PR4404
PR4405 AD+_G_2 Do Not Stuff
3KR5J-GP 2 DY 1

2
PC4402

10KR2F-2-GP
D D

2DC_IN_D

PR4406
2 1

PWR_CHG_ACP
SCD1U25V2KX-GP
CHARGER_SRC
PQ4402

1
AD+_G_1

SCD1U25V2KX-GP
3 4 PC4404 A00 ESD

PWR_CHG_ACN

Do Not Stuff
DCBATOUT CHARGER_SRC

PC4403

Do Not Stuff
ACOK_IN 2 5 PG4404

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SCD1U50V3KX-GP

SCD1U25V2KX-GP
Do Not Stuff
DY

SC10U25V5KX-GP
1
1 6 2 1

PC4406

PC4408

PC4409

PC4410

PC4411
1

1
PC4405

PC4407
2N7002KDW-GP PG4405
84.2N702.A3F CHG_AGND Do Not Stuff
2 1 DY

2
CHG_AGND PD4402
CH035H-40PT0-GP PG4406
83.1R504.B8F Do Not Stuff
Battery type 4 series 3 series 2 series 2 1

PWR_CHG_1
K A AD+
PG4407
Do Not Stuff
2 1 PQ4403
PR4408 309kohm 287kohm 287kohm K A BT+ G
AC_DIS [24]

1
PD4405 D
CH035H-40PT0-GP

AD+
PR4409 47kohm 47kohm 47kohm PR4407 S
10R2J-2-GP 83.1R504.B8F
2N7002K-2-GP

2
309KR2F-GP

84.2N702.J31
1

PWR_CHG_VCC 2 1
ACDET 18.178V 17.055V 17.055V

AC_DIS_M
PR4408

PC4412 CHG_AGND

28
PU4401 SC1U25V3KX-1-GP PR4422
PC4401 20KR3J-1-GP AD+

VCC
2

+SDC_IN SC2D2U10V3KX-1GP 2 1
SCD01U50V2KX-1GP

24 PWR_CHG_REGN 2 1
REGN
47KR2F-GP

PWR_CHG_ACN 1
1

1
ACN
PR4409
1
PC4413

PR4410 18 PR4430

5
6
7
8
3D3V_S5_KBC 4K02R2F-GP PWR_CHG_ACP BATDRV 470KR2F-GP
C 2 PU4403
C

D
D
D
D
ACP PU4404 DCBATOUT
2

17 PWR_CHG_BATSRC1 2 BT+_1 Do Not Stuff 5 4

2

2
PWR_CHG_CMSRC BATSRC PR4414
D G
3 6 3
CMSRC 10R2F-L-GP PD4403 Do Not Stuff 7
D S
2

PWR_CHG_PHASE_1
D S
25 PWR_CHG_BTST K A
65BOM charger 8 1
1

BTST D S

G
S
S
S
4
PR4411 PR4412 ACDRV CH035H-40PT0-GP
DY DY

4
3
2
1
Do Not Stuff Do Not Stuff SI7121DN-T1-GE3-GP BT+
83.1R504.B8F
PWR_CHG_ACDET 6 26 PWR_CHG_HIDRV 84.07121.037
ACDET HIDRV
2

1
PL4401 PR4415
PG4409 PC4414 D01R3721F-GP-U
Do Not Stuff 27 PWR_CHG_PHASE SCD047U25V2KX-GP 1 2 1 2

2
PWR_CHG_SDA PHASE COIL-4D7UH-33-GP
2 1 11

SCD1U50V3KX-GP
[24,43] SMBDA1 SDA

Do Not Stuff

SC10U25V5KX-GP
68.4R71A.20H

SC10U25V5KX-GP
SC10U25V5KX-GP

Do Not Stuff
5
6
7
8

Do Not Stuff
PWR_CHG_SCL PWR_CHG_LODRV

PC4415

PC4416

PC4417

PC4418

PC4419
[24,43] SMBCLK1 2 1 12 23

2
D
D
D
D
SCL LODRV

Do Not Stuff
PU4405

PG4417
Pull High at page 24 PG4410 PG4411 Do Not Stuff

1
Do Not Stuff Do Not Stuff
Do Not Stuff

PG4413
PR4416 22 2 1

1
GND

PG4412
Do Not Stuff DY
65BOM charger

2
G
S
S
S
ACOK_IN 1 2 PWR_CHG_ACOK 5

1
PG4401 ACOK PWR_CHG_SRP CHG_AGND
20

4
3
2
1
Do Not Stuff SRP
2 1 PWR_CHG_IADP 7
[24] AD_IA IADP
PG4414 19 PWR_CHG_SRN
Do Not Stuff SRN
2 1 PWR_CHG_IDCHG 8 BT+_1
[24] boost_mon IDCHG
PG4415
Do Not Stuff PR4417 PC4420
2 1 PWR_CHG_PMON 9 1 2 PWR_CHG_SRP_1 1 2
[24,46] P_SYS

1
PMON PWR_CHG_STAT# 1 PC4421 PC4422
16

1
PR4418 TB_STAT# 10R2F-L-GP Do Not Stuff SCD1U25V2KX-GP Do Not Stuff
Do Not Stuff TP4405
DY
DY

2
1 2 PWR_CHG_PROCHOT# 10 15 PWR_CHG_BATPRES#
[4,24,43,46] H_PROCHOT#

2
PROCHOT# BATPRES#
SC100P50V3JN-2GP

SC100P50V3JN-2GP
1

1
30KR2F-GP

PR4419
PWR_CHG_CMPIN CHG_AGND CHG_AGND
PC4423

PC4424

PR4425

13
CMPIN PWR_CHG_SRN_1
1 2
2

B TP4404 B
1 PWR_CHG_CMPOUT 14
2

CMPOUT 7D5R2F-GP
29
3D3V_AUX_S5 GND
21
ILIM
1

CHG_AGND CHG_AGND CHG_AGND

PWR_CHG_ILIM

PR4420 PR4421 BQ24780SRUYR-GP PWR_CHG_REGN

100KR2J-1-GP Do Not Stuff CHG_AGND
DY
For BQ24780S, 2 1
AD+ PBAT_PRES# [24,43]
074.24780.0B73
2

change PC4425 from 100pF PG4416

1
Do Not Stuff
1

to PR4425 30kohm resister 1 PR4435

PR4423 PR4424 100KR2J-1-GP
Do Not Stuff 10KR2F-2-GP PR4431
DY
100KR2J-1-GP

2
2

PWR_CHG_ACOK [17,24]

1
DCBATOUT PR4432
1

120KR2J-GP
PR4433
CHG_AGND CHG_AGND Do Not Stuff H_PROCHOT# [4,24,43,46]
DY

2
E PQ4408_E
1

2
2

PR4458 PR4455 84.2N702.A3F

Do Not Stuff Do Not Stuff 2nd = 84.DM601.03F
PD4404 3rd = 84.2N702.E3F
1N4148WS-7-F-GP 4th = 84.2N702.F3F
2

PQ4405
K APD4403_A B
PQ4405_3
PD4403_K

PR4462 3 4
PQ4408
C

LMBT3906LT1G-1-GP PQ4408_C 2 1 PQ4405_2 2 5 PQ4405_5

1
PC4426
SC1U25V3KX-1-GP
84.T3906.E11 Do Not Stuff 1 6
1

2N7002KDW-GP

2
PR4451 PR4463
680KR2F-GP Do Not Stuff DY
A A

PQ4405_6
2

2PWR_CHG_ACOK

CHECK EE

2
PR4413
follow custormer circuits. 1
100KR2F-L1-GP
<Core Design>
PR4450

1
10KR2F-2-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2

Taipei Hsien 221, Taiwan, R.O.C.

Title
3D3V_S5

Size
CHARGER
Document Number
BQ24770 Rev
A2
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 44 of 105
5 4 3 2 1
 A B C D E

Main Func = 3D3V_5V

Vinafix.com
3D3V_AUX_S5
4 4

DCBATOUT PWR_DCBATOUT_5V

1
PR4501
PG4520
Do Not Stuff DY 2 1

2
PR4504 Do Not Stuff
PR4530 PG4536
Do Not Stuff
PWR_5V_EN1_R PWR_5V_EN1 2 1
2 DY 1 1 2

Do Not Stuff Do Not Stuff

2
PG4518
PR4507 2 1
DCBATOUT PWR_DCBATOUT_3D3V Do Not Stuff Do Not Stuff
PR4506 PG4534

1
PG4525 Do Not Stuff 2 1
2 1
1 2 PWR_3D3V_EN2
[40] 3V_5V_EN Do Not Stuff
Do Not Stuff PG4542
PG4521 2 1
2 1
Do Not Stuff
Do Not Stuff PG4543
PG4524 2 1
2 1
Do Not Stuff
Do Not Stuff
PG4531
2 1
DCBATOUT
Do Not Stuff

PWR_DCBATOUT_3D3V

PC4528 PC4509
PC4525 PC4519 PC4531
SC4D7U25V5KX-GP
1

1
Do Not Stuff

Do Not Stuff
PWR_DCBATOUT_5V

1
SCD1U50V3KX-GP

SCD01U50V2KX-1GP
DY
3 DY 3
2

2
PC4530 PC4529 PC4527
PU4504
8
7
6
5

5
6
7
8

1
Do Not Stuff

SCD1U50V3KX-GP

SC4D7U25V5KX-GP

SC10U25V5KX-GP
Do Not Stuff

D
D
D
D
D
D
D
D

PU4501

12

2
Design Current=5A PU4503 Design Current=7A
65BOM charger
65BOM charger

VIN
7.5A<OCP>9A PC4535 PR4528 10.5A<OCP>12.6A

G
S
S
S
1PWR_3D3V_VBST2_11 2 PWR_3D3V_VBST2 PC4516
S
S
S
G

2
1D5R3-GP PR4524
1
2
3
4

4
3
2
1
9 17 PWR_5V_VBST1 1 2 PWR_5V_VBST1_1 1 2
SCD1U50V3KX-GP BOOT2 BOOT1
3D3V_S5 1D5R3-GP
68.3R310.20A PWR_3D3V_DRVH2 10 16 PWR_5V_DRVH1 SCD1U50V3KX-GP 68.2R210.20B 5V_S5
PL4502 UGATE2 UGATE1 PL4501
1 2 PWR_3D3V_LL2 8 18 PWR_5V_LL1 1 2
IND-3D3UH-57GP PHASE2 PHASE1
1

PWR_3D3V_DRVL2 11 15 PWR_5V_DRVL1 IND-2D2UH-46-GP-U

1
LGATE2 LGATE1

5
6
7
8
PR4533 DY PU4502 PR4529 PG4532 PC4518
8
7
6
5

D
D
D
D

Do Not Stuff
PC4517 PT4502 PG4535 Do Not Stuff 14 PWR_5V_VO1
DY Do Not Stuff
1

1
BYP1

Do Not Stuff
D
D
D
D

PU4505
2
1

Do Not Stuff
SE220U6D3VM-38-GP

Do Not Stuff

Do Not Stuff PWR_3D3V_FB2 4 2 PWR_5V_FB1 DY PT4501

2
FB2 FB1
Do Not Stuff

DY
1PWR_3D3V_SNUB

65BOM4 charger

SE220U6D3VM-38-GP
2

2
G
65BOM charger 074.06576.0043 79.22710.3KL
2

2
S
S
S

1PWR_5V_SNUB
PWR_3D3V_EN2 PWR_5V_EN1
S
S
S
G

6 20

3
2
1
EN2 EN1
1
2
3
4
3V_FEEDBACK

PWR_3D3V_CS2 5 1 PWR_5V_CS1
CS2 CS1 TP4501
1

1
Do Not Stuff
PR4517 PWR_5V_VCLK 1 PR4531
79.22710.3KL PC4520
DY 174KR2F-GP VCLK
19
137KR2F-1-GP PC4536
DY
2

Do Not Stuff Do Not Stuff

2
7 21
2

2
PGOOD GND
LDO3

LDO5
1

1
2 RT6576DGQW-GP 2
3

13

PR4512 PR4535 PR4525

1
6K8R2F-2-GP 3D3V_PWR_2
DYDo Not Stuff 3D3V_S5
5V_PWR_2 Do Not Stuff DY PR4527
PR4534 15K4R2F-GP
PWR_5V_FB1_R
2

1 2

1 2
PWR_3D3V_FB2_R
1
Do Not Stuff

PC4523

2
1

DYDo Not Stuff PC4526

PC4524
Do Not Stuff
PC4522 DY
DY
2

2
SC4D7U6D3V3KX-GP SC1U10V3KX-4GP-U
2

2
2
1

1
PR4523 PR4526
10KR2F-2-GP 9K76R2F-1-GP
[17,40,53,54] 3V_5V_POK
PH at Page40 Close to VFB Pin (pin2)
2

2
3D3V_PWR_2 3D3V_AUX_S5

PR4532
1 2
Close to VFB Pin (pin5) Do Not Stuff

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L Inductor: CHIP CHOKE 2.2U PCMC063T-2R2MN 18mohm/20mohm Isat =14Arms 68.2R210.20B
Inductor: CHIP IND 3.3UH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A O/P capCHIP CAP EL 220U 6.3V M6.3*4.4 /Chemi-con/ 18mOhm / 79.22710.3KL
O/P capCHIP CAP EL 220U 6.3V M6.3*4.4 /Chemi-con/ 18mOhm / 79.22710.3KL H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037 L/S:SIS780 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037
L/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
1 1

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DCDC-3D3V&5V
Size Document Number Rev
A2
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 45 of 105
A B C D E
 5 4 3 2 1

Main Func = CPU_CORE

PR4611
48D7KR2F-GP
1 2

Vinafix.com
PC4632
1 2

PC4602
PR4602 SCD01U50V2KX-1GP SC1KP50V2KX-1GP
D 750R2F-GP 81208_AGND D
1 2 PWR_VCCSA_COMP_R 1 2 PWR_VCCSA_CSN [50]

2
PR4606
PC4604 PC4606 NTC-100K-11-GP-U

1
SC15P50V2JN-2-GP SCD015U25V2KX-GP
69.60013.201

1
1 2 PC4607 PR4609
PC4603 SCD01U50V2KX-1GP 14K3R2F-GP

2
SC1KP50V2KX-1GP

1
PWR_VCCSA_VSN_R 1 2 1 2 PWR_VCCSA_CSN_NTC
81208_AGND
PR4605 PR4612
[7] VSSSA_SENSE PR4604 1 2 1 2 1 2 PWR_VCCSA_CSP [50]
Do Not Stuff 8K06R3F-AS-GP
825R2F-GP PR4613 102KR2F-GP 3D3V_S0

2
PC4605 1 2
SC1KP50V2KX-1GP

1
PR4608 PC4609 SC220P50V2KX-3GP

1
2K74R2F-GP
[7] VCCSA_SENSE PR4607 1 2 1 2
1 2
DY PR4614
Do Not Stuff
Do Not Stuff
81208_AGND

2
PWR_VCCSA_VSP_R 1 2 1 2 PR4670 1 2 Do Not Stuff VR_RDY
PR4616 PR4630 1 2 Do Not Stuff
PC4608 VR_EN [40,52]
2K49R2F-GP SC1KP50V2KX-1GP +VCCST_CPU
PWR_VCCSA_VSP_RC PR4671 1 2 PSYS
[24,44] P_SYS
Do Not Stuff

Do Not Stuff
PR4622

100R2F-L1-GP-U
PR4623

1
PC4610
SCD1U25V2KX-GP +VCCST_CPU +VCCSTG Check +VCCST_CPU or +VCCSTG

2
[7] VCCGT_SENSE Do Not Stuff 1 2 PR4617

1
45D3R2F-L-GP
PR4621
DY

1
PC4611 [#543016]
SC1KP50V2KX-1GP

1
C PR4619 C
[7] VSSGT_SENSE Do Not Stuff 1 2 PR4618 2 1 1KR2F-3-GP PR4624 PR4669
Do Not Stuff
VR_SVID_CLK [7] DY DY Do Not Stuff
PWR_VCCGT_VSN_R 1 2 VR_SVID_ALERT# [7]

2
PC4612 SC2200P50V2KX-2GP PG4601 VR_SVID_DATA [7]
Do Not Stuff

[50]

[47,48,50]
PR4668

PWR_VCCSA_PWM
2 1

PWR_VCORE_DRVON
1

PR4665

PR4666

PR4667
1 2 H_PROCHOT# [4,24,43,44]
PR4625 100R2F-L1-GP-U
37D4R2F-GP
81208_AGND

PWR_VCORE_VR_RDY
1

PWR_VCCSA_CSP1B
PR4626

PWR_VCCSA_COMP
2

PWR_VCCSA_IOUT

49D9R2F-GP

0R2J-2-GP

10R2F-L-GP
PWR_VCCGT_VSN

PWR_VCCSA_VSN
PWR_VCCGT_VSP

PWR_VCCSA_VSP

PWR_VCCSA_ILIM
1KR2F-3-GP PC4613 1 2 SC470P50V2KX-3GP

PWR_VCORE_EN

1
PWR_VCCGT_FB_R PR4627
1 2 1 2 PWR_VCORE_CSP [47]
1

PR4632 PR4628 8K06R3F-AS-GP

2

PC4614 24K9R2F-L-GP 107KR2F-GP

SC470P50V2KX-3GP 1 2 81208_AGND
2

2
PR4629
81208_AGND
1 2 PWR_VCORE_CSNNTC
1

PWR_VCORE_VRHOT#
PWR_VCORE_ALERT#

2
PR4631 14KR2F-GP

49

48
47
46
45
44
43
42
41
40
39
38
37

PWR_VCORE_SCLK

PWR_VCORE_SDIO
PC4617 4K75R2F-1-GP 1 2 PU4601 PR4633
1

1
SC10P50V2JN-4GP NTC-100K-11-GP-U

PSYS
VSP_1B
VSN_1B
COMP_1B
ILIM_1B
CSN_1B
CSP_1B
IOUT_1B
VR_RDY
GND

VSN_2PH
VSP_2PH

EN
PWR_VCCGT_ILIM_R

PC4615 PC4634 PC4616

69.60013.201
2

SC470P50V2KX-3GP SCD022U16V2KX-3GP SCD056U16V2KX-GP

2

2
PWR_VCCGT_COMP_R
1

PR4634 PC4618 81208_AGND PWR_VCORE_CSN [47]

1
1 2 SC2200P50V2KX-2GP PWR_VCCGT_IOUT 1 36 PR4635
PWR_VCCGT_DIFFOUT IOUT_2PH PWM_1B
2 35 1 2
2

PR4638 NTC-220K-5-GP-U PWR_VCCGT_FB DIFFOUT_2PH DRVON

3 34
200KR2F-L-GP PWR_VCCGT_COMP FB_2PH SCLK 61K9R2F-GP
4 33
PWR_VCCGT_ILIM COMP_2PH ALERT#
[48] PWR_VCCGT_CSPA 1 2 2 1 1 PR4639 2 1 PR4640 2 5 074.81208.0B73 32
PR4637 PWR_VCCGT_CSCOMP ILIM_2PH SDIO
6 31 PR4636
1

57K6R3F-2-GP PC4620 12K4R2F-GP PWR_VCCGT_CSSUM CSCOMP_2PH VR_HOT# PWR_VCORE_IOUT PC4633 81208_AGND

7 30
75KR2F-GP SC1KP50V2KX-1GP PWR_VCCGT_CSREF CSSUM_2PH IOUT_1A PWR_VCORE_CSP_1A PWR_VCORE_COMP_R
DY PC4621
Do Not Stuff
8
CSREF_2PH CSP_1A
29 1 2 PC4601 1 2 1 2
9 28 SC1KP50V2KX-1GP SC1500P50V2KX-2GP
2

CSP2_2PH CSN_1A PWR_VCORE_ILIM 2K49R2F-GP

10 27
CSP1_2PH ILIM_1A PWR_VCORE_COMP PC4622 PC4619
11

ROSC_COREGT
26 1 2
TSENSE_2PH COMP_1A

ADDR_VBOOT
B 12 25 PWR_VCORE_VSN 2 1PWR_VCORE_VSN_R SC15P50V2JN-2-GP 81208_AGND B

TSENSE_1PH
ICCMAX_2PH
ROSC_SAUS
VRMP VSN_1A

ICCMAX_1A
ICCMAX_1B
PWM1_2PH
PWM2_2PH
5V_S5 SC1KP50V2KX-1GP
PWR_VCORE_VRMP

PWM_1A

VSP_1A
1 2 PR4645 2 1 Do Not Stuff VSS_SENSE [7]
1

PR4644
VCC
1

1
[48] PWR_VCCGT_CSNA PR4646 2 1 10R2F-L-GP PR4603 422R2F-2-GP PC4625
PC4623 1KR2F-3-GP SC1KP50V2KX-1GP
SCD047U25V2KX-GP PR4647
NCP81208MNTXG-2-GP
2

13
14
15
16
17
18
19
20
21
22
23
24

2
1 2 PR4648 2 1 Do Not Stuff VCC_SENSE [7]
2

PWR_VCCGT_CSP2 3K4R2F-GP
1

PWR_VCORE_VCC_R

PWR_VCORE_ROSC_SAUS

PC4626 PWR_VCCGT_CSP1 PWR_VCORE_VSP 2PWR_VCORE_VSP_RC PWR_VCORE_VSP_R

PWR_VCORE_ROSC_COREGT

1 1 2
SCD01U50V2KX-1GP PWR_VCCGT_TSENSE PR4649
2

2K49R2F-GP PC4627
DCBATOUT PWR_VCORE_TSENSE SC1KP50V2KX-1GP 2 PR4650 1 PWR_VCORE_NTC
PR4651 81208_AGND PWR_VCORE_PWM [47] Do Not Stuff
[48] PWR_VCCGT_CSPA 1 2 PR4601 PWR_VCORE_ADDR_BOOT

2
1 2 1KR2F-3-GP PWR_VCCSA_ICCMAX

1
4K87R2F-GP PWR_VCORE_ICCMAX PR4652 PR4653
PWR_VCCGT_ICCMAX PC4628 12K7R2F-GP NTC-100K-11-GP-U
1

SCD1U25V2KX-GP
69.60013.201

2
PC4629

2
SCD01U50V2KX-1GP
2

1
PR4662 PR4658 PR4660

1
PWR_VCCGT_NTC 1 PR4655 2 PR4663

90K9R2F-GP

18K7R2F-GP
49K9R2F-L-GP
Do Not Stuff 10KR2F-2-GP
81208_AGND 81208_AGND
2

5V_S5
2

2
1

PR4656 PR4657
NTC-100K-11-GP-U PR4661 PC4630 2D2R2F-GP PR4664 PR4659
69.60013.201 12K7R2F-GP SCD1U25V2KX-GP 1 2 24KR2F-GP 24KR2F-GP For NCP81208MNTXG-2-GP Vboot
2

U22 15W U23e 28W

2

2
1
1

PR4637 47K (64.47025.55L) 73K (64.73225.55L) PC4631

SC1U10V2KX-1GP 81208_AGND
2

PR4641 47K (64.47025.55L) 73K (64.73225.55L)

81208_AGND
PR4640 12.4K (64.12425.6DL) 15K (64.15025.6DL) 81208_AGND 81208_AGND 81208_AGND
PWR_VCCGT_PWMA [48]
PR4662 49.9K (64.49925.6DL) 88.7K (64.88725.6DL)
A A
PR4658 88.7K (64.88725.6DL) 90.9K (64.90925.6DL)

PR4647 2.37K (64.23715.6DL) 2.15K (64.21515.6DL)

PR4635 38.3K (64.38325.6DL) 37.4K (64.37425.6DL)

<Core Design>
PR4628 73.2K (64.73225.6DL) 69.8K (64.69825.6DL)

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
NCP81208MN_CPU_VCORE(1/3)
Size Document Number Rev
A2 Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 46 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU_CORE

DCBATOUT

For acoustic noice

Vinafix.com

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SCD1U25V2KX-GP
PC4710

1
D PC4702 PC4703 PC4701 PC4704 PC4705 D
DCBATOUT

2
1

1
PT4702
SE33U25VM-10-GP
OPSPT4703
SE33U25VM-10-GP

2
PR4701
1 2 PW R_VCORE_BOOT_RC

PWR_VCORE_BOOT
3D9R3-GP

1
5V_S5 PC4706
SCD22U25V3KX-GP
PR4702

2
2D2R2F-GP

25
26
27
28
29
30

33

35
1
2 1 PW R_VCORE_VCC PU4701

THWN

VIN
VIN
VIN
VIN
VIN
VIN

GH

BOOT
1
PC4708 VCC_CORE
SC1U10V2KX-1GP 6
2
C VCC PW R_VCORE_PHASED C
PHASED 34 PL4701
7 VCCD PHASEF 32
1

PC4707 12 PW R_VCORE_SW 1 2
SC2D2U10V2KX-GP VSW#12
5 13
2

CGND VSW#13
VSW#14 14 COIL-D15UH-2-GP
15
4
074.81382.0AE3 VSW#15
16 68.R1510.20A
[46] PW R_VCORE_PW M PWM VSW#16
VSW#17 17
PR4704 1 2 PW R_VCORE_DISB# 2 18
DISB# VSW#18

1
[46,48,50] PW R_VCORE_DRVON Do Not Stuff PT4701
36 Do Not Stuff
ZCD_EN DY

1
5V_S5 PG4707 PG4708

2
Do Not Stuff

Do Not Stuff
3 PR4703
DY

1
SMOD# Do Not Stuff

GL#10
GL#11

PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
GL#8
GL#9

2
NCP81382MNTXG-1-GP PW R_VCORE_SNUB
8
9
10
11

19
20
21
22
23
24
31
37

1
PW R_VCORE_GL
DY PC4709
Do Not Stuff

2
Confirm with EE:
22uF/0805 total 32pcs (DY 5 pcs)
B B
[46] PW R_VCORE_CSP

[46] PW R_VCORE_CSN

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
NCP81382MN_CPU_VCORE(2/3)
Size Document Number Rev
A3 Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 47 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU_CORE

DCBATOUT

Vinafix.com

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SCD1U25V2KX-GP
D D
PC4811

1
PC4802 PC4803 PC4804 PC4805 PC4806

2
PR4802
1 2

PWR_VCCGT_BOOTA
3D9R3-GP PW R_VCCGT_BOOTA_RC

5V_S5

1
PC4809
SCD22U25V3KX-GP
PR4803

2
2D2R2F-GP

25
26
27
28
29
30

33

35
1
2 1 PW R_VCCGT_VCCA PU4801

THWN

VIN
VIN
VIN
VIN
VIN
VIN

GH

BOOT
1

C PC4808 C
SC1U10V2KX-1GP 6 +VCCGT
2

VCC PW R_VCCGT_PHASEDA
PHASED 34 PL4801
7 VCCD PHASEF 32
1

PC4807 12 PW R_VCCGT_SW A 1 2
SC2D2U10V2KX-GP VSW#12 COIL-D15UH-2-GP
5 13
2

CGND VSW#13
VSW#14 14 68.R1510.20A
15
074.81382.0AE3 VSW#15

1 PT4801
4 PWM VSW#16 16
[46] PW R_VCCGT_PW MA 17
PR4808 PW R_VCCGT_DISB#_A VSW#17
1 2 2 DISB# VSW#18 18

2
[46,47,50] PW R_VCORE_DRVON Do Not Stuff
36 ZCD_EN

1
5V_S5 PG4808 PG4809

Do Not Stuff

Do Not Stuff
3 PR4804

2
SMOD# Do Not Stuff
DY
GL#10
GL#11

PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
79.33719.L01
GL#8
GL#9

SE330U2VDM-L-GP
2
NCP81382MNTXG-1-GP
8
9
10
11

19
20
21
22
23
24
31
37
PW R_VCCGT_SNUB_1

1
PW R_VCCGT_GL1
PC4810
Do Not Stuff
DY

2
B B

Confirm with EE:

22uF/0805 total 35pcs (DY 5 pcs)
[46] PW R_VCCGT_CSPA

[46] PW R_VCCGT_CSNA

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
NCP81382MN_CPU_VCCGT(3/3)
Size Document Number Rev
A3 Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 48 of 105

5 4 3 2 1
 5 4 3 2 1

Main Func = CPU_CORE

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
NCP81210MN_CPU_VCCGTUS
Size Document Number Rev
A4 Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 49 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU_CORE

DCBATOUT DCBATOUT_+VCCSA
Vinafix.com
PG5023
D 2 1 D

Do Not Stuff
PG5024
2 1

Do Not Stuff

DCBATOUT_+VCCSA

PC5029 PC5027 PC5002

1
SC10U25V5KX-GP

SC10U25V5KX-GP

SCD1U25V2KX-GP
5
6
7
8
PR5013

2
D
D
D
D
1 2 PW R_VCCSA_BST_RC PU5002
Do Not Stuff #543977 Intel PDG Rev0.91
2D2R3-1-U-GP +VCCSA(ICCMAX.=5A)
PWR_VCCSA_BST

65BOM charger

G
S
S
S
PC5008
SCD22U25V3KX-GP PW R_+VCCSA +VCCSA

4
3
2
1
2
PW R_+VCCSA
C PU5001 PG5026 C

PL5001 2 1
1 8 PW R_VCCSA_DRVH
BST DRVH PW R_VCCSA_SW Do Not Stuff
2 PWM SW 7 1 2
[46] PW R_VCCSA_PW M 3 6 PG5025
[46,47,48] PW R_VCORE_DRVON EN GND
5V_S5 4 VCC DRVL 5 IND-D47UH-22-GP 2 1

1
9 Do Not Stuff
GND
1

PR5014 PG5028
PC5001 Do Not Stuff 2 1
DY

5
6
7
8

2
SC2D2U10V3KX-1GP NCP81253MNTBG-1-GP
2

D
D
D
D
PU5003 Do Not Stuff

2
PG5021 PG5022

PWR_VCCSA_SNUB
Do Not Stuff PG5027
074.81253.0AE3

Do Not Stuff

Do Not Stuff
2 1

1
65BOM charger Do Not Stuff

G
S
S
S
PG5030
2 1

4
3
2
1
PW R_VCCSA_DRVL Do Not Stuff
PG5029

1
2 1
PC5031
DY Do Not Stuff Do Not Stuff

2
PG5031
2 1

Do Not Stuff
B B

Confirm with EE:

[46] PW R_VCCSA_CSP 22uF/0805 total 20pcs (DY 5 pcs)

[46] PW R_VCCSA_CSN

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
NCP81253MN_CPU_VCCSA
Size Document Number Rev
A3 Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 50 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = VDDQ

DCBATOUT +PWR_SRC_1D35V
Vinafix.com
PG5103
D D
2 1

Do Not Stuff
PG5104
2 1

Do Not Stuff
PG5105
2 1

Do Not Stuff
PG5106
2 1
+PWR_SRC_1D35V
Do Not Stuff
PG5124
2 1 5V_S5

Do Not Stuff PC5112

PC5109 PC5111 PC5114

2
Do Not Stuff
SC4D7U25V5KX-GP

SC4D7U25V5KX-GP
1

SC4D7U25V5KX-GP
3D3V_S0 PC5113
DY

1
PC5101 SCD1U50V3KX-GP

1
2

2
SC1U10V3KX-4GP-U
2
1

DY PR5104 PU5102

5
6
7
8
Do Not Stuff PR4605_2

D
D
D
D

Do Not Stuff
PU5101
2

20 12 PC5119 Design Current=13.6A

[40] 1D35V_VTT_PWRGD
Do Not Stuff PGOOD V5IN SCD1U50V3KX-GP 65BOM charger
2 PR5109 1 DDR_VTT_PG_CTRL_R 17 PR5105 20.4A<OCP>24.5A
[5] SM_PGCNTL S3

G
S
S
S
15 PWR_1D35V_VBST 1 2 1 2
VBST
2 PR5110 1 Do Not Stuff PWR_1D35V_EN 16

4
3
2
1
[17,24,27,40,52,54] SIO_SLP_S3# S5 2D2R3-1-U-GP
DY PWR_1D35V_VREF PWR_1D35V_DRVH
6 14
VREF DRVH
1

C 1D35V_S3 C
PR5103 PL5101
10KR2F-2-GP 13 PWR_1D35V_SW 1 2
SW
IND-D47UH-22-GP
2

5
6
7
8
PWR_1D35V_REFIN 8 11 PWR_1D35V_DRVL
30K1R2F-L-GP

1
D
D
D
D
REFIN DRVL

Do Not Stuff
2

Do Not Stuff

1
PU5103 PC5121 PC5123 PC5124 PC5125 PC5126 PC5127 PC5128 EC5101 EC5102 EC5103
PC5103

PC5102

DY

PC5120
10

PG5107
1

PGND

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

Do Not Stuff

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
PWR_1D35V_MODE Do Not Stuff PR5112
19
65BOM charger DY DY
1

PR5108 MODE Do Not Stuff

2 PR5101

2
12KR2F-L-GP

1
G
4

2
1

SCD1U16V2KX-3GP
S
S
S
PWR_1D35V_TRIP 18 9 PWR_1D35V_VDDQS
182KR2F-GP
SCD1U16V2KX-3GP
2

TRIP VDDQSNS

PWR_1D35V_VDDQS
SCD01U50V2KX-1GP

3
2
1
PR51021
Do Not Stuff

+0D675V_DDR_P TPS51216_PHS_SET
PR4601_1

2
PWR_1D35V_VTTREF VLDOIN
PC5115

5
VTTREF
1

1
3

SC10U6D3V3MX-GP
2

PC5118 VTT PC5122

PR5106

DY
1

1
Do Not Stuff
SCD22U10V2KX-1GP Do Not Stuff
PC5116

PC5117
1
2

2
VTTSNS
21 DY
SCD1U16V2KX-3GP
2

GND
4
2

2
VTTGND
7
GND
TPS51716RUKR-GP
74.51716.073 1D35V_S3

1
+0D675V_DDR_P 0D675V_S0 PC5104
PG5101 DDR_VREF_S3 PR5107
2 1 1 2 PWR_1D35V_EN

SC1U10V3KX-4GP-U
PR5111

2
[17,24,40] SIO_SLP_S4#
Do Not Stuff PWR_1D35V_VTTREF 1 2 Do Not Stuff PC5106

1
PG5102 DY
2 1 Do Not Stuff

Do Not Stuff
2
Do Not Stuff

B B

State S3 S5 VDDR VTTREF VTT I/P cap: 10U 25V K0805 X5R/ 78.10622.51L
Inductor: CHIP CHOKE 0.68UH PCMC063T-R68 4~4.2mohm Isat =26Arms 68.R4710.10M
S0 Hi Hi On On On
O/P cap:CHIP CAP C 22U 6.3V M0805 X5R / 78.22610.51L
S3 Lo Hi On On Off(Hi-Z) H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
S4/S5 Lo Lo Off Off Off L/S:SIS780 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037

A A
20140728 david

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

MEM&MEMVTT
Size Document Number Rev
C Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 51 of 105
5 4 3 2 1
 A B C D E

Vinafix.com
4 4

VCCIO Design Current=2A

+VCCIO(ICCMAX = 2.73A)

+VCCIO 1D0V_PW R
5V_S5 1D0V_PW R
Cyntec. 2.5mm×2.0mmX1.2mm
DCR: 59m Ohm
PU5203
Idc : 3 A , Isat : 3A
1 VIN#1 VOUT#8 8
2 VIN#2 VOUT#7 7
3 VBIAS VOUT#6 6
1 2 PW R_VCCIO_EN 4 5
[17,24,27,40,51,54] SIO_SLP_S3#
PR5216 DY Do Not Stuff ON GND
DY 9
VIN#9

1
1 2
DY PC5227
[40,46] VR_EN PR5218 DY
Do Not Stuff Do Not Stuff Do Not Stuff

2
Do Not Stuff

3 3

VCCPRIM_CORE Design Current=1.8A

ICCMAX= 2.57A
2 2

1D0V_PW R
VCCPRIM_CORE
0.95 V PG5211
2 1

Do Not Stuff
PG5212
2 1

Do Not Stuff
PG5213
2 1

Do Not Stuff
PG5214
2 1

Do Not Stuff

<Core Design>

1
Wistron Corporation 1

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

DCDC-0D975V_VCCIO
Size Document Number Rev
A3
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 52 of 105

A B C D E
 5 4 3 2 1

Main Func = 1D0V

DCBATOUT PW R_DCBATOUT_1D0V 1D0V_PW R 1D0V_S5

PG5310 PG5305
2 1 2 1

Do Not Stuff
PG5309
Vinafix.com Do Not Stuff
PG5306
2 1 2 1
D D
Do Not Stuff Do Not Stuff
PG5308 PG5307
2 1 2 1
Do Not Stuff Do Not Stuff
PG5304 PG5303
2 1 2 1
Do Not Stuff Do Not Stuff
PG5301
2 1

Do Not Stuff
PG5302
2 1

Do Not Stuff

PW R_DCBATOUT_1D0V

PU5301
MAG. 7*7*3
Design Current =6.4A
DCR: 8.9mOhm 9.6A<OCP<11.52A
1

C PC5301 PC5310 EC5301 C

Idc : 11 A , Isat : 22A
SCD1U25V2KX-GP

3D3V_S5
PR5302
SC10U25V5KX-GP
SC10U25V5KX-GP
2

8 6 PW R_1D0V_BOOT 1 2 PW R_1D0V_BOOT_R 1 2 PC5305 PW R_1D0V_LX

IN BS SCD1U50V3KX-GP 1D0V_PW R

1
PH at Page40 Do Not Stuff
PR5304 DY
Do Not Stuff 10 PW R_1D0V_LX 1 2
LX PL5301
2 68.R681A.10A
IND-D68UH-36-GP-U
[40] 1D0V_S5_PW RGD 1 PR5310 2 PW R_1D0V_PG 2 PG FB 4 PW R_1D0V_FB

1
Do Not Stuff PC5302

PC5307

PC5308

PC5303
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
3D3V_S5

Do Not Stuff
1 PR5308 2 PW R_1D0V_ILMT 3 ILMT BYP 7 DY
Do Not Stuff PR5303

2
1 PW R_1D0V_BYP 1 2
EN

1
Do Not Stuff
9 5 PW R_1D0V_LDO PR5301 PC5306
GND LDO

SC220P50V2KX-3GP
68KR2F-GP
R1

2
SY8208DQNC-GP-U

2
1

1
PR5309 74.08208.K73 PC5304 PC5309
1 DS3 2 PW R_1D0V_EN SC1U10V2KX-1GP

SC2D2U10V3KX-1GP
[17,24,40,54] SIO_SLP_SUS#

2
Do Not Stuff

1
1

PC5311 PR5305
R2
1

PR5311 PR5307 100KR2F-L1-GP

[17,40,45,54] 3V_5V_POK 1NON DS3 2 DY DY Do Not Stuff
B B
Do Not Stuff

0R2J-2-GP
2

2
2

Vo=0.6x(1+R1/R2)
=1.05 V

[#543016] VCCPrim_Core must ramp equal to or before VccPrim_1p0 supply

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L

Inductor: CHIP CHOKE 2.2U PCMC063T-2R2MN 18~20mohm Isat =14Arms 68.2R210.20B
O/P cap: CHIP CAP EL 330U 2.5V M6.3*4.4 3.5Arms Chemi-con/ 79.3371V.6CL
H/S:SIS412DN-T1-GE3 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
L/S:SIS412DN-T1-GE3 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037 <Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DCDC-V1D00A
Size Document Number Rev
A3 Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 53 of 105

5 4 3 2 1
 5 4 3 2 1

Main Func = 1D5V

S-1339D15-M5001 for 1D5V_S0

3D3V_S5
Vinafix.com
D D

Do Not Stuff
PC5408
3234

2
Design Current = 16mA

PU5402 1D5V_PW R 1D5V_S0

PG5404
1 VIN VOUT 5 1 2

PR5405 1
2 VSS3234
[17,24,27,40,51,52] SIO_SLP_S3# 3234 2PW R_1D5V_EN 3 ON/OFF NC#4 4 Do Not Stuff

Do Not Stuff PC5407

PC5409
Do Not Stuff
DY Do Not Stuff
Do Not Stuff 3234

Do Not Stuff
2

2
C C

APL5930 for 1D8V_S5

SC1U10V3KX-4GP-U 5V_S5 3D3V_S5

Design Current = 665mA

3D3V_S5
PC5403

SC10U6D3V3MX-GP
1

1
1

PR5402 PC5401
Do Not Stuff 1D8V_PW R
2

2
PH at Page40
DY PU5401
2

5 1D8V_PW R 1D8V_S5
VIN#5
6 VCNTL VOUT#4 4 PG5405
[40] 1D8V_S5_PW ROK 1 PR5408 2 PW R_1D8V_POK 7 POK VOUT#3 3
Do Not Stuff PW R_1D8V_EN 8 2 1 2
B EN FB B
9 VIN#9 GND 1
PR5406 Do Not Stuff
[17,40,45,53] 3V_5V_POK 1 2 PR5403 PC5405 PG5406
Do Not Stuff
1

1
NON DS3 APL5930KAI-TRG-GP
PC5406

16K5R2F-2-GP

SC68P50V2JN-1GP
0R2J-2-GP
PR5401 DY DY 74.05930.03D DY PC5404 PC5402 1 2
Do Not Stuff
2ND = 74.G9731.03D
2

2
Do Not Stuff

Do Not Stuff

SC22U6D3V3MX-1-GP
1.8V_RUN_FB
[#544669 Rev0.53] PG5407
2

2
PR5407
1 2
[17,24,40,53] SIO_SLP_SUS# 1 2
Do Not Stuff
DS3
Do Not Stuff

1
PR5404
13K3R2F-L1-GP

2 Vout=0.8V*(R1+R2)/R2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LDO-V1D5V&V1D8V
Size Document Number Rev
A3 Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 54 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = LCD LCDVDD_LCD LCDVDD INVERTER POWER Main Func = CAM
R5523
1 2 DCBATOUT DCBATOUT_LCD
LCD1 0R5J-5-GP
41 EE note: Never change R5211 to short pad after MP 800mA
F5503
1 1 2

2 LCDVDD_LCD R5518 C5515

DCBATOUT_LCD

SC1KP50V2KX-1GP
3 DBC_EN_R 1 2 POLYSW-1D1A24V-GP-U C5535S
Trace width = 80mil DBC_PANEL_EN [20]
4 69.50007.A31 EE note: Never change R5229 to short pad after MP

CD1U50V3KX-GP
C5538
5 100R2J-2-GP

2
Reserved for one time fuse: 69.43001.201

2
Vinafix.com
6
7 C5536 3D3V_S0 3D3V_CAMERA_S0
8 DBC_EN_R 3D3V_S0 RN5505

SC1U10V2KX-1GP
2

1
SCD1U16V2KX-3GP
9 EDP_HPD_CONN 2
10 LCD_TST_C 1
DY 3
4
DMIC_PCH_DATA [19]
DMIC_PCH_CLK [19] R5532
D 11 eDP_AUX_CON_P 1 2 D

1
12 eDP_AUX_CON_N ESD A00 Do Not Stuff
13
LCD For ESD R5521 RN5504 0R5J-5-GP

1
14 eDP_TX_CON_N0 10KR2J-3-GP DMIC_DATA_EDP 2 3 DMIC_DATA [27]
15 eDP_TX_CON_P0 DMIC_CLK_EDP 1 4 DMIC_CLK [27] EC5503 DY C5539
16 SC4D7U6D3V3KX-GP

2
R5525

Do Not Stuff
17 eDP_TX_CON_N1 SRN33J-5-GP-U

1
eDP_TX_CON_P1 PANEL_SIZE_ID_CONN PANEL_SIZE_ID
18 1 DY 2 PANEL_SIZE_ID [20]

EC5501

EC5502
19 DY DY

Do Not Stuff

Do Not Stuff
20 LCD_BRIGHTNESS Do Not Stuff For AUDIO Grade B or C selection.

2
1
21 BLON_OUT_C 20140815 david
22 PANEL_SIZE_ID_CONN R5526
LCD_CBL_DET#_R 1 R5539 2
23
Do Not Stuff
LCD_CBL_DET# [20] PU/PD FOR AUX CHANNEL DY Do Not Stuff
24 Layout Note: Reduce the stubs.
25

2
26 MIC_GND SKL PDG (#543016):
27 DMIC_CLK_EDP Recommends having a pull-up resistor of 100 kΩ for AUXN A00
28 DMIC_DATA_EDP
and a pull-down resistor of 100 kΩ for AUXP 69.10103.041-->68.01012.20B & change pin
29
30 USB_CAMERA_PN4 Camera between the AC capacitor and the connector,
31 USB_CAMERA_PP4 to assist source detection by the sink device.
32 3D3V_CAMERA_S0 TR5501
33 USB_CAMERA_PN4 2 1 DCBATOUT_CAMERA DCBATOUT
USB_CPU_PN4 [16]
34 USB_CON_PN6 eDP_AUX_CON_P R5528 1 DY 2 Do Not Stuff
35 USB_CON_PP6 USB_CAMERA_PP4 3 4 USB_CPU_PP4 [16]
eDP_AUX_CON_N R5529 1 2 Do Not Stuff R5501
36
TP_RS
DY 3D3V_S0
FILTER-4P-137-GP 0R3J-0-U-GP
37
38 TP_RESET Touch Panel 1 2
39 68.01012.20B
40 TPAN_VDD

1
Layout Note: RN5502 C5516
42 1 8 BKLT_CTRL C5542 SC1KP50V2KX-1GP
Colse to LCD1. 2 7 BLON_OUT_C SCD1U50V3KX-GP

2
3 6 EDP_HPD IRCCD1
4 5 DCBATOUT_CAMERA
ACES-CON40-18-GP 1 R5531 2 R5524 1 2 Do Not Stuff IR_CAMERA_DET#
Do Not Stuff
DY PEN_CABLE_DET#
1
2 R5540
SRN100KJ-5-GP PEN_SW#
3
20.K0678.040

1
EC5504 EC5505 PEN_DET# IR_CAMERA_DET#_R
D5503 4 1 2 IR_CAMERA_DET# [20]
Do Not Stuff SCD1U25V2KX-GP PEN_LED#3
5
RN5503 1 eDP_BKLT_CTRL DY NC#5
6 100R3J-4-GP
2nd = 20.K0809.040

2
MIC_GND LCD_TST_C GND
C 1 8 LCD_TST [24] 7 C
LCD_BRIGHTNESS BKLT_CTRL GND
2 7 3 8
BLON_OUT_C GND
3 6 PANEL_BKEN_EC [24]
4 5 2 LCD_TST Fo EMI reserved
ACES-CON6-19-GP-U
SRN100J-4-GP
BAT54C-7-F-3-GP EC (BIST MODE)
75.00054.E7D
EDP_HPD_CONN 100R2J-2-GP R5519
1 2 EDP_HPD [8] 2nd = 83.R2003.W81
3rd = 75.00054.A7D
4th = 83.R2003.V81
[8] eDP_TX_CPU_N0 C5508 1 2 SCD1U16V2KX-3GP eDP_TX_CON_N0
3D3V_S0 5V_S0
Main Func = TS
C5532 1 2 SCD1U16V2KX-3GP eDP_TX_CON_P0 TPAN_VDD
[8] eDP_TX_CPU_P0

1
R5522
Do Not Stuff
DY R5527

[8] eDP_TX_CPU_N1 C5534 1 2 SCD1U16V2KX-3GP eDP_TX_CON_N1

Do Not Stuff
Touch Panel
C5537 1 2 SCD1U16V2KX-3GP eDP_TX_CON_P1
[8] eDP_TX_CPU_P1

2
Do Not Stuff R5537
F5502
TPAN_VDD_F 2 Do Not Stuff TP_RS
C5533 eDP_AUX_CON_N
1 DY 1 2 TOUCH_PANEL_INTR# [4,24]
[8] eDP_AUX_CPU_N 1 2 SCD1U16V2KX-3GP

1
[8] eDP_AUX_CPU_P C5531 1 2 SCD1U16V2KX-3GP eDP_AUX_CON_P DY 100R2J-2-GP
R5520 2 1 0R3J-0-U-GP C5541
Do Not Stuff
Brightness

2
1 R5530 2 eDP_BKLT_CTRL EE note: Never change R5232 to short pad after MP
[8] L_BKLT_CTRL Do Not Stuff
Reserved for one time fuse: 69.43001.201 R5538
TP_RESET 1 2 PLT_RST# [17,24,31,40,61,68,73,91]

1
DY 100R2J-2-GP
LCDVDD C5540
Do Not Stuff

2
D5502 A00 Change
[8] EDP_VDD_EN 1

3 LCDVDD_EN USB_CON_PN6 Do Not Stuff 1 2 R5535 USB_CPU_PN6 [16]

B 2 B
[24] LCD_TST_EN
2

3D3V_S0
R5506
BAT54C-7-F-3-GP 100KR2J-1-GP
75.00054.E7D U5501 USB_CON_PP6 Do Not Stuff 1 2 R5536 USB_CPU_PP6 [16]
2nd = 83.R2003.W81 LCDVDD
1

1 5
EN VIN#5
3rd = 75.00054.A7D 2
GND
3 4
VOUT VIN#4
1

4th = 83.R2003.V81 C5505

RT9724GB-GP SC4D7U6D3V3KX-GP
2

Layout Note: 74.09724.09F

Trace width = 80mil

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
LCD&CAM&DMC&Touch
Size Document Number Rev
A2
Loveland SKL-U A00
Date: Friday, September 18, 2015 Sheet 55 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CRT
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 56 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = HDMI

R5401 R5403
HDMI_CLK#_R 1 2 HDMI_CLK#_R_C HDMI_DATA0#_R 1 2 HDMI_DATA0#_R_C

Do Not Stuff Do Not Stuff

1
C5402 1 2 SCD1U16V2KX-3GP HDMI_CLK#_R
[8] HDMI_CLK#
[8] HDMI_CLK
C5403 1 2 Vinafix.com
SCD1U16V2KX-3GP HDMI_CLK_R R5414
150R2J-L1-GP-U
R5417
150R2J-L1-GP-U
C5404 1 2 SCD1U16V2KX-3GP HDMI_DATA0#_R
[8] HDMI_DATA0# C5405 SCD1U16V2KX-3GP HDMI_DATA0_R
D 1 2 D

2
[8] HDMI_DATA0

R5402 R5404
HDMI_CLK_R 1 2 HDMI_CLK_R_C HDMI_DATA0_R 1 2 HDMI_DATA0_R_C
C5406 1 2 SCD1U16V2KX-3GP HDMI_DATA1#_R
[8] HDMI_DATA1# C5407 SCD1U16V2KX-3GP HDMI_DATA1_R Do Not Stuff Do Not Stuff
[8] HDMI_DATA1 1 2

C5408 1 2 SCD1U16V2KX-3GP HDMI_DATA2#_R

[8] HDMI_DATA2# R5405 R5407
C5409 1 2 SCD1U16V2KX-3GP HDMI_DATA2_R
[8] HDMI_DATA2 HDMI_DATA2#_R HDMI_DATA2#_R_C HDMI_DATA1#_R HDMI_DATA1#_R_C
1 2 1 2

Do Not Stuff Do Not Stuff

8
7
6
5

8
7
6
5

1
5V_S0 RN5402 RN5403
SRN470J-3-GP SRN470J-3-GP R5415 R5416
Q5403
150R2J-L1-GP-U 150R2J-L1-GP-U
G

1
2
3
4

1
2
3
4

2
D HDMI_PLL_GND
R5413 R5406 R5408
1 DY 2 S HDMI_DATA2_R 1 2 HDMI_DATA2_R_C HDMI_DATA1_R 1 2 HDMI_DATA1_R_C

2
R5418 Do Not Stuff Do Not Stuff
Do Not Stuff 2N7002K-2-GP Do Not Stuff
DY
84.2N702.J31 HDMI CONN
2ND = 84.2N702.031 5V_S0

1
HDMI1
C 3rd = 84.07002.I31 22 C

3
4th = 84.2N702.W31 20
D5401
BAW 56-9-GP HDMI_DATA2_R_C 1
69.50007.691: 75.00056.07D 2
OBS REASON: Please transfer to down size item 69.48001.081 for cost reduction and good cost down trend HDMI_DATA2#_R_C 3

DDC_CLK_PH1 2

DDC_DATA_PH2 1
HDMI_DATA1_R_C 4
5V_S0 5V_HDMI_R_S0 5V_HDMI_S0 5
F5701 HDMI_DATA1#_R_C 6
HDMI_DATA0_R_C 7
1 R5409 2 1 2 8
Do Not Stuff HDMI_DATA0#_R_C 9
HDMI_CLK_R_C 10
POLYSW -1D1A6V-9-GP-U 11
For DIODE in case of leakage from HDMI1 HDMI_CLK#_R_C 12

4
3
3D3V_S0
69.48001.081 13
14
2ND = 69.50011.081 RN5401 DDC_CLK_HDMI 15
3RD = 69.50013.101 SRN2K2J-1-GP 5V_HDMI_S0 DDC_DATA_HDMI 16
Q5402 17
18

1
2
4 3 DDC_CLK_HDMI 19
[8] CPU_DP1_CTRL_CLK

1
C5401

HPD_HDMI_CON
5 2 21
SCD1U16V2KX-3GP 23
6 1

2
3D3V_S0 SKT-HDMI23-92-GP
B 2N7002KDW -GP 22.10296.981 B
[8] CPU_DP1_CTRL_DATA 84.T3904.H11 R5411 2ND = 22.10296.961

C
DDC_DATA_HDMI 150KR2F-L-GP
Q5401 B HDMI_HPD_B 2 1 3RD = 22.10296.A21
84.2N702.A3F

1
2nd = 84.2N702.E3F LMBT3904LT1G-GP
R5419

E
3rd = 75.00601.07C R5410
4th = 84.DMN66.03F [8] CPU_DP1_HPD 1 2 HDMI_HPD_E 200KR2F-L-GP

1
Do Not Stuff

2
R5412
10KR2J-3-GP
EMI Request:

2
HDMI_DATA1#_R_C HDMI_DATA0#_R_C DDC_CLK_HDMI
HDMI_DATA1_R_C HDMI_DATA0_R_C DDC_DATA_HDMI
HDMI_DATA2#_R_C HDMI_CLK_R_C HPD_HDMI_CON
HDMI_DATA2_R_C HDMI_CLK#_R_C
EU5703
EU5701 EU5702 1 10
1 10 1 10
2 9
2 9 2 9
3
3 3 8
8 8 4
DY 7
4
DY 7 4
DY 7
5 6 <Core Design>
A 5 6 5 6 A

Wistron Corporation
Do Not Stuff 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Do Not Stuff Do Not Stuff Do Not Stuff Taipei Hsien 221, Taiwan, R.O.C.
Do Not Stuff Do Not Stuff Title

HDMI
Size Document Number Rev
A3 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 57 of 105

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 58 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 59 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = HDD

Vinafix.com
E

5V_S0
5V_HDD_S0 SATA HDD Connector E

HDD1
80 mils 1 R6006 2 21
Do Not Stuff 1
22
1

1
C6002 C6001 C6008 C6007 [16] SATA_TX_CPU_P0 SCD22U10V2KX-1GP 2 1 C6005 SATA_TX_CON_P0 2
DY DY [16] SATA_TX_CPU_N0 SCD22U10V2KX-1GP 2 1 C6006 SATA_TX_CON_N0 3
Do Not Stuff

Do Not Stuff

SC10U10V5KX-2GP

SCD1U16V2KX-3GP
4
2

2
SCD22U10V2KX-1GP 1 2 C6004 SATA_RX_CON_N0 5
[16] SATA_RX_CPU_N0 SCD22U10V2KX-1GP 1 SATA_RX_CON_P0
[16] SATA_RX_CPU_P0 2 C6003 6
7
8
D 9 D
HDD_DET# 10
[20] HDD_DET# [67] FFS_INT2_Q 11
12

1
EC6001 5V_HDD_S0 13
Do Not Stuff DY 14
Close to HDD1 15

2
16
17
18
19 23
[67] HDD_DEVSLP 1 R6007 2 HDD_DEVSLP_R 20
Do Not Stuff 24
3D3V_AUX_S5
ACES-CON20-28-GP
C C

20.F2036.020
1

R6003 DY
Do Not Stuff 5V_HDD_S0 1
DCBATOUT AFTP5601 Do Not Stuff
2

5V_HDD_ENABLE# U6001
1

SATA_TX_CON_P0 1 10 SATA_TX_CON_P0
R6002 SATA_TX_CON_N0 LINE_1 NC#10 SATA_TX_CON_N0
DY 5V_S0 5V_HDD_S0 2 LINE_2 NC#9 9
Do Not Stuff
SATA_RX_CON_N0
3 GND DY GND 8
SATA_RX_CON_N0
4 LINE_3 NC#7 7
SATA_RX_CON_P0 5 6 SATA_RX_CON_P0
2

LINE_4 NC#6
6

B Q6001 B
Do Not Stuff U6002
DY Do Not Stuff
Do Not Stuff
1 D DY D 6
2 D D 5
2nd = 084.27002.003F 5V_HDD_ENABLE
1

3 G S 4 Do Not Stuff
3rd = 84.2N702.E3F
Do Not Stuff Layout Note:
C6009 Do Not Stuff Place near HDD1
1

2ND = 84.P2703.03D
Do Not Stuff

R6004 DY
2 DY 1 HDD_PWR_EN_R 3rd = 84.03456.D3D <Core Design>
20,99 HDD_PWR_EN AO6402A MAX 7A
2

Do Not Stuff
1

Rds(on) = 27~40m Ohm

R6005
Do Not Stuff
DY
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
A A
2

Title

SATA HDD
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 60 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = WLAN

DCBATOUT
3D3V_AUX_S5

Vinafix.com

1
1
D
R6103 D
R6102 3D3V_S5 3D3V_S5_W LAN
330KR2J-L1-GP
100KR2J-1-GP

2
2
3.3V_W LAN_ENABLE# U6101
1 D D 6
2 D D 5
3D3V_S5 3.3V_W LAN_ENABLE 3 G S 4

AO6402A-GP
C6113 84.06402.B3D

C6108
Do Not Stuff
2ND = 84.P2703.03D

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1

1
C6107

C6109
C6110
SC470P50V2KX-3GP

C6111
SC470P50V2KX-3GP

C6112
SC10U6D3V3MX-GP
Q6101 3rd = 84.03456.D3D
1

1
2N7002KDW -GP AO6402A MAX 7A DY
DYDoR6105

2
Not Stuff Rds(on) = 27~40m Ohm

2
84.2N702.A3F

SC4700P50V2KX-1GP
1

2
2nd = 75.00601.07C |VGS|max=20V A00 Change
2

R6104
[24] AUX_EN_W OW L 1 2 3.3V_W LAN_EN
Do Not Stuff USB_CON_PP7 Do Not Stuff 2 R6111
1
1 USB_CPU_PP7 [16]
R6101
Do Not Stuff
DY
2

C C
USB_CON_PN7 Do Not Stuff 1 2 R6110 USB_CPU_PN7 [16]
W LAN1

NP2 NP2 NP1 NP1

3D3V_S5_W LAN
76 76 77 77
74 3_3V GND 75
72 3_3V REFCLKN1 73
PCIE_W LAN_W AKE# 1 R6121 2 PCIE_W LAN_W AKE#_R 70 71
Do Not Stuff PEWAKE1#_0/3_3V REFCLKP1
68 CLKREQ1#_0/3_3V GND 69
66 PERST1#_0/3_3V PETN1 67
64 RESERVED#64 PETP1 65
62 ALERT_0/3_3 GND 63
Do Not Stuff TP6103 60 61
E51_RX2 I2C_CLK_0/3_3 PERN1
1 58 I2C_DATA_0/3_3 PERP1 59
[15] W IFI_RF_EN Do Not Stuff 1 2 R6114 W LAN_DISABLE#1 56 57
Do Not Stuff W_DISABLE#1_0/3_3V GND
[20] BLUETOOTH_EN 1 2 R6113 BLUETOOTH_EN_NGFF 54
RESERVED/W_DISABLE#2_0/3_3V PEWAKE0#_0/3_3V 55 PCIE_W LAN_W AKE# [17]
Do Not Stuff 1 2 R6116 PLT_RST_NGFF# 52 53 W LAN_CLKREQ_W LAN# 1 R6112 2
[17,24,31,40,55,68,73,91] PLT_RST# PERST0#_0/3_3V 3.3V CLKREQ0#_0/3_3V CLKREQ_PCIE#1 [18]
50 51 Do Not Stuff
SUSCLK/32KHZ_0/3_3V GND
48 COEX1_0/1_8V REFCLKN0 49 PEG_CLK1_CPU# [18] EMI request
Do Not Stuff TP6102 1 E51_RX1 46 47 PEG_CLK1_CPU [18]
E51_TX1 COEX2_0/1_8V REFCLKP0
44 COEX3_0/1_8V GND 45
R6109 1 DY Do Not Stuff CL_CLK_R

PEG_CLK1_CPU#

PEG_CLK1_CPU
[18] CL_CLK 2 42 CLINK_CLK PETN0 43 PCIE_RX_CPU_N5 [16]
R6119 1 DY 2 Do Not Stuff CL_DATA_R 40 41
[18] CL_DATA CLINK_DATA PETP0 PCIE_RX_CPU_P5 [16]
R6108 1 DY 2 Do Not Stuff CL_RST#_R 38 39
[18] CL_RST# CLINK_RESET GND
36 GND PERN0 37 PCIE_TX_CON_N5 [16]
3160 does not support C-Link 34 DP_ML0P PERP0 35 PCIE_TX_CON_P5 [16]
B B
32 DP_ML0N GND 33
30 GND DP_HPD_0/3_3V 31
28 DP_ML1P GND 29
26 DP_ML1N Module Key DP_ML2P 27
24 GND DP_ML2N 25
22 DP_AUXP GND 23

EC6102
Do Not Stuff

EC6103
Do Not Stuff
20 21
Reserved for NGFF Debug Card DP_AUXN DP_ML3P

1
18 GND DP_ML3N 19
16 LED#2 DP_MLDIR 17 DY DY

2
3D3V_S5 3D3V_S5_W LAN 3D3V_S5_W LAN
Rb 6 LED#1 GND 7
4 5 USB_CON_PN7
3_3V USB_D-
1 R6118 2 2 3_3V USB_D+ 3 USB_CON_PP7
DY Do Not Stuff 1
NGFF_KEY_A 75P GND

[24] HOST_DEBUG_TX 1 R6115 2 E51_TX1

DY Do Not Stuff SKT-MINI67P-12-GP-U
Ra 062.10007.0081
2ND = 62.10043.S31
EE Note:
For NFGG Debug Card: 3RD = 62.10043.N61
Stuff Ra, Rb; DY Rc.

A <Core Design> A

Support: Intel Dual Band Wireless-AC 3160

3D3V_S5_W LAN Wistron Corporation
Do Not Stuff AFTP5801 1
1 W LAN_CLKREQ_W LAN# 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Do Not Stuff AFTP5802 Taipei Hsien 221, Taiwan, R.O.C.
Do Not Stuff AFTP5803 1 W LAN_DISABLE#1
Do Not Stuff AFTP5804 1 BLUETOOTH_EN_NGFF
1 PLT_RST_NGFF# Title
Do Not Stuff AFTP5805
1 USB_CON_PN7
Do Not Stuff
Do Not Stuff
AFTP5806
AFTP5807 1 USB_CON_PP7 NGFF_WLAN CONN
Size Document Number Rev
A3
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 61 of 105
5 4 3 2 1
 A B C D E

Vinafix.com
4 4

3 3

(Blanking)

2 2

<Core Design>

1
Wistron Corporation 1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 62 of 105
A B C D E
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)
Size Document Number Rev
A4 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 63 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Power BTN

Power button PWRBTN

1
G6401 G6402
Do Not Stuff Do Not Stuff PWR1
6
KBC_PWRBTN#_C

2
4
1 2 LID_CLOSE#_C 3
[24] LID_CL_SIO# R6408 1 100R2J-2-GP KBC_PWRBTN#_C
2 2

Vinafix.com

2
[24] KBC_PWRBTN# R6403 100R2J-2-GP

1
AFTP6101 1 1
3D3V_S5 6 5
DY

1
DY ED6401 5
DY EC6401

Do Not Stuff
D D
Do Not Stuff ACES-CON4-39-GP

1
Do Not Stuff

2
C6401 20.K0422.004

1
1 AFTP6102
DY 2nd = 20.K0465.004 For EMI Reserved

2
3rd = 20.K0382.004 LID_CLOSE#_C EC6405 1DY 2 Do Not Stuff PWSW2
Do Not Stuff
Do Not Stuff
2nd = 62.40089.441
3D3V_S5 1 AFTP6103

LID_CLOSE#_C 1 AFTP6104

Main Func = Battery LED

5V_S5

Q6406
Low actived from KBC GPIOQ6403 R2 MASK_BASE_LEDS# MASK_BASE_LEDS# [24]
R6405 E R6407
[24] CHG_AMBER_LED# 1 6 CHG_AMBER_LED#_M 1 2CHG_AMBER_LED_R# B R1
C AMBER_LED_BAT 1 2 BAT_AMBER
MASK_BASE_LEDS# 2 5 MASK_BASE_LEDS# Do Not Stuff
DDTA143ECA-7-F-GP
470R2J-2-GP
3 4
BATT_WHITE_LED# [24] 84.00143.K11

1
2nd = 84.02143.011
DY EC6402
2N7002KDW-GP

Do Not Stuff
2
84.2N702.A3F BAT_AMBER [66]
2nd = 84.2N702.E3F
C BAT_WHITE [66] C
3rd = 75.00601.07C
4th = 84.DMN66.03F 5V_S5
Low actived from KBC GPIO
Q6404 R2
R6404 E R6406
BATT_WHITE_LED#_M 1 2BATT_WHITE_LED_R# B R1
C WHITE_LED_BAT 1 2 BAT_WHITE
Do Not Stuff
DDTA143ECA-7-F-GP
330R2J-3-GP
84.00143.K11

1
2nd = 84.02143.011
DY EC6403

Do Not Stuff
2
Main Func = HDD LED
[16] SATA_LED#
SATA HDD LED
LOW actived from PCH GPIO 5V_S5

SATA_LED#_M S Q6401 R2
E R6401
D SATA_LED#_B B
3D3V_S0 R1
C SATA_LED 1 2
Q6408 SATA_LED_R [66]
MASK_BASE_LEDS# G
B 3D3V_S5 B
1 6 DDTA143ECA-7-F-GP
330R2J-3-GP
84.00143.K11
2 5 Q6402 2nd = 84.02143.011
2N7002K-2-GP R1=R2=4.7K
1

3 4
R6402 84.2N702.J31
2N7002KDW-GP 10KR2J-3-GP
2ND = 84.2N702.031 For EMI Reserved
84.2N702.A3F
2

2nd = 84.2N702.E3F LED_SATA_DIAG_OUT# [24] 3rd = 84.07002.I31 SATA_LED EC6407 1DY 2 Do Not Stuff
3rd = 75.00601.07C
4th = 84.DMN66.03F

Main Func = PWR LED

PWR LED
LOW actived from KBC GPIO
5V_S5

[24] PWR_LED#_S S Q6405 R2

E R6409
D PWR_LED#_B B R1
C PWR_LED 1 2 PWR_LED#_R [66]
MASK_BASE_LEDS# G
DDTA143ECA-7-F-GP
330R2J-3-GP
84.00143.K11
Q6407 2nd = 84.02143.011
2N7002K-2-GP R1=R2=4.7K
A A
84.2N702.J31
2ND = 84.2N702.031
<Core Design>
3rd = 84.07002.I31
For EMI Reserved
Wistron Corporation
PWR_LED EC6406 1DY 2 Do Not Stuff 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LED Board&Power Button

Size Document Number Rev
C
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 64 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = KB Main Func = TPAD

3D3V_S0 3D3V_S5
TP_VDD

Internal Keyboard Connector

2
TP_VDD Discharge Circuit

1
Do Not Stuff R6521
R6520 DY R6522
Do Not Stuff
AFTP6202 KB1 Do Not Stuff
1 DY

1
32 Q6505

1
TP_ON#_GATE

3D3V_TP_S5_R
30 G

2
[20] KB_DET# AFTP6221 KSI7
1 29
KSI6 Q6205_Q

Vinafix.com
AFTP6222 1 28 C6503 DY D
AFTP6230 1 KSI4 27 SCD1U16V2KX-3GP
AFTP6218 1 KSI2 26 1 2 TP_VDD S
R6509
AFTP6214 1 KSI5 25
AFTP6227 1 KSI1 24 1 2 TP_LOCK# Do Not Stuff
D AFTP6234 1 KSI3 23 1KR2J-1-GP Do Not Stuff D
[24] KSI[0..7]

S
AFTP6228 1 KSI0 22 R6516 2ND = 84.2N702.031
KSO5 100KR2J-1-GP
AFTP6215 1 21 [24] TP_EN# 1 2 TP_ON#_GATE G 3rd = 84.07002.I31
AFTP6224 KSO4 4th = 84.2N702.W31
G
[24] KSO[0..16] 1 20
AFTP6213 1 KSO7 19
AFTP6223 1 KSO6 18 Q6504 D
AFTP6231 1 KSO8 17 TP_VDD DMP2130L-7-GP

D
AFTP6208 1 KSO3 16 84.02130.031
AFTP6206 1 KSO1 15 2ND = 84.03413.A31 Precision Touch Pad Connector
AFTP6226 1 KSO2 14
AFTP6207 1 KSO0 13 TP_VDD
AFTP6233 1 KSO12 12 3D3V_S0 TP_VDD
R6517

2
1
AFTP6225 1 KSO16 11 Pin number Pin name
AFTP6229 1 KSO15 10 RN6504 1 2 C6504
AFTP6203 1 KSO13 9 SRN10KJ-5-GP DY 8 VDD
AFTP6216 1 KSO14 8 2 1
AFTP6219 1 KSO9 7 TPAD1 7 DAT(I2C)
AFTP6220 1 KSO11 6 Support PTP Do Not Stuff SCD1U16V2KX-3GP

3
4
AFTP6232 1 KSO10 5 2 1 10 6 CLK(I2C)
CAP_LED 4 20.K0592.030 8
3 SRN33J-5-GP-U R6513 I2C1_SDA_R 7 5 GND
2 2nd = 20.K0621.030 RN6503 1 4 TPCLK_C 4K7R2J-2-GP I2C1_SCL_R 6
PS2 [24] CLK_TP_SIO
[24] DAT_TP_SIO 2 3 TPDATA_C 5 4 ATTN
AFTP6201 1 1 3rd = 20.K0565.030 4
[4,24] INT_TP# TP_LOCK#
31
[24] TP_LOCK#
3 3 GPIO
[20] I2C0_SCL_TCH_PAD R6518 1 DY 2 Do Not Stuff I2C1_SCL_R TPDATA_C 2
R6519 1 DY 2 Do Not Stuff I2C1_SDA_R 2 DAT(PS2)
ACES-CON30-10-GP I2C [20] I2C0_SDA_TCH_PAD
TPCLK_C 1
9 1 CLK(PS2)

EC6501
Do Not Stuff

EC6504
Do Not Stuff

EC6502
Do Not Stuff
1

1
ACES-CON8-40-GP
EC6503 5V_S0
CAP LED Control 5V_S5 Do Not Stuff
DY DY DY DY
1 20.K0667.008

2
Q6502 AFTP6235
LOW actived from KBC GPIO R2
E 2nd = 20.K0665.008
1 R6508 2 CAP_LED_R# B R6506 TP_VDD
[24] CAP_LED#_S Do Not Stuff
R1
CAP_LED_Q CAP_LED
C 1 2

2
DDTA143ECA-7-F-GP 1KR2J-1-GP R6512 Need to check if it is Active High or Active Low
84.00143.K11 Do Not Stuff and check if there is PH on TPAD side.
C 2nd = 84.02143.011 C

2
1
RN6502
For EMI Reserved

1
SRN2K2J-1-GP TP_VDD

CAP_LED#_S EC6507 1 CAP_LED

DY 2 Do Not Stuff AFTP6243 1
TP side has pull high
Q6204_G

3
4
2N7002KDW-GP R6514
2 1 INT_TP#
Keyboard Backlight (Reserved) I2C0_SCL_TCH_PAD 1 6 I2C1_SCL_R
20140820 DAIVD 10KR2J-3-GP
84.2N702.A3F 2 5
EE Note: Never change to short pad after MP 2nd = 84.2N702.E3F
Reserve location for Fuse: 069.50001.0051 3rd = 75.00601.07C 3 4 I2C1_SDA_R
(POLYSW 0603/0.5A/6V) 4th = 84.DMN66.03F
5V_S0 Q6503
+5V_KB_BL TP_VDD 1 AFTP6239
TPCLK_C 1 AFTP6238
I2C0_SDA_TCH_PAD TPDATA_C 1 AFTP6236
1KBBL 2 I2C1_SCL_R 1 AFTP6237
R6504 0R3J-0-U-GP I2C1_SDA_R 1 AFTP6240
1

INT_TP# 1 AFTP6241
KBBLC6501 TP_LOCK# 1 AFTP6242
2

SCD1U16V2KX-3GP
KBLIT1 SMBUS
5
Do Not Stuff 1 2 R6515 I2C1_SCL_R
R6503
1 [12,13,18,66,67,99] PCH_SMBCLK
Do Not Stuff 1
DY I2C1_SDA_R
[12,13,18,66,67,99] PCH_SMBDATA DY 2 R6511
1 KBBL 2 KB_LED_DET_C 2 KBBL
[8] KB_LED_BL_DET
3
1

51KR2J-1-GP 4
1

KB_BL_CTRL#

KBBL 6 Need to check with SW.

EC6505
Do Not Stuff

EC6506
Do Not Stuff
R6507 DY C6502

1
100KR2J-1-GP ACES-CON4-56-GP-U
2

Do Not Stuff

DY DY
2

20.K0800.004 1

2
2ND = 20.K0841.004 AFTP6245
D

B B
KB Backlight Power Consumption: 285mA max. Q6501
DMN3404L-7-GP
KBBL
G
[24] BKLGT_PWM
84.03404.C31
1

DY R6505
Do Not Stuff
+5V_KB_BL 1
KB_LED_DET_C 1 AFTP6248
2

KB_BL_CTRL# 1 AFTP6246
AFTP6247

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Key Board&Touch Pad

Size Document Number Rev
A2 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 65 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = IO Connector

Vinafix.com VGA Connector

D
VGABD1 I/O Board Connector D

17
5V_S0 1

3D3V_S0 2 IOBD1
3 19
4 1
[8] PCH_DPC_N0 5
[8] PCH_DPC_P0 6 2
7 3
[8] PCH_DPC_N1
[8] PCH_DPC_P1
8
9
USB3 (USB2.0) [37]
[37]
USB_PN2_C
USB_PP2_C 4
5
10 6
[8] PCH_DPC_AUXN
[8] PCH_DPC_AUXP
11
12
Cardreader (USB2.0) [33] USB_PN5_C
[33] USB_PP5_C 7
8
13 [20] SD_READ_MODE# 9
[12,13,18,65,67,99] PCH_SMBDATA 14 10
[12,13,18,65,67,99] PCH_SMBCLK 15 USB20_VCCA 11
[8] CPU_DP2_HPD 16 12
18 13
14
HRS-CON16-2-GP 15
16
020.K0032.0016 3D3V_S0
17
18
20

ACES-CON18-2-GP
C C

20.K0707.018

2nd = 20.K0713.018

Pitch: 1mm
Power: 5 pins
GND: 5 pins

USB_PN5_C 1 AFTP6304 Do Not Stuff

USB_PP5_C 1
LED Connector USB_PN2_C
USB_PP2_C
1
1
AFTP6303
AFTP6301
AFTP6302
Do Not Stuff
Do Not Stuff
Do Not Stuff
USB20_VCCA 1 AFTP6311 Do Not Stuff
1 AFTP6314 Do Not Stuff

LEDBD1
7
[64] BAT_AMBER 1
B B

[64] BAT_W HITE 2

[64] SATA_LED_R 3
[64] PW R_LED#_R 4
5
6
8

PTW O-CON6-21-GP

020.K0002.0006
2nd = 20.K0824.006

BAT_AMBER 1 AFTP6308 Do Not Stuff

BAT_W HITE 1 AFTP6307 Do Not Stuff
SATA_LED_R 1 AFTP6306 Do Not Stuff Wistron Confidential document, Anyone can not
PW R_LED#_R 1 AFTP6305 Do Not Stuff Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

IO Board Connector
Size Document Number Rev
A3
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 66 of 105
5 4 3 2 1
 5 4 3 2 1

SSID = User.interface
Free Fall Sensor
3D3V_S0 Vinafix.com
D D

1 R6701 2 3D3V_RUN_FFS
Do Not Stuff

3D3V_S0

C6701

C6703
Do Not Stuff
1

1
C6702
SCD1U16V2KX-3GP

1
SCD1U16V2KX-3GP
DY U6701
R6702

2
DYDo Not Stuff
9 VDD CS 2
5

2
RES
10 VDD_IO
INT1 12 HDD_FALL_INT [18]
INT2 11

[12,13,18,65,66,99] PCH_SMBCLK 1 SCL/SPC

[12,13,18,65,66,99] PCH_SMBDATA 4 SDA/SDI/SDO GND 6
3D3V_RUN_FFS 3 7
C
SDO/SA0 GND
3D3V_S0 GND 8 C

1 LNG2DMTR-GP
R6703 074.LNG2D.00BZ
100KR2J-1-GP
2

FALL_INT2

Q6701
1

5V_S0 2N7002KDW-GP
84.2N702.A3F
2nd = 084.27002.003F 3D3V_S0
3rd = 84.2N702.E3F
1

R6705

1
Do Not Stuff DY
B R6704 B
DYDo Not Stuff
2

2
HDD [60] FFS_INT2_Q FFS_INT2 [20] PCH

1
2 DY
R6706
1
R6707
Do Not Stuff 1MR2J-1-GP

Note

2
- no via, trace, under the sensor (keep out area around 2mm)
- stay away from the screw hole or metal shield soldering joints
- design PCB pad based on our sensor LGA pad size (add 0.1mm) 2014.04.24 Venrer suggest,reserve to prevent error trigger
<Core Design>
- solder stencil opening to 90% of the PCB pad size
- mount the sensor near the center of mass of the NB as possible as you can
A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Note
(1) Keep all signals are the same trace width. (included VDD, GND). Free Fall Sensor
(2) No VIA under IC bottom. Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 67 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Debug

Vinafix.com
D D

Debug Connector
Layout Note:
Place near trace separated point 3D3V_S0
DB1
11
LPC_LAD[3..0] RN6801 1
[18,24] LPC_LAD[3..0]
C Do Not Stuff C
LPC_LAD3 1 8 LPC_LAD3_C LPC_LAD0_C 2
LPC_LAD2 2 7 LPC_LAD2_C LPC_LAD1_C 3
LPC_LAD1 3 LPC 6 LPC_LAD1_C LPC_LAD2_C 4
LPC_LAD0 4 5 LPC_LAD0_C LPC_LAD3_C 5
LPC_FRAME#_DEBUG 6 DY
LPC
1 2 PLT_RST#_DEBUG 7
[18,24] LPC_LFRAME#
[17,24,31,40,55,61,73,91] PLT_RST# R6801 LPC
1 2 Do Not Stuff 8
R6802 Do Not Stuff 9
[18] CLK_PCI_LPC
10
12

Do Not Stuff

Do Not Stuff

B 20.D0075.110: Dummy Pad with solder mask is ZZ.00PAD.Y41 B

DB1 Optional: New one smaller LPC connector is 20.F1180.010.

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Dubug connector
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 68 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 69 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Hall Sensor

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4 A00
Loveland SKL-U
Date: Tuesday, September 15, 2015 Sheet 70 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
RESERVED
Document Number Rev
A4 Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 71 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB3.0 PORT
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 72 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU 3V3_AON_S0

PDP-06877-006

1
R7312 From GPIO21
dGPU Reset GC6_20 Do Not Stuff D7301
R7308 1 GPU_PEX_RST_HOLD [76]
3V3_AON_S0

2
U7301 GPU_PEX_RST# 1 2 GPU_PEX_RST_D# 3 GC6_20
[20] DGPU_HOLD_RST# 1 5
A VCC SYS_PEX_RST_MON#
2
U74LVC1G08G-AL5-R-GP-U Do Not Stuff
[17,24,31,40,55,61,68,91] PLT_RST# 2
B OPS
GC6_20
3
GND Y
4
Vinafix.com SYS_PEX_RST_MON#
To GPIO8
[76] Do Not Stuff
Do Not Stuff 1D05V_VGA_S0
1.05V +/- 30mV
73.01G08.EHG 2nd = 75.00054.R7D

1
2ND = 73.7SZ08.EAH
D
3RD = 73.01G08.L04 R7306 3.3A D

R7304
3rd = 75.BAT54.07D
1 DY 2 Do Not Stuff OPS 100KR2F-L1-GP
4th = 75.00054.Y7D

1
3V3_AON_S0 GPU_PEX_RST# [76]
C7312 OPS C7310 OPS C7323 OPS C7326S OPS

SC1U10V2KX-1GP

SC4D7U6D3V3KX-GP

SC10U6D3V3MX-GP

C22U6D3V3MX-1-GP
2

2
GPU1A 1 OF 14
1/14 PCI_EXPRESS

2
GK208/GF117/GF119
Q7301
R7303 R7313 AB6 NC
PEX_WAKE#
G OPS 10KR2J-3-GP
NON_GC6 PEX_IOVDD
AA22
D SYS_PEX_RST_MON# 1 2 GPU_PEX_RST# AC7 AB23
[18] CLKREQ_PEG#0

1
0R2J-2-GP PEX_RST# PEX_IOVDD
AC24
GPU_CLKREQ# PEX_IOVDD
OPS S AC6
PEX_CLKREQ# PEX_IOVDD
AD25
PEX_IOVDD
AE26 Place close VDD ball Place close Chip
[18] CLK_PCIE_VGA AE8 AE27
2N7002K-2-GP PEX_REFCLK PEX_IOVDD
[18] CLK_PCIE_VGA# AD8
84.2N702.J31 PEX_REFCLK#
C7301 1OPS 2SCD22U10V2KX-1GP dGPU_TXP_CPU_RXP0 AC9
[16] CPU_RXP_C_dGPU_TXP0 PEX_TX0
C7302 1OPS 2SCD22U10V2KX-1GP dGPU_TXN_CPU_RXN0 AB9
[16] CPU_RXN_C_dGPU_TXN0 PEX_TX0#
1 DY 2 [16] dGPU_RXP_C_CPU_TXP0 AG6
PEX_RX0
[16] dGPU_RXN_C_CPU_TXN0 AG7 AA10
R7305 PEX_RX0# PEX_IOVDDQ
AA12
Do Not Stuff C7303 1OPS dGPU_TXP_CPU_RXP1 PEX_IOVDDQ
[16] CPU_RXP_C_dGPU_TXP1 2SCD22U10V2KX-1GP AB10 AA13
C7304 1OPS dGPU_TXN_CPU_RXN1 PEX_TX1 PEX_IOVDDQ
[16] CPU_RXN_C_dGPU_TXN1 2SCD22U10V2KX-1GP AC10 AA16
PEX_TX1# PEX_IOVDDQ
AA18
PEX_IOVDDQ
[16] dGPU_RXP_C_CPU_TXP1 AF7 AA19
PEX_RX1 PEX_IOVDDQ
[16] dGPU_RXN_C_CPU_TXN1 AE7 AA20
PEX_RX1# PEX_IOVDDQ
AA21
C7305 1OPS dGPU_TXP_CPU_RXP2 PEX_IOVDDQ
[16] CPU_RXP_C_dGPU_TXP2 2SCD22U10V2KX-1GP AD11 AB22
C7306 1OPS dGPU_TXN_CPU_RXN2 PEX_TX2 PEX_IOVDDQ
[16] CPU_RXN_C_dGPU_TXN2 2SCD22U10V2KX-1GP AC11 AC23
PEX_TX2# PEX_IOVDDQ
AD24
PEX_IOVDDQ
[16] dGPU_RXP_C_CPU_TXP2 AE9 AE25
PEX_RX2 PEX_IOVDDQ
[16] dGPU_RXN_C_CPU_TXN2 AF9 AF26
PEX_RX2# PEX_IOVDDQ
AF27
C7307 1OPS dGPU_TXP_CPU_RXP3 PEX_IOVDDQ
C
[16] CPU_RXP_C_dGPU_TXP3 2SCD22U10V2KX-1GP AC12 C
C7308 1OPS dGPU_TXN_CPU_RXN3 PEX_TX3
[16] CPU_RXN_C_dGPU_TXN3 2SCD22U10V2KX-1GP AB12
PEX_TX3#

[16] dGPU_RXP_C_CPU_TXP3 AG9

PEX_RX3
[16] dGPU_RXN_C_CPU_TXN3 AG10
PEX_RX3#
AB13
PEX_TX4
AC13
PEX_TX4#
AF10
PEX_RX4
AE10
PEX_RX4# 3.3V +/- 5%
3V3_AON_S0
AD14
AC14
PEX_TX5
AA8
210mA
PEX_TX5# PEX_PLL_HVDD
AA9
PEX_PLL_HVDD
AE12
PEX_RX5
AF12
PEX_RX5#
AB8
PEX_SVDD_3V3
AC15
PEX_TX6
AB15 Place close Chip

1
PEX_TX6# C7316 C7315 OPS
C7324 OPS
OPS

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
AG12

SCD1U25V2KX-GP
GPIO51(PCH) PEX_RX6
GPIO5 AG13

2
PEX_RX6#
AB16
PEX_TX7
AC16
PEX_TX7#
AF13
PEX_RX7
GPIO0 AE13
PEX_RX7#
AD17 NC
PEX_TX8
AC17 NC
PEX_TX8#
AE15 NC
PEX_RX8
AF15 NC
PEX_RX8#
GPIO45 (PCH) AC18
PEX_TX9 NC VDD_SENSE
F2 VGACORE_VDD_SENSE_1 [82]
AB18
GPIO96(KBC) PEX_TX9# NC
POWER IC
AG15 NC F1 VGACORE_GND_SENSE_1 [82]
PEX_RX9 GND_SENSE
AG16 NC
B GPIO51(KBC) PEX_RX9# B
GPIO47 (PCH)
GPIO6 AB19 NC
PEX_TX10
AC19 NC
PEX_TX10#
GPIO54(PCH) AF16
PEX_RX10 NC
AE16 NC
PEX_RX10#
GPIO8
AD20 NC
PEX_TX11
AC20 NC
PEX_TX11#
GPIO21
AE18 NC
PEX_RX11
AF18 NC
PEX_RX11#
AC21 NC
PEX_TX12 R7307
AB21 NC
PEX_TX12# Do Not Stuff
AG18 NC AF22 PEXTSTCLK_OUT 1 DY 2
PEX_RX12 PEX_TSTCLK_OUT
AG19 NC AE22 PEXTSTCLK_OUT# L7301
PEX_RX12# PEX_TSTCLK_OUT#
AD23 1D05V_VGA_S0
AE23
PEX_TX13 NC
NC Place close VDD ball Place close Chip MHC1608S121PBP-GP 1.05V +/- 30mV
PEX_TX13#
OPS 150mA
AF19 NC AA14 VCC1R05VIDEO_PEX_PLLVDD 1 2
PEX_RX13 PEX_PLLVDD
PEX_RST# AE19
PEX_RX13# NC PEX_PLLVDD
AA15 68.00335.151
AF24 NC C7318

1
PEX_TX14 C7317 C7319
AE24
PEX_TX14# NC OPS OPS OPS

SC4D7U6D3V3KX-GP

SC1U10V2KX-1GP
SCD1U16V2KX-3GP
AE21 NC

2
PEX_RX14 R7302
AF21 NC
PEX_RX14#
AD9 TESTMODE 1 OPS 2
TESTMODE 10KR2F-2-GP
AG24 NC
PEX_TX15
AG25 NC
PEX_TX15#
AG21 NC
PEX_RX15
AG22 NC
PEX_RX15#
OPS R7301
GF119 GF117
GK208 AF25 PEX_TERMP 1 OPS 2
PEX_TERMP 2K49R2F-GP
A N14M-GE-S-A2-GP A

71.0N14M.B0U

<Core Design>
N15V-GM-S-A2: JG0YH
N16V-GM is 071.0N16V.000U Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU(1/5)PEG
Size Document Number Rev
A2
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 73 of 105

5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU

GPU1I 9 OF 14
6/14 IFPD

LVDS Interface U6
GF119/GK208

IFPD_RSET
GF117

NC
GF117 GF119/GK208

DVI/HDMI DP
GPU1G
Vinafix.com
7 OF 14 GM108
4/14 IFPAB GM108 IFPC_PLLVDD T7 NC NC I2CX_SDA P4
IFPD_PLLVDD IFPD_AUX_I2CX_SDA#
NC I2CX_SCL IFPD_AUX_I2CX_SCL P3
GF117 GF119/GK208
R7 IFPD_PLLVDD NC
D GM108 NC IFPA_TXC# AC4 D
NC IFPA_TXC AC3 NC TXC IFPD_L3# R5
GF119/GK208 GF117 R4
NC TXC IFPD_L3
AA6 IFPAB_RSET NC
NC IFPA_TXD0# Y3 NC TXD0 IFPD_L2# T5
NC IFPA_TXD0 Y4 NC TXD0 IFPD_L2 T4

IFPAB_PLLVDD V7 NC NC TXD1 U4
IFPAB_PLLVDD IFPD IFPD_L1#
NC AA2 NC TXD1 U3
IFPA_TXD1# IFPD_L1
W7 IFPAB_PLLVDD NC NC IFPA_TXD1 AA3
NC TXD2 IFPD_L0# V4
NC TXD2 IFPD_L0 V3
NC AA1
IFPA_TXD2#
NC IFPA_TXD2 AB1
GM108
IFPC_IOVDD R6 NC NC D4
IFPD_IOVDD GPIO17
NC AA5
IFPA_TXD3#
NC AA4 GF119/GK208 GF117

4
3
IFPA_TXD3
RN7401
NC IFPB_TXC# AB4 Do Not Stuff
GM108 NC IFPB_TXC AB5 DY N14M-GE-S-A2-GP
GF119/GK208 GF117
71.0N14M.B0U

1
2
IFPAB_IOVDD W6 NC NC AB2
IFPA_IOVDD IFPB_TXD4#
NC IFPB_TXD4 AB3
Y6
IFPB_IOVDD NC OPS
NC AD2
IFPB_TXD5#
NC IFPB_TXD5 AD3
4
3

C RN7402 GPU1J 10 OF 14 C
DY Do Not Stuff NC IFPB_TXD6# AD1 7/14 IFPEF
NC IFPB_TXD6 AE1
GF119/GK208
GF117
GM108
1
2

GM108 DVI-DL DVI-SL/HDMI DP

NC AD5
IFPB_TXD7# GF117
NC IFPB_TXD7 AD4 GF119 GK208 NC I2CY_SDA I2CY_SDA IFPE_AUX_I2CY_SDA# J3
NC I2CY_SCL I2CY_SCL IFPE_AUX_I2CY_SCL J2
IFPEF_PLLVDD J7 NC
IFPEF_PLLVDD

NC TXC TXC J1
IFPE_L3#
GM108 NC TXC TXC IFPE_L3 K1
NC B3 K7 NC
GPIO14 IFPEF_PLLVDD
IFPAB NC TXD0 TXD0 IFPE_L2# K3
K2
NC TXD0 TXD0 IFPE_L2
N14M-GE-S-A2-GP
71.0N14M.B0U K6
IFPEF_RSET NC NC TXD1 TXD1 IFPE_L1#
M3
NC TXD1 TXD1 IFPE_L1 M2

OPS NC TXD2 TXD2 IFPE_L0# M1

NC TXD2 TXD2 IFPE_L0 N1

HDMI Interface IFPE NC FOR GK208

GM108
GPU1H 8 OF 14 NC HPD_E C2
HPD_E GPIO18
5/14 IFPC GM108
IFPC
GF119/GK208 GF117 GM108 GF117
GF119 GK208
T6 IFPC_RSET NC GF117 GF119/GK208
B IFPEF_IOVDD H6 B
IFPE_IOVDD NC
DVI/HDMI DP GF119/GK208
GF117
J6 IFPF_IOVDD NC DVI-DL DVI-SL/HDMI DP
IFPD_PLLVDD GM108
M7 IFPC_PLLVDD NC NC I2CW_SDA IFPC_AUX_I2CW_SDA# N5
N7 IFPC_PLLVDD NC NC I2CW_SCL IFPC_AUX_I2CW_SCL N4 NC I2CZ_SDA IFPF_AUX_I2CZ_SDA# H4
NC I2CZ_SCL IFPF_AUX_I2CZ_SCL H3

NC TXC IFPC_L3# N3
NC TXC N2 NC TXC J5
IFPC_L3 IFPF_L3#
NC TXC J4
IFPF_L3
4
3

NC TXD0 R3
IFPC_L2# RN7403
NC TXD0 IFPC_L2 R2 NC TXD3 TXD0 IFPF_L2# K5
DY Do Not Stuff NC TXD3 TXD0 IFPF_L2 K4
NC TXD1 IFPC_L1# R1
NC TXD1 IFPC_L1 T1 NC TXD4 TXD1 IFPF_L1# L4
IFPF NC TXD4 TXD1 L3
1
2

IFPF_L1
NC TXD2 IFPC_L0# T3
NC TXD2 IFPC_L0 T2 NC TXD5 TXD2 IFPF_L0# M5
NC TXD5 TXD2 M4
IFPF_L0
GM108
IFPD_IOVDD NC FOR GK208
P6 NC NC C3
IFPC_IOVDD GPIO15 GF117 GM108
NC HPD_F F7
N14M-GE-S-A2-GP GPIO19
4
3

RN7404
71.0N14M.B0U
DY Do Not Stuff
OPS
N14M-GE-S-A2-GP
71.0N14M.B0U
1
2

A A
<Core Design>
OPS
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU(2/5)DIGITALOUT
Size Document Number Rev
Custom
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 74 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU

R7519
DY 1.35V +/- 3%
1 2 GC6_FB_EN [20,76,83]
GPU1B Do Not Stuff 1D35V_VGA_S0
[78] FBA_D[0..31] 2 OF 14 4.88A
R7518 Under GPU
2/14 FBA
FBA_D0 FB_CLAM 4 OF 14 GPU1D
FBA_D1
E18
FBA_D0 NC FB_CLAMP
F3 1 OPS 2 Near GPU
F18 12/14 FBVDDQ
FBA_D2 FBA_D1
E16
FBA_D3 F17
FBA_D2
FBA_D3
GF119 GF117/GK208 10KR2J-3-GP
FBVDDQ
B26 A00 08.10
FBA_D4 D20 C25 C7501 C7502 C7525 C7507 C7513 C7514 C7517 C7520
FBA_D4 FBVDDQ

1
SC10U10V5KX-2GP
FBA_D5 D21 E23 OPS OPS OPS OPS OPS OPS OPS OPS

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
Vinafix.com
FBA_D5 FBVDDQ

SC22U6D3V3MX-1-GP
FBA_D6 F20 E26

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SC1U10V3KX-4GP-U

SC1U10V3KX-4GP-U
FBA_D7 FBA_D6 FBVDDQ
E21 F14

2
FBA_D8 FBA_D7 FBVDDQ
E15 F21
FBA_D9 FBA_D8 FBVDDQ
D15 G13
FBA_D10 FBA_D9 FBVDDQ
F15 G14
FBA_D11 FBA_D10 FBVDDQ
F13 G15
FBA_D12 FBA_D11 FBVDDQ
C13 G16
D FBA_D13 FBA_D12 FBVDDQ D
B13 G18
FBA_D14 FBA_D13 FBVDDQ
E13 G19
FBA_D15 FBA_D14 FBVDDQ
D13 G20
FBA_D16 FBA_D15 FBVDDQ
B15 G21
FBA_D17 FBA_D16 GM108 FBVDDQ
C16 FBVDDQ_AON FBVDDQ H24
FBA_D18 FBA_D17
A13 FBVDDQ_AON FBVDDQ H26
FBA_D19 FBA_D18
A15 FBVDDQ_AON FBVDDQ J21
FBA_D20 FBA_D19
B18 FBVDDQ_AON FBVDDQ K21
FBA_D21 FBA_D20
A18 L22
FBA_D22 FBA_D21 FBVDDQ
A19 L24
FBA_D23 FBA_D22 FBVDDQ
C19 L26
FBA_D24 FBA_D23 FBVDDQ
B24 M21
FBA_D25 FBA_D24 FBVDDQ
C23 N21
FBA_D26 FBA_D25 FBVDDQ
A25 R21
FBA_D27 FBA_D26 FBVDDQ
A24 T21
FBA_D28 FBA_D27 FBVDDQ
A21 V21
FBA_D29 FBA_D28 FBVDDQ
B21 W21
FBA_D30 FBA_D29 FBVDDQ
C20
FBA_D31 FBA_D30
[79] FBA_D[32..63] C21
FBA_D32 FBA_D31
R22
FBA_D33 FBA_D32 FBA_CMD0
R24 C27 FBA_CMD0 [78]
FBA_D34 FBA_D33 FBA_CMD0 FBA_CMD1 TP7501 Do Not Stuff
T22 C26 1
FBA_D35 FBA_D34 FBA_CMD1 FBA_CMD2
R23 E24 FBA_CMD2 [78]
FBA_D36 FBA_D35 FBA_CMD2 FBA_CMD3
N25 F24 FBA_CMD3 [78]
FBA_D37 FBA_D36 FBA_CMD3 FBA_CMD4
N26 D27 FBA_CMD4 [78,79]
FBA_D38 FBA_D37 FBA_CMD4 FBA_CMD5
N23 D26 FBA_CMD5 [78,79]
FBA_D39 FBA_D38 FBA_CMD5 FBA_CMD6
N24 F25 FBA_CMD6 [78,79]
FBA_D40 FBA_D39 FBA_CMD6 FBA_CMD7
V23 F26 FBA_CMD7 [78,79]
FBA_D41 FBA_D40 FBA_CMD7 FBA_CMD8
V22 F23 FBA_CMD8 [78,79]
FBA_D42 FBA_D41 FBA_CMD8 FBA_CMD9
T23 G22 FBA_CMD9 [78,79]
FBA_D43 FBA_D42 FBA_CMD9 FBA_CMD10
U22 G23 FBA_CMD10 [78,79]
FBA_D44 FBA_D43 FBA_CMD10 FBA_CMD11
Y24 G24 FBA_CMD11 [78,79]
FBA_D45 FBA_D44 FBA_CMD11 FBA_CMD12
AA24 F27 FBA_CMD12 [78,79]
FBA_D46 FBA_D45 FBA_CMD12 FBA_CMD13
Y22 G25 FBA_CMD13 [78,79]
FBA_D47 FBA_D46 FBA_CMD13 FBA_CMD14 TP7502 Do Not Stuff
AA23 G27 1
FBA_D48 FBA_D47 FBA_CMD14 FBA_CMD15
AD27 G26 FBA_CMD15 [78,79]
FBA_D49 FBA_D48 FBA_CMD15 FBA_CMD16
AB25 M24 FBA_CMD16 [79]
FBA_D50 FBA_D49 FBA_CMD16 FBA_CMD17 TP7505 Do Not Stuff
AD26 M23 1 1D35V_VGA_S0
FBA_D51 FBA_D50 FBA_CMD17 FBA_CMD18
AC25 K24 FBA_CMD18 [79]
FBA_D52 FBA_D51 FBA_CMD18 FBA_CMD19
AA27 K23 FBA_CMD19 [79] Under GPU
FBA_D53 FBA_D52 FBA_CMD19 FBA_CMD20
AA26 M27 FBA_CMD20 [78,79]
FBA_D54 FBA_D53 FBA_CMD20 FBA_CMD21 R7505
W26 M26 FBA_CMD21 [78,79]
FBA_D55 FBA_D54 FBA_CMD21 FBA_CMD22 FB_CAL_PD_VDDQ
FBA_D56
Y25
FBA_D55 FBA_CMD22
M25
FBA_CMD23
FBA_CMD22 [78,79] 2 OPS 1 D22
FB_CAL_PD_VDDQ
R26 K26 FBA_CMD23 [78,79]
FBA_D57 FBA_D56 FBA_CMD23 FBA_CMD24 40D2R2F-GP
T25 K22 FBA_CMD24 [78,79]
FBA_D58 FBA_D57 FBA_CMD24 FBA_CMD25 FB_CAL_PU_GND
N27 J23 FBA_CMD25 [78,79] C24
FBA_D59 FBA_D58 FBA_CMD25 FBA_CMD26 FB_CAL_PU_GND
R27 J25 FBA_CMD26 [78,79]
FBA_D60 FBA_D59 FBA_CMD26 FBA_CMD27
V26 J24 FBA_CMD27 [78,79]
FBA_D61 FBA_D60 FBA_CMD27 FBA_CMD28 FB_CAL_TERM_GND
V27 K27 FBA_CMD28 [78,79] B25
FBA_D62 FBA_D61 FBA_CMD28 FBA_CMD29 FB_CAL_TERM_GND
W27 K25 FBA_CMD29 [78,79]
FBA_D63 FBA_D62 FBA_CMD29 FBA_CMD30
W25 J27 FBA_CMD30 [78,79]
FBA_D63 FBA_CMD30 N14M-GE-S-A2-GP
J26
FBA_CMD31
FBA_DQM0 FBA_CMD31 TP7504 Do Not Stuff
71.0N14M.B0U
D19 1
FBA_DQM0

1
[78] FBA_DQM0 FBA_DQM1 D14
[78] FBA_DQM1 FBA_DQM1 1D35V_VGA_S0
[78] FBA_DQM2
FBA_DQM2 C17
FBA_DQM2
R7507 R7506 OPS
FBA_DQM3 C22 OPS OPS

51D1R2F-GP
42D2R2F-GP
[78] FBA_DQM3 FBA_DQM4 FBA_DQM3
P24
C [79] FBA_DQM4 FBA_DQM5 FBA_DQM4 C
W24

2
[79] FBA_DQM5 FBA_DQM6 FBA_DQM5
AA25
[79] FBA_DQM6 FBA_DQM7 FBA_DQM6 GM108 FBA_DEBUG0 R7501 1
U25 F22 DY 2 Do Not Stuff
[79] FBA_DQM7 FBA_DQM7 FBA_CMD34 FBA_DEBUG0
FBA_DEBUG1 R7503 1
FBA_CMD35 FBA_DEBUG1 J22 DY 2 Do Not Stuff

FBA_EDC0 E19
[78] FBA_EDC0 FBA_EDC1 FBA_DQS_WP0
C15
[78] FBA_EDC1 FBA_EDC2 FBA_DQS_WP1 FBA_CLK0P
B16 D24 FBA_CLK0P [78]
[78] FBA_EDC2 FBA_EDC3 FBA_DQS_WP2 FBA_CLK0 FBA_CLK0N
B22 D25 FBA_CLK0N [78]
[78] FBA_EDC3 FBA_EDC4 FBA_DQS_WP3 FBA_CLK0# FBA_CLK1P
R25 N22 FBA_CLK1P [79]
[79] FBA_EDC4 FBA_EDC5 FBA_DQS_WP4 FBA_CLK1 FBA_CLK1N
W23 M22 FBA_CLK1N [79]
[79] FBA_EDC5 FBA_EDC6 FBA_DQS_WP5 FBA_CLK1#
AB26
[79] FBA_EDC6 FBA_EDC7 FBA_DQS_WP6
T26
[79] FBA_EDC7 FBA_DQS_WP7

F19 D18
[78] FBA_DQS_RN0 FBA_DQS_RN0 FBA_WCK01
C14 C18
[78] FBA_DQS_RN1 FBA_DQS_RN1 FBA_WCK01#
A16 D17
[78] FBA_DQS_RN2 FBA_DQS_RN2 FBA_WCK23
A22 D16
[78] FBA_DQS_RN3 FBA_DQS_RN3 FBA_WCK23#
P25 T24
[79] FBA_DQS_RN4 FBA_DQS_RN4 FBA_WCK45
W22 U24
[79] FBA_DQS_RN5 FBA_DQS_RN5 FBA_WCK45#
AB27 V24
[79] FBA_DQS_RN6 FBA_DQS_RN6 FBA_WCK67
T27 V25
[79] FBA_DQS_RN7 FBA_DQS_RN7 FBA_WCK67#

F16
62mA
FB_PLLAVDD 1D05V_VGA_S0
Under GPU Near GPU FBA_CMD0
P22 FBA_CMD16
FB_PLLAVDD L7501
FBA_CMD3
FB_PLLAVDD H22
35mA FBA_PLL_AVDD 1 2 FBA_CMD19
FB_DLLAVDD FBA_CMD20
OPS
GF117 GF119/GK208 MHC1608S300QBP-GP
C7505 C7506 C7518
1

OPS OPS OPS 68.00335.051

SC22U6D3V3MX-1-GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

2nd = 68.00334.051
2

1
R7508 R7509 R7510 R7511 R7512
30ohm@100MHZ(ESR=0.01ohm)

10KR2F-2-GP

10KR2F-2-GP

10KR2F-2-GP

10KR2F-2-GP

10KR2F-2-GP
TP7503 1 FB_VREF D23 OPS OPS OPS OPS OPS
FB_VREF_PROBE

<DUMMY>

2
N14M-GE-S-A2-GP Sourcer suggest to change to
71.0N14M.B0U 68.00335.051 from 68.00084.H41.

OPS

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU(3/5)VRAMI/F
Size Document Number Rev
A1
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 75 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU

30ohm@100MHz
1D05V_VGA_S0 DCR=0.04 ohm
3V3_AON_S0 Max current = 3000mA
GPU1K 11 OF 14
3/14 DACA GM108 GM108
L7601 52mA
1 2
GF119/GK208 GF117 GF117 GF119/GK208 RN7603 OPS

SCD1U16V2KX-3GP
W5 B7 I2CA_SCL 3 2 C7605
NC NC

1
DACA_VDD I2CA_SCL I2CA_SDA MHC1608S300QBP-GP C7606 GPU1M 13 OF 14
NC A7 4 1 OPS
AE2
I2CA_SDA DY 68.00335.051 OPS SC2D2U10V2KX-GP 9/14 XTAL_PLL 3V3_AON_S0
DACA_VREF TSEN_VREF NC
Do Not Stuff 2nd = 68.00334.051

2
AF2 AE3 GPU_PLL_VDD L6
DACA_RSET NC NC DACA_HSYNC CORE_PLLVDD
AE4 L7602 SP_PLLVDD M6
NC 111mA

1
DACA_VSYNC MCB1608S181FBP-GP SP_PLLVDD R7617
1 OPS 2 N6 NC
Do Not Stuff
VID_PLLVDD
NC DACA_RED
AG3 N6:On co-layout designs, DY
AF4
Vinafix.com 68.00909.261 this ball can be connected
to power rail filter.
GF119/GK208 GF117

2
NC DACA_GREEN
180ohm@100MHz C7601 C7604 C7602

1
AF3 C7603 OPS
NC DACA_BLUE DCR=0.3 ohm

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
OPS DY OPS VIDEO_CLK_XTAL_SS A10 C10 N12P_XTAL_OUTBUFF
Max current = 300mA XTAL_SSIN XTAL_OUTBUFF

2
SC10U6D3V3MX-GP
PDP-06877-006

Do Not Stuff
D D
C11 B10
N14M-GE-S-A2-GP XTAL_IN XTAL_OUT

1
71.0N14M.B0U N14M-GE-S-A2-GP R7602

1
71.0N14M.B0U 20PF 5% 50V +/-0.25PF 0402 10KR2J-3-GP
OPS
OPS OPS R7601 R7603
10KR2J-3-GP OPS Do Not Stuff

2
27MHZ_IN 1 DY 2 27MHZ_OUT

2
X7601

2
1 4 OPS
R7604 1K3R2J-GP

1
2 3 27MHZ_OUT_R GM:
OPS C7607 = 78.15034.1FL

2
C7608 = 78.15034.1FL
C7607 C7608
SC18P50V2JN-1-GP SC18P50V2JN-1-GP
R7604 = 63.13234.1DL

Straps

1
OPS XTAL-27MHZ-85-GP-U OPS
82.30034.641
2ND = 82.30034.651
3RD = 82.30034.681 3V3_AON_S0

(DG-07158-001)

1
R7613
Do Not Stuff R7645
1 2 OPS 10KR2J-3-GP
[73] GPU_PEX_RST#
DY

2
R7656
1 VIDEO_THERM_OVERT# OVERT# 1 OPS 2 OVERT_GPU#
TP7606
0R2J-2-GP

1
VGA_CORE IC not support ALERT#.
84.2N702.A3F OPS C7609

4
2nd = 84.2N702.E3F SC2700P50V2KX-1-GP

2
Q7602 3rd = 75.00601.07C
2N7002KDW-GP 4th = 84.DMN66.03F
OPS

3
R7653
GPU1N 14 OF 14 3V3_AON_S0 P_H_S#
GPIO9_ALERT
1 DY 2 PURE_HW_SHUTDOWN# [26,40]
8/14 MISC1

1
D9 SMBC_THERM_NV Do Not Stuff
I2CS_SCL SMBD_THERM_NV R7612
D8 DY C7610
I2CS_SDA Do Not Stuff
1 2 3V3_AON_S0

2
C A9 I2CC_SCL 4 1 RN7604 OPS C
I2CC_SCL
B9 I2CC_SDA 3 DY 2 Do Not Stuff
I2CC_SDA 10KR2J-3-GP 3V3_AON_S0
GF119 3V3_AON_S0
P2800_VGA_DXN GF117 GK208
1 E12
TP7603 THERMDN I2CB_SCL 3V3_AON_S0
NC C9 3 2 RN7605
I2CB_SCL
1 P2800_VGA_DXP F12 NC C8 I2CB_SDA 4 DY 1 Do Not Stuff R7657
THERMDP I2CB_SDA

1
TP7604

4
3
R7633 1 OPS 2 Q7601_G
N12P_JTAG_TCK AE5 GC6_20 Do Not Stuff
N12P_JTAG_TMS JTAG_TCK 0R2J-2-GP RN7601
1 AD6
TP7602 N12P_JTAG_TDI JTAG_TMS
1 AE6 OPS SRN4K7J-8-GP

2
TP7605 N12P_JTAG_TDO JTAG_TDI
1 AF6
TP7601 N12P_JTAG_TRST JTAG_TDO GC6_FB_EN_GPU GPIO5_GC6_PWR_EN_GPU
AG4 C6 Q7601

1
2
JTAG_TRST# (GC6_FB_EN/FB_CLAMP_MON) GPIO0
GPIO1
B2 3V3_MAIN_EN is an open-drain GPIO.
D6 3 4 SMBD_THERM_NV
GPIO2 [18,24,26] SML1_SMBDATA
3
4

C7 3V3_AON_S0
RN7602 GPIO3 R7636
F9 2 5
GPIO4 GPIO5_GC6_PWR_EN_GPU NPN-07376
SRN10KJ-5-GP (3V3_MAIN_EN) GPIO5 A3 1 2 GPIO5_GC6_PWR_EN [83]
OPS A4 GPU_EVENT_GPU# Do Not Stuff Do Not Stuff 1 6
(GPU_EVENT#/FB_CLAMP_TGL_REQ#) GPIO6

1
GK208 GPIO7
B6 GC6_20 2ND = 83.27101.01F
OVERT A6 OVERT_GPU# R7605 3RD = 83.01426.01F 2N7002KDW-GP
2
1

GPIO8 GPIO9_ALERT 100KR2J-1-GP

GPIO9
F8
GPIO10_FBVREF
OPS OPS
C5
GPIO10
E7 D7601

2
GPIO11 PWR_LEVEL VGA_CORE_VID [82] SMBC_THERM_NV
D7 A K AC_PRESENT [17]
GPIO12
GPIO13
B4 VGA_CORE_PSI [82] DY [18,24,26] SML1_SMBCLK
Do Not Stuff 84.2N702.A3F
R7631 Do Not Stuff 2nd = 84.2N702.E3F
GK208 GF117 GF119
3V3_AON_S0 1 2 D7602 3rd = 75.00601.07C
GPIO16 NC GPIO16
D5 GC6_20 A K OVER_CURRENT_P8# [24] 4th = 84.DMN66.03F
GPIO20 NC GPIO20
E6
GPU_PEX_RST_HOLD_GPU# 1
GC6_20 OPS
GPIO8 NC C4 2 R7630 GPU_PEX_RST_HOLD [73] 1SS400GPT-GP
GPIO21 Do Not Stuff 83.00400.C1F
GM108 DA-05691-001_V05 P15
2ND = 83.27101.01F
GPIO20/21 NC : for ALL
3RD = 83.01426.01F
N14M-GE-S-A2-GP
71.0N14M.B0U

OPS 3D3V_VGA_S0
GPIO10_FBVREF
GPU1L 12 OF 14
2

10/14 MISC2
1

R7626
GF117/GF119/GK208 DY Do Not Stuff R7610
OPS 100KR2J-1-GP
E10 NC
1

VMON_IN0
F10 D12 ROM_CS#
2

VMON_IN1 NC ROM_CS#
B12 ROM_SI
ROM_SI
A12 ROM_SO 3V3_AON_S0
STRAP0 ROM_SO
B D1 C12 ROM_SCLK B
STRAP1 STRAP0 ROM_SCLK
D2
STRAP2 STRAP1
E4
STRAP3 STRAP2
E3
STRAP3
2

STRAP4 D3
STRAP4 R7643
GF119 GF117 DY Do Not Stuff
GK208
R7628
C1 NC
1

STRAP5
R7607 D11 BUFRST# 2 OPS 1
40K2R2F-GP BUFRST# SYS_PEX_RST_MON_GPU#
1 2 STRAP_REF0_GND_N9 F6 NC D10 10KR2J-3-GP
MULTI_STRAP_REF0_GND PGOOD
N16V-GM
GF117 GF117
GF119 GF119
N15V-GS supports Binary Mode. GK208 GK208 R7629
N16V-GM supports Multi-Level Strap. F4
MULTI_STRAP_REF1_GND NC
GPIO8 SYS_PEX_RST_MON_GPU#
GC6_20
NC E9 1 2
CEC Do Not Stuff SYS_PEX_RST_MON# [73]
F5
MULTI_STRAP_REF2_GND NC GF117 GM108 R7619,R7638,R7642,R7616,R7640,R7655 for N16V-GM 4 pcs VRAM
GK208
GF119 Connect to SYS_PEX_RST_MON# 3V3_AON_S0
Multi Strap:RAM_CFG[3:0]
N14M-GE-S-A2-GP if GC62.0 is implemented. N15V-GM-S: Binary Strap for VRAMs.
3D3V_VGA_S0
Leave NC for GC6 1.0. 3V3_AON_S0

N16_Micron2G4G

N16_Samsung4G
71.0N14M.B0U
N16_Micron1G

N16V-GM/N15_Samsung&Hynix&Hynix2G&Micron2G
N16_Hynix1G
4K99R2F-L-GP

4K99R2F-L-GP

1
OPS
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
1

45K3R2F-L-GP
R7606 R7615 R7634

Do Not Stuff
1
R7608

R7611

R7616

R7638

R7639
10KR2F-2-GP Do Not Stuff

R7625
DY Do Not Stuff N15_Micron&Micron2G&Samsung2G
1

1
3V3_AON_S0 3D3V_S0
R7640

N16V-GM N16V-GM N15_Hynix&Micron2G&Samsung&Samsung2G

1
R7646
2
N16V-GM R7635
2

2
2

3V3_AON_S0 STRAP2 Do Not Stuff

2
2

R7648 ROM_SCLK N15_Samsung

Q7606
2

2
R7649 Do Not Stuff STRAP3 STRAP0

2
Do Not Stuff G ROM_SO
GC6_20 GC6_20 STRAP4 STRAP1
1

R7623 GC6_20 D ROM_SI N15_Hynix&Hynix2G&Micron&Micron2G&Samsung2G

Do Not Stuff

Do Not Stuff
1

GPU_EVENT# [20]
N16_Hynix2G4G

GC6_FB_EN 1 2GC6_FB_EN_GPU
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

[20,75,83] GC6_FB_EN
1

1
N15V-GM
R7614

R7620

R7618

R7619

R7655

R7642
N15V_GM

N15V_GM

N16_Samsung1G

N16_Samsung2G

GPU_EVENT_GPU# S N15_Micron&Samsung2G R7621 R7647

1

1
Do Not Stuff R7637 R7609 R7650 R7632 R7654 Do Not Stuff 4K99R2F-L-GP R7622
1

Do Not Stuff Do Not Stuff 4K99R2F-L-GP Do Not Stuff 45K3R2F-L-GP N15_Samsung&Hynix&Hynix2G N16V-GM Do Not Stuff
R7627 Do Not Stuff
N15_Micron&Hynix2G N16V-GM N15V-GM N16V-GM
Do Not Stuff Do Not Stuff
2

2
DY 2ND = 84.2N702.031
2

2
SORx_EXPOSED=0000
For Gen3 support
2

GC6_20
No VBIOS ROM
R7644
2 DY 1
A A
Do Not Stuff

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU(4/5)GPIO/STRAP
Size Document Number Rev
Custom
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 76 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU VGA_CORE

GPU1F 6 OF 14
13/14 GND
A2 GND GND M13
Under GPU 5 OF 14
AB17 GND GND M15
GPU1E AB20 GND GND M17 G10,G12:
11/14 NVVDD AB24 GND GND N10 If GC62.0 is implemented, connect to a 3V3 rail that will be on in GC6.
K10 VDD AC2 GND GND N12 If GC62.0 is NOT implemented, connect to the same rail as VDD33.
K12 VDD AC22 GND GND N14
K14 AC26 N16
C7722
1
C7708 C7723 C7702 C7701
Vinafix.comK16
VDD
VDD AC5
GND
GND
GND
GND N18 3V3_AON_S0

1
K18 VDD AC8 GND GND P11
OPS OPS OPS OPS OPS L11 AD12 P13 Under GPUNear GPU
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
VDD GND GND
D L13 AD13 P15 D
2

2
VDD GND GND
L15 VDD A26 GND GND P17
L17 VDD AD15 GND GND P2
M10 VDD AD16 GND GND P23
M12 VDD AD18 GND GND P26
M14 AD19 P5 C7735
VDD GND GND

1
M16 AD21 R10 OPS C7736 C7704
VDD GND GND
M18 AD22 R12 OPS

SC1U10V2KX-1GP
SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP
VDD GND GND GPU1C 3 OF 14
N11 AE11 R14 OPS

2
VDD GND GND
N13 VDD AE14 GND GND R16 14/14 XVDD/VDD33
N15 VDD AE17 GND GND R18
N17 VDD AE20 GND GND T11 AD10 NC#AD10(GM108:3V3_AON) VDD33 G10
P10 VDD AB11 GND GND T13 AD7 NC#AD7 (GM108:3V3_AON) VDD33 G12
C7709 C7725 C7721 C7720 C7719 P12 AF1 T15 B19 G8
VDD GND GND NC#B19 FBA_CMD32 VDD33
1

1
P14 VDD AF11 GND GND T17 VDD33 G9
OPS OPS OPS OPS OPS P16 AF14 U10
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
VDD GND GND
P18 AF17 U12 F11
2

2
VDD GND GND 3V3AUX 3D3V_VGA_S0
R11 VDD AF20 GND GND U14
R13 VDD AF23 GND GND U16 V5 NC#V5
R15 VDD AF5 GND GND U18 V6 NC#V6 Under GPU Near GPU
R17 VDD AF8 GND GND U2
T10 VDD AG2 GND GND U23
T12
T14
VDD AG26
AB14
GND GND U26
U5
3.3V +/- 5%
VDD GND GND
T16
T18
VDD B1
B11
GND GND V11
V13
CONFIGURABLE
POWER CHANNELS C7734 C7729
85mA
VDD GND GND

1
U11 B14 V15 * nc on substrate OPS OPS C7728 C7703
VDD GND GND
OPS OPS OPS OPS U13 B17 V17 OPS

SC1U10V2KX-1GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP
VDD GND GND
U15 B20 Y2 G1 OPS

2
C VDD GND GND NC#G1 C
U17 VDD B23 GND GND Y23 G2 NC#G2
1

V10 VDD B27 GND GND Y26 G3 NC#G3

C7714 C7713 C7712 C7711 V12 B5 Y5 G4
VDD GND GND NC#G4
SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

V14 B8 G5
2

VDD GND NC#G5

V16 VDD E11 GND G6 NC#G6
V18 VDD E14 GND G7 NC#G7
E17 GND
E2 GND
N14M-GE-S-A2-GP E20 V1
GND NC#V1
E22 GND V2 NC#V2
E25
71.0N14M.B0U E5
GND
GND
E8 GND
OPS H2 GND
Near GPU H23 GND W1 NC#W1
H25 GND W2 NC#W2
H5 GND W3 NC#W3
K11 GND W4 NC#W4
K13 GND
K15 GND
K17 N14M-GE-S-A2-GP
C7732 C7731 C7730 C7726 C7724 C7717 C7710 GND
L10 GND
1

OPS OPS OPS OPS OPS OPS OPS L12

L14
GND 71.0N14M.B0U
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

GND
SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

L16 OPS
2

GND
L18 GND
L2 GND
L23 GND
L25 GND
B B
L5 GND GND AA7
M11 GND GND AB7

N14M-GE-S-A2-GP

71.0N14M.B0U

OPS

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU(5/5)PWR/GND
Size Document Number Rev
A3
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 77 of 105
5 4 3 2 1
 5 4 3 2 1

1D35V_VGA_S0 VRAM3 Place close VRAM1 VDD ball

FBA_D[0..31] [75] 1D35V_VGA_S0 VRAM1 1D35V_VGA_S0
FBA_D0 FBA_D[0..31] [75]
B2 VDD DQ0 E3
D9 F7 FBA_D4 B2 E3 FBA_D21
G7
VDD
VDD
DQ1
DQ2 F2 FBA_D2 D9
VDD
VDD
DQ0
DQ1 F7 FBA_D17 A00 08.10
K2 F8 FBA_D7 G7 F2 FBA_D20
VDD
Vinafix.com
DQ3 VDD DQ2

1
SC1U10V3KX-4GP-U
C7805
K8 H3 FBA_D1 K2 F8 FBA_D16 C7827 C7804
VDD DQ4 VDD DQ3

Do Not Stuff

Do Not Stuff
N1 H8 FBA_D5 K8 H3 FBA_D22 DY DY OPS
VDD DQ5 FBA_D3 VDD DQ4 FBA_D19
N9 G2 N1 H8

2
VDD DQ6 FBA_D6 VDD DQ5 FBA_D23
D R1 VDD DQ7 H7 N9 VDD DQ6 G2 D
1D35V_VGA_S0 R9 D7 FBA_D10 R1 H7 FBA_D18
VDD DQ8 FBA_D13 1D35V_VGA_S0 VDD DQ7 FBA_D30
DQ9 C3 R9 VDD DQ8 D7
A1 C8 FBA_D8 C3 FBA_D25
VDDQ DQ10 FBA_D12 DQ9 FBA_D31
A8 VDDQ DQ11 C2 A1 VDDQ DQ10 C8
C1 A7 FBA_D11 A8 C2 FBA_D26
VDDQ DQ12 FBA_D15 VDDQ DQ11 FBA_D29
C9 VDDQ DQ13 A2 C1 VDDQ DQ12 A7
D2 B8 FBA_D9 C9 A2 FBA_D24
VDDQ DQ14 FBA_D14 VDDQ DQ13 FBA_D28
E9 A3 D2 B8
F1
VDDQ DQ15
E9
VDDQ DQ14
A3 FBA_D27 Place close VRAM2 VDD ball
VDDQ VDDQ DQ15 1D35V_VGA_S0
H2 VDDQ LDQS F3 FBA_EDC0 [75] F1 VDDQ
H9 G3 H2 F3
VDDQ LDQS# FBA_DQS_RN0 [75]
H9
VDDQ
VDDQ
LDQS
LDQS# G3
FBA_EDC2 [75]
FBA_DQS_RN2 [75]
A00 08.10
FBA_VREF_0 UDQS C7 FBA_EDC1 [75] OPS OPS
H1 VREFDQ UDQS# B7 FBA_DQS_RN1 [75] UDQS C7 FBA_EDC3 [75]

1
R7808 M8 FBA_VREF_0 H1 B7 C7820 C7821 C7822
VREFCA VREFDQ UDQS# FBA_DQS_RN3 [75]

SCD1U16V2KX-3GP

Do Not Stuff

SC1U10V3KX-4GP-U
1 OPS 2 FBA_ZQ0 L8 ZQ ODT K1 FBA_CMD2 [75] R7809 M8 VREFCA DY
243R2F-2-GP 1 OPS 2FBA_ZQ1 L8 K1 FBA_CMD2 [75]

2
243R2F-2-GP ZQ ODT
CS# L2 FBA_CMD0 [75]
[75,79] FBA_CMD9 N3 A0 RESET# T2 FBA_CMD5 [75,79] CS# L2 FBA_CMD0 [75]
[75,79] FBA_CMD11 P7 A1 [75,79] FBA_CMD9 N3 A0 RESET# T2 FBA_CMD5 [75,79]
[75,79] FBA_CMD8 P3 A2 NC#J1 J1 [75,79] FBA_CMD11 P7 A1
[75,79] FBA_CMD25 N2 A3 NC#J9 J9 [75,79] FBA_CMD8 P3 A2 NC#J1 J1
[75,79] FBA_CMD10 P8 A4 NC#L1 L1 [75,79] FBA_CMD25 N2 A3 NC#J9 J9
[75,79] FBA_CMD24 P2 A5 NC#L9 L9 [75,79] FBA_CMD10 P8 A4 NC#L1 L1
[75,79] FBA_CMD22 R8 A6 NC#M7 M7 [75,79] FBA_CMD24 P2 A5 NC#L9 L9
[75,79] FBA_CMD7 R2 A7 NC#T3 T3 FBA_CMD20 [75,79] [75,79] FBA_CMD22 R8 A6 NC#M7 M7
[75,79] FBA_CMD21 T8 A8 NC#T7 T7 FBA_CMD4 [75,79] [75,79] FBA_CMD7 R2 A7 NC#T3 T3 FBA_CMD20 [75,79]
[75,79] FBA_CMD6 R3 A9 [75,79] FBA_CMD21 T8 A8 NC#T7 T7 FBA_CMD4 [75,79]
C L7 R3 C
[75,79] FBA_CMD29 A10/AP [75,79] FBA_CMD6 A9
R7 A9 L7
[75,79]
[75,79]
FBA_CMD23
FBA_CMD28 N7
A11 VSS
B3
[75,79]
[75,79]
FBA_CMD29
FBA_CMD23 R7
A10/AP
A9
Place close VRAM1VDDQ ball
A12/BC# VSS A11 VSS Change to 10U 0603 for height limit issue. 1D35V_VGA_S0
VSS E1 [75,79] FBA_CMD28 N7 A12/BC# VSS B3
72.41K26.00U VSS G8 VSS E1
[75,79] FBA_CMD12 M2 BA0 VSS J2 72.41K26.00U VSS G8
A00 08.10
[75,79] FBA_CMD27 N8 BA1 VSS J8 [75,79] FBA_CMD12 M2 BA0 VSS J2

C7813
Do Not Stuff

C7832 Do Not Stuff

C7829 SCD1U16V2KX-3GP

C7831 SCD1U16V2KX-3GP

C7830 Do Not Stuff

[75,79] FBA_CMD26 M3 BA2 VSS M1 [75,79] FBA_CMD27 N8 BA1 VSS J8
C7812 C7810 C7814
OPS OPS
VSS M9 [75,79] FBA_CMD26 M3 BA2 VSS M1

1
VSS P1 VSS M9 OPS OPS OPS
E7 P9 OPS P1 DY DY DY

SC1U10V3KX-4GP-U

SC1U10V3KX-4GP-U

SC1U10V3KX-4GP-U
[75] FBA_DQM0 LDM VSS VSS
[75] FBA_DQM1 D3 T1 [75] FBA_DQM2 E7 P9

2
UDM VSS LDM VSS
OPS VSS T9 [75] FBA_DQM3 D3 UDM VSS T1
VSS T9
[75] FBA_CLK0P J7 CK VSSQ B1
[75] FBA_CLK0N K7 B9 [75] FBA_CLK0P FBA_CLK0P J7 B1
CK# VSSQ FBA_CLK0N CK VSSQ
VSSQ D1 [75] FBA_CLK0N K7 CK# VSSQ B9
[75] FBA_CMD3 K9 CKE VSSQ D8 VSSQ D1
E2 [75] FBA_CMD3 FBA_CMD3 K9 D8
VSSQ CKE VSSQ
VSSQ E8 VSSQ E2
[75,79] FBA_CMD13 L3 WE# VSSQ F9 VSSQ E8
K3 G1 L3 F9
[75,79] FBA_CMD15
[75,79] FBA_CMD30 J3
CAS# VSSQ
G9
[75,79] FBA_CMD13
[75,79] FBA_CMD15 K3
WE# VSSQ
G1
Place close VRAM1VDDQ ball
RAS# VSSQ CAS# VSSQ 1D35V_VGA_S0
[75,79] FBA_CMD30 J3 RAS# VSSQ G9 Change to 10U 0603 for height limit issue.

Check MT41K256M16HA-107G-E-GP
MT41K256M16HA-107G-E-GP A00 08.10

C7836 Do Not Stuff

C7833 Do Not Stuff

C7835 Do Not Stuff

C7834 SCD1U16V2KX-3GP
OPS

SC1U10V3KX-4GP-U
C7817

SC1U10V3KX-4GP-U
C7811

SC1U10V3KX-4GP-U
C7816

Do Not Stuff
C7815
1

1
B B
Frame Buffer Patition A-Lower Half OPS OPS OPS
FBCLK Termination place on VRAM side DY DY DY DY

2
1D35V_VGA_S0

FBA_CLK0P
1
1K33R2F-GP
R7806

2
OPS R7810
162R2F-GP
2

FBA_VREF_0
OPS
1
1
SC820P50V2KX-1GP
C7803

1K33R2F-GP
R7807
1

FBA_CLK0N
OPS OPS
2

Layout Note: Place in the end.

2

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM1,2 (1/4)
Size Document Number Rev
A3
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 78 of 105

5 4 3 2 1
 5 4 3 2 1

Place close VRAM3 VDD ball

1D35V_VGA_S0
1D35V_VGA_S0 VRAM2 1D35V_VGA_S0 VRAM4
FBA_D[32..63] [75] FBA_D[32..63] [75] A00 08.10

C7910 Do Not Stuff

C7909 Do Not Stuff

B2 E3 FBA_D32 B2 E3 FBA_D41
VDD DQ0 FBA_D39 VDD DQ0 FBA_D45
D9 VDD DQ1 F7 D9 VDD DQ1 F7

1
G7 F2 FBA_D35 G7 F2 FBA_D43 OPS C7906
VDD
Vinafix.com
DQ2 VDD DQ2

SC1U10V3KX-4GP-U
K2 F8 FBA_D36 K2 F8 FBA_D47 DY DY
VDD DQ3 FBA_D34 VDD DQ3 FBA_D40
K8 H3 K8 H3

2
VDD DQ4 FBA_D38 VDD DQ4 FBA_D46
N1 VDD DQ5 H8 N1 VDD DQ5 H8
D N9 G2 FBA_D33 N9 G2 FBA_D42 D
VDD DQ6 FBA_D37 VDD DQ6 FBA_D44
R1 VDD DQ7 H7 R1 VDD DQ7 H7
1D35V_VGA_S0 R9 D7 FBA_D58 1D35V_VGA_S0 R9 D7 FBA_D49
VDD DQ8 FBA_D61 VDD DQ8 FBA_D53
DQ9 C3 DQ9 C3
A1 C8 FBA_D56 A1 C8 FBA_D51
VDDQ DQ10 FBA_D63 VDDQ DQ10 FBA_D54
A8 VDDQ DQ11 C2 A8 VDDQ DQ11 C2
C1 A7 FBA_D57 C1 A7 FBA_D50
VDDQ DQ12 FBA_D62 VDDQ DQ12 FBA_D55
C9 VDDQ DQ13 A2 C9 VDDQ DQ13 A2
D2 B8 FBA_D59 D2 B8 FBA_D48
E9
VDDQ DQ14
A3 FBA_D60 E9
VDDQ DQ14
A3 FBA_D52 Place close VRAM4 VDD ball
VDDQ DQ15 VDDQ DQ15 1D35V_VGA_S0
F1 VDDQ F1 VDDQ
H2 F3 H2 F3
H9
VDDQ
VDDQ
LDQS
LDQS# G3
FBA_EDC4 [75]
FBA_DQS_RN4 [75] H9
VDDQ
VDDQ
LDQS
LDQS# G3
FBA_EDC5 [75]
FBA_DQS_RN5 [75]
A00 08.10

C7913 SCD1U16V2KX-3GP

C7912 SCD1U16V2KX-3GP
OPS OPS
UDQS C7 FBA_EDC7 [75] UDQS C7 FBA_EDC6 [75]

1
FBA_VREF_1 H1 B7 FBA_VREF_1 H1 B7 OPS C7911
VREFDQ UDQS# FBA_DQS_RN7 [75] VREFDQ UDQS# FBA_DQS_RN6 [75]

SC1U10V3KX-4GP-U
R7912 M8 R7913 M8
VREFCA VREFCA
1 OPS 2FBA_ZQ2 L8 K1 FBA_CMD18 [75] 1 OPS 2FBA_ZQ3 L8 K1 FBA_CMD18 [75]

2
243R2F-2-GP ZQ ODT 243R2F-2-GP ZQ ODT

CS# L2 FBA_CMD16 [75] CS# L2 FBA_CMD16 [75]

[75,78] FBA_CMD9 N3 A0 RESET# T2 FBA_CMD5 [75,78] [75,78] FBA_CMD9 N3 A0 RESET# T2 FBA_CMD5 [75,78]
[75,78] FBA_CMD11 P7 A1 [75,78] FBA_CMD11 P7 A1
[75,78] FBA_CMD8 P3 A2 NC#J1 J1 [75,78] FBA_CMD8 P3 A2 NC#J1 J1
[75,78] FBA_CMD25 N2 A3 NC#J9 J9 [75,78] FBA_CMD25 N2 A3 NC#J9 J9
[75,78] FBA_CMD10 P8 A4 NC#L1 L1 [75,78] FBA_CMD10 P8 A4 NC#L1 L1
[75,78] FBA_CMD24 P2 A5 NC#L9 L9 [75,78] FBA_CMD24 P2 A5 NC#L9 L9
[75,78] FBA_CMD22 R8 A6 NC#M7 M7 [75,78] FBA_CMD22 R8 A6 NC#M7 M7
R2 T3 R2 T3
[75,78]
[75,78]
FBA_CMD7
FBA_CMD21 T8
A7 NC#T3
T7
FBA_CMD20 [75,78]
FBA_CMD4 [75,78]
[75,78]
[75,78]
FBA_CMD7
FBA_CMD21 T8
A7 NC#T3
T7
FBA_CMD20 [75,78]
FBA_CMD4 [75,78]
Place close VRAM3 VDDQ ball
C A8 NC#T7 A8 NC#T7 1D35V_VGA_S0 C
[75,78] FBA_CMD6 R3 A9 [75,78] FBA_CMD6 R3 A9
[75,78] FBA_CMD29 L7 A10/AP [75,78] FBA_CMD29 L7 A10/AP
R7 A9 R7 A9
[75,78]
[75,78]
FBA_CMD23
FBA_CMD28 N7
A11
A12/BC#
VSS
VSS B3
[75,78]
[75,78]
FBA_CMD23
FBA_CMD28 N7
A11
A12/BC#
VSS
VSS B3 A00 08.10

C7921 Do Not Stuff

C7922 Do Not Stuff

C7923 Do Not Stuff

C7925 Do Not Stuff

VSS E1 VSS E1
72.41K26.00U G8 72.41K26.00U G8 C7916 C7915 C7919
VSS VSS

1
[75,78] FBA_CMD12 M2 BA0 VSS J2 [75,78] FBA_CMD12 M2 BA0 VSS J2 OPS OPS OPS

SC1U10V3KX-4GP-U

SC1U10V3KX-4GP-U

SC1U10V3KX-4GP-U
[75,78] FBA_CMD27 N8 BA1 VSS J8 [75,78] FBA_CMD27 N8 BA1 VSS J8 DY DY DY DY
[75,78] FBA_CMD26 M3 M1 [75,78] FBA_CMD26 M3 M1

2
BA2 VSS BA2 VSS
VSS M9 VSS M9
VSS P1 OPS VSS P1
[75] FBA_DQM4 E7 LDM VSS P9 [75] FBA_DQM5 E7 LDM VSS P9
[75] FBA_DQM7 D3 UDM VSS T1 [75] FBA_DQM6 D3 UDM VSS T1
VSS T9 VSS T9

[75] FBA_CLK1P J7 OPS B1 [75] FBA_CLK1P FBA_CLK1P J7 B1

CK VSSQ FBA_CLK1N CK VSSQ
[75] FBA_CLK1N K7 CK# VSSQ B9 [75] FBA_CLK1N K7 CK# VSSQ B9
VSSQ D1 VSSQ D1
[75] FBA_CMD19 FBA_CMD19 K9 D8 [75] FBA_CMD19 FBA_CMD19 K9 D8
CKE VSSQ CKE VSSQ
VSSQ E2 VSSQ E2
VSSQ E8 VSSQ E8
L3 F9 L3 F9
[75,78] FBA_CMD13
[75,78] FBA_CMD15 K3
WE# VSSQ
G1
[75,78] FBA_CMD13
[75,78] FBA_CMD15 K3
WE# VSSQ
G1
Place close VRAM4 VDDQ ball
CAS# VSSQ CAS# VSSQ 1D35V_VGA_S0
[75,78] FBA_CMD30 J3 RAS# VSSQ G9 [75,78] FBA_CMD30 J3 RAS# VSSQ G9

MT41K256M16HA-107G-E-GP MT41K256M16HA-107G-E-GP A00 08.10

C7929 SCD1U16V2KX-3GP

C7928 Do Not Stuff

C7930 Do Not Stuff

C7927 SCD1U16V2KX-3GP
C7917 C7926 C7924
OPS OPS

1
B B
OPS OPS OPS

SC1U10V3KX-4GP-U

SC1U10V3KX-4GP-U

SC1U10V3KX-4GP-U
DY DY
Frame Buffer Patition A-Lower Half

2
1D35V_VGA_S0
FBCLK Termination place on VRAM side
1
1K33R2F-GP
R7903

FBA_CLK1P

2
OPS R7914
2

FBA_VREF_1 162R2F-GP
OPS
1
SC820P50V2KX-1GP
C7902

1K33R2F-GP
R7904

1
1

OPS FBA_CLK1N
OPS
2

Layout Note: Place in the end.

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM3,4 (2/4)
Size Document Number Rev
A3
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 79 of 105

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM5,6 (3/4)
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015
Sheet 80 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM7,8 (4/4)
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015
Sheet 81 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = dGFX_CORE

Vinafix.com
DCBATOUT

D D

PC8208 PC8209
Do Not Stuff

2
OPS OPS

SCD1U25V2KX-GP
PC8210 PC8214 PC8220
Do Not Stuff

SC10U25V5KX-GP

SC10U25V5KX-GP
Do Not Stuff
OPS OPS OPS

SC4D7U25V5KX-GP

SC4D7U25V5KX-GP
5V_S0 2 2

1
3 3
4 1 1 4

1
10 10
PR8223 OPS_075.03664.0073
9 9 OPS_075.03664.0073
2D2R3J-2-GP 7 7
6 8 8 6
OPS 5 5

2
Do Not Stuff
RT8812_PVCC VGA_CORE
PU8202 PU8204
PL8201 OPS

1
PC8202 OPS PC8207 1 2
2PWR_VGA_CORE_TON_1 SCD1U50V3KX-GP IND-D33UH-7-GP

1
1

2
OPS PR8216 68.R3310.201 PT8207 PT8206

18

1
SCD1U25V2KX-GP PU8201
DY Do Not Stuff
79.33719.L01OPS 79.33719.L01
OPS

PVCC

SE330U2VDM-L-GP
2

2
PWR_VGA_SNUB1
PR8202 PR8201

SE330U2VDM-L-GP
2 PWR_VGA_CORE_TON PWR_VGA_CORE_UGATE1

1
DCBATOUT 1OPS 2
2D2R2F-GP
OPS
1
499KR2F-1-GP
9
TON UGATE1
2
DYPC8206
Do Not Stuff
PR8203 PR8210
PWR_VGA_CORE_BOOT1 1 2PWR_VGA_CORE_BOOT1_1 1

2
3V3_AON_S0 1 OPS 2 13 1 2
PGOOD BOOT1 0R3J-0-U-GP OPS
100KR2J-1-GP PC8211
OPS SCD1U50V3KX-GP
PWR_VGA_CORE_EN 3 20 PWR_VGA_CORE_PHASE1
[19,24,83] DGPU_PWROK EN PHASE1

PWR_VGA_CORE_PSI 4 19 PWR_VGA_CORE_LGATE1
PSI LGATE1 DCBATOUT
PR8207 PR8224 OCP setting (current limit ~ 60.3A)
[76] VGA_CORE_VID 1 2 0R2J-2-GP 1 2
OPS OPS
5K76R2F-2-GP OPS should be in DUMMY column. PU8206
PC8203 1 Do Not Stuff PWR_VGA_CORE_VID PWR_VGA_CORE_UGATE2 PC8212 PC8213
DY2 5 14

2
VID UGATE2 OPS OPS

SCD1U25V2KX-GP
Do Not Stuff PC8215 PC8224 PC8221
C Do Not Stuff C

SC10U25V5KX-GP

SC10U25V5KX-GP
PC8201 PR8211
DY 2 2 OPS OPS OPS

SC4D7U25V5KX-GP

SC4D7U25V5KX-GP
PWR_VGA_CORE_RGND 1 2 Do Not Stuff PWR_VGA_CORE_VREF 8 15 PWR_VGA_CORE_BOOT2 1
OPS 2PWR_VGA_CORE_BOOT2_1 1 2 3 3

1
VREF BOOT2 0R3J-0-U-GP OPS 4 1 1 4
PC8216
SCD1U50V3KX-GP 10 10
1

PWR_VGA_CORE_REFIN PWR_VGA_CORE_PHASE2
R2 7 16 9 OPS_075.03664.0073
9
7OPS_075.03664.0073
REFIN PHASE2
PR8206 R1 6 8
7
20KR2F-L-GP OPS PWR_VGA_CORE_REFADJ 6 17 PWR_VGA_CORE_LGATE2 5
8 6
5
REFADJ LGATE2
1

REFIN_VREF PR8222
2

20KR2F-L-GP Do Not Stuff

R3 OPS
PWR_VGA_CORE_SS 11
SS VSNS
12 PWR_VGA_CORE_VSNS
Do Not Stuff PU8208
VGA_CORE
1

PR8208 PC8205
OPSSC47P50V2JN-3GP PL8202 OPS
PWR_VGA_CORE_RGND
2

1 OPS 2 21 10
GND RGND 1 2
2KR2F-3-GP
2

IND-D33UH-7-GP N16V_GM_B1

1
OPS RT8812AGQW-GP PT8208 Config B
1

3V3_AON_S0 PR8215

1
OPS

SE330U2D5VM-14-GP
PC8223 Do Not Stuff
SC2700P50V2KX-1-GP 74.08812.073
DY OPS
2

2
C

2
PWR_VGA_CORE_RGND PR8258 PWR_VGA_SNUB2
10KR2J-3-GP

1
PC8218
OPS Do Not Stuff
2

PR8257
R4+R5 DY

2
[76] VGA_CORE_PSI 1 OPS 2 PWR_VGA_CORE_PSI
1

0R2J-2-GP
PR8209
OPS
1

N16V_GM_B1 18KR2F-GP
DY
PC8226
2
Do Not Stuff

PC8204 PR8259
Config B Do Not Stuff
DY Do Not Stuff
2

DY
1
PWR_VGA_CORE_RGND

PWR_VGA_CORE_RGND

VGA_CORE
2

Design Current=33.5A
56.65A <OCP< 66.7A

1
Component N15V-GM-S N16V-GM-B1 PR8212
B Config D Config B 100R2F-L1-GP-U B
Check
value OPS

2
PR8221
27K 20K 1 2 0R2J-2-GP
R1 (PR8222) OPS VGACORE_VDD_SENSE_1 [73]

1
64.27025.6DL 64.20025.6DL 3D3V_VGA_S0

1
PC8222
R2 (PR8206) 7.5K 20K
PR8256
OPS PC8219
DY Do Not Stuff
64.75015.6DL OPS

2
64.20025.6DL SC47P50V2JN-3GP
1 2 PWR_VGA_CORE_EN
PWR_VGA_CORE_EN [83]

2
0 2K 1KR2J-1-GP
R3 (PR8208)
63.R0034.1DL 64.20015.6DL PR8220
2 0R2J-2-GP
2

1
Do Not Stuff

7.87K 18K PC8225 OPS VGACORE_GND_SENSE_1 [73]

1
R4+R5 (PR8209) 64.78715.6DL 64.18025.6DL
PR8260 DY PC8217

1
DY
1

5.6nF 2.7nF Do Not Stuff

C (PC8223) [20,83] DGPU_PWR_EN 1 DY 2

2
78.56222.2FL 78.27224.2FL PR8213
100R2F-L1-GP-U
Do Not Stuff OPS
78.56222.2FL:OBS REASON: 50V is more popular, chage to 78.56224.2FL

2
For tuning VGA_CORE sequence.

I/P cap: 10U 25V K0805 X5R/ 78.10622.51L

Inductor:CHIP CHOKE 0.22UH PCMC104T-R22/ 1mohm/ Isat =60A rms /68.R2210.10C
O/P cap: CHIP CAP EL 330U 2.5V M6.3*4.4 Chemi-con/79.3371V.6CL
H/S: SIRA14DP-T1-GE3 / 6.8mohm/8.5mOhm@4.5Vgs/ 84.A14DP.037
L/S:SIRA06DP-T1-GE3 / 2.75mohm/3.5mOhm@4.5Vgs/ 84.SRA06.037

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8812_VGACORE
Size Document Number Rev
A2
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 82 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU dGPU Power Discharge Circuit

[DG-07158-001 Rev03]Power up sequence:
3.3V ==> NVVDD (VGA_CORE) ==> PEX_VDD (1.05V) ==> FBVDD/Q (1.35V)
3D3V_AUX_S5
1D05V_VGA_S0
3D3V_S0 to 3V3_AON_S0 and 3D3V_VGA_S0 1D05V_VGA_EN#
1D05V_VGA_S0 1D35V_VGA_S0
3D3V_S0
1 OPS 2
1D35V_VGA_S0
3V3_AON_S0 3D3V_VGA_S0 PR8307 D G S
U8301 3D3V_VGA_S0 100KR2J-1-GP
3D3V_VGA_S0: 3A @ 3.3V 3D3V_VGA_S0

1
Vinafix.com
GC6 2.0 only DY C8307 5V_S0 4 13
Do Not Stuff VBIAS OUT1#13 PQ8301 PR8306 PR8313
OUT1#14
14
3D3V_VGA_CT_1
R8301
OPS OPS OPS
12 C8302 1 2 2N7002KDW-GP 100R2J-2-GP 100R2J-2-GP

2
CT1
1
IN1#1 OPS 1 2 84.2N702.A3F Need to fine tune.
3V3_AON_S0 SC470P50V2KX-3GP
2 8 NON_GC6

2
IN1#2 OUT2#8 2nd = 84.2N702.E3F
3 9
D
[76] GPIO5_GC6_PWR_EN
3V3_MAIN_EN is an open-drain GPIO.
EN1 OUT2#9
CT2
10 3V3_AON_CT_2
C8306
3V3_AON_S0 0R6J-3-GP
3rd = 75.00601.07C S G D Need to fine tune. DIS_1D35V_VGA_S0
D

1
4th = 84.DMN66.03F
3D3V_S0 6
IN2#6 OPS

SC470P50V2KX-3GP
3D3V_VGA_S0 3V3_AON_S0
7
IN2#7 GND
11 OPS
5 15

D
2
1
C8305 EN2 GND 1D05V_VGA_EN 1D05V_VGA_S0_DISCHG
DY OPSC8301

1
C8304 PQ8302

Do Not Stuff

SC10U10V5KX-2GP

SC10U10V5KX-2GP
R8306 G5016KD1U-GP OPS 2N7002K-2-GP

2
NON_GC6 0R2J-2-GP 84.2N702.J31

2
1
074.05016.0093 OPS
3D3V_AUX_S5
VGA_CORE

S
PR8315
[20,82] DGPU_PWR_EN PWR_VGA_CORE_EN#
2 OPS 1
VGA_CORE 1D35V_VGA_EN#
100KR2J-1-GP
Need to fine tune.

1
PQ8305 PR8309
2N7002KDW-GP OPS 100R2J-2-GP
84.2N702.A3F OPS

2
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F VGA_CORE_DISCHG

1D35V_VGA_S0 [82] PWR_VGA_CORE_EN

3D3V_AUX_S5
1.35V +/- 3%. PR8317
3V3_AON_S0
DGPU_PWR_EN#
1D35V_S3 5.6A 1D35V_VGA_S0
2 OPS 1
3V3_AON_S0
PQ8304 Need to fine tune.
100KR2J-1-GP
OPS
SIRA06DP-T1-GE3, SO-8 8 D S 1

1
C 7 D S 2 C
Id=40A, Qg=22.5 nC 6 D S 3 PQ8306 PR8316

1
Rdson=2.5~3.5 mohm 5 D PC8310 2N7002KDW-GP OPS 100R2J-2-GP
1

SC10U6D3V3MX-GP
PC8309
84.2N702.A3F OPS
OPS G OPS
4

2
SC10U6D3V3MX-GP SIRA06DP-T1-GE3-1-GP 084.SRA06.0037 2nd = 84.2N702.E3F
2

3rd = 75.00601.07C
4th = 84.DMN66.03F 3V3_AON_S0_DISCHG

1D35V_ENABLE_RC
3D3V_S5_KBC
R8305 [20,82] DGPU_PWR_EN
DY OPS
1 2 1 2
750KR2J-GP 3D3V_AUX_S5
PR8314
PR8319
3D3V_VGA_S0
1

Do Not Stuff PC8308 GPIO5_GC6_PWR_EN#

3D3V_AUX_S5
2 OPS 1
3D3V_VGA_S0
OPS
OPS Need to fine tune.
2

1D35V_VGA_EN# SCD01U50V2KX-1GP 100KR2J-1-GP

1 2

1
PR8311 D G S
100KR2J-1-GP PQ8307 PR8318
TP8301 OPS
2N7002KDW-GP 100R2J-2-GP
6

Do Not Stuff
PQ8303 DCBATOUT 84.2N702.A3F OPS

2
2N7002KDW-GP OPS 2nd = 84.2N702.E3F
1D35V_ENABLE_TP 3rd = 75.00601.07C
84.2N702.A3F
1
1

2nd = 84.2N702.E3F 4th = 84.DMN66.03F 3D3V_VGA_S0_DISCHG

Do Not Stuff 3rd = 75.00601.07C S G D OPS PR8312
D8301 DY PR8310 330KR2J-L1-GP
1 4th = 84.DMN66.03F Do Not Stuff
[20,75,76] GC6_FB_EN [76] GPIO5_GC6_PWR_EN
1

1D35V_VGA_EN
GC6_20 3

2 1D35V_ENABLE

Do Not Stuff

1 2
3D3V_S5 RT8068A for 1D05_VGA Design Current = 1.1A
B R8303 B
0R2J-2-GP PG8301
1

NON_GC6 2 1

1D05V_VGA_S0_PWRGD
R8304
Do Not Stuff PU8301
1D05V_VGA_S0
Do Not Stuff
PG8302 1D05V_VGA_S0

Note:ZZ.08068.A4301
GC6_20 2 1 PWR_1D05V_PVDD 10 1 1D05V_PWR
2

PR8301 PVIN LX#1

PL8301
[DG-07158-001 Rev03] PWR_1D05V_SVIN PWR_1D05V_PHASE
Do Not Stuff 1 OPS 2
2D2R2F-GP
9
PVIN LX#2
2 PG8304
PG8303 1OPS 2 2 1

1
2 1 PC8301 8 3
SVIN LX#3
OPS SC1U10V2KX-1GP IND-2D2UH-161-GP-U Do Not Stuff

1
Do Not Stuff 7 PG8305

2
PWR_1D05V_EN NC#7 PR8303 PC8305
EN OPS
5 2 1
1

Do Not Stuff
PC8307 PC8306 7K5R2F-1-GP
6 OPS R1 DY

1
FB
SC10U6D3V3MX-GP

Do Not Stuff
PWR_1D05V_PGOOD PC8303 PC8304
OPS DY 4
PGOOD
Do Not Stuff

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
11 OPS OPS PG8306
2

2
GND
2 1

2
3V3_AON_S0 RT8068AZQWID-GP-U
PWR_1D05V_FB Do Not Stuff
PG8307
74.08068.A43 2 1

1
PR8304

1
Do Not Stuff
PR8305
OPS 100KR2F-L1-GP PR8302 R2
1D05V_VGA_EN 10KR2F-2-GP OPS
1 OPS 2

2
PR8320 Vo=0.6*(1+(R1/R2))

2
1

0R2J-2-GP PC8302
DY 1 OPS 2 1D05V_VGA_S0_PWRGD
Do Not Stuff
2

0R2J-2-GP

3D3V_VGA_S0
1

PR8308
A A
Do Not Stuff
GC6_20
2

R8302
1 2 1D05V_VGA_EN
[19,24,82] DGPU_PWROK
0R2J-2-GP <Core Design>
NON_GC6
2

DY C8303 Wistron Corporation

Do Not Stuff 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1

Taipei Hsien 221, Taiwan, R.O.C.

Title

DISCRETE VGA POWER

Size Document Number Rev
A2 Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 83 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 84 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 85 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

UNUSED PARTS/EMI Capacitors

Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015Sheet 86 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 87 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 88 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = UnusedParts

H3
H1 H2 H4 H5 H6 H7 HCPU1 HCPU2 HCPU3
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff

Vinafix.com
D D
1

1
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff

STF237R117H81-1-GP STF237R117H81-1-GP STF237R117H81-1-GP

HGPU1 HGPU2 HGPU3
SPR1 SPR2 SPR3
Do Not Stuff SPRING-24-GP-U SPRING-13-GP-U

OPS OPS OPS Spring Spring Spring

1
1

1
34.44L12.001 34.44L12.001 34.44L12.001 Do Not Stuff 34.45T31.001 34.43E24.001

C C

Main Func = EMICapacitors

Mind the voltage rating of the caps.

DCBATOUT
1

1
EC9701 EC9702 EC9703 EC9704 EC9705 EC9706 EC9707 EC9708 EC9709 EC9710 EC9711 EC9712 EC9713 EC9714 EC9715 EC9716 EC9717 EC9723 EC9724 EC9726 EC9727 EC9728

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

SC1U25V3KX-1-GP
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
2

2
B B

5V_S0
3D3V_S0 5V_S5 AUD_AGND
1D35V_VGA_S0
EC9720 EC9719 EC9718 EC9721 EC9722
1

EC9737 EC9735 EC9736 EC9738 EC9734 EC9732 EC9733

1

1
DY DY DY EC9725 EC9739 EC9744 EC9743 EC9745

1
SC1U10V2KX-1GP

Do Not Stuff
Do Not Stuff

Do Not Stuff

SCD1U25V2KX-GP

DY DY DY DY DY DY
2

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
SCD1U25V2KX-GP

DY DY
2

Do Not Stuff

Do Not Stuff
2

2
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

UNUSED PARTS/EMI Capacitors

Size Document Number Rev
A3
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 89 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 90 of 105
5 4 3 2 1
 5 4 3 2 1

SSID = TPM
[18,24,25] SPI_CLK_ROM 33R2J-2-GP 1 R9107 2 SPI_CLK_ROM_TPM

[18,24,25] SPI_SO_ROM 33R2J-2-GP 1 R9106 2 SPI_SO_ROM_TPM

Vinafix.com [18,24,25] SPI_SI_ROM 33R2J-2-GP 1 R9105 2 SPI_SI_ROM_TPM

Do Not Stuff 1R9104 SPI_IRQ#

D
3D3V_TPM 2
DY D

3D3V_TPM 10KR2J-3-GP 2 R9103 1 SPI_CS2#_R

3D3V_S0
R9114 10KR2J-3-GP 2 R9102 1 SERIRQ_TPM
2 1 Do Not Stuff
3D3V_S0 3D3V_TPM 3D3V_S5
R9110 3D3V_TPM
R9108 2
Do Not Stuff DY
1
2
DY
Do Not Stuff
1
Q9101 3D3V_TPM

SCD1U16V2KX-3GP
1

1
C9104
3D3V_S5 DMP2130L-7-GP

Q9102 DY R9117
Do Not Stuff

2
2 R9101 1 S S
Do Not Stuff TPM_GPIO2 D

2
TPM_GPIO2

+UZ12_TPM

D
DY D 84.02130.031
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1

1
C9102

C9103
C9101
SC4D7U6D3V3KX-GP

G
SPI_CS2#_R G R9118

G
C 10KR2J-3-GP C
2

Do Not Stuff
Do Not Stuff Q9101.G 1 R9115 2 SPI_CS2#_R

2
100R2F-L1-GP-U

U9101 3D3V_S0

8 29 TPM_GPIO0 R9119 1 2
Do Not Stuff R9111 1TPM_VDD14 14 VDD GPIO0/SDA/XOR_OUT 10KR2J-3-GP
2 VDD GPIO1/SCL 30
3D3V_S5 3D3V_TPM_1 Do Not Stuff 2 R9112 1TPM_VDD22 22 3 TPM_GPIO2 R9120 1 2
VDD GPX/GPIO2
6 DY
Do Not Stuff
GPIO3/BADD
R9109 1 2 R9113 1TPM_VSB TPM_GPIO4 R9116 1 2SPI_CS2#_R
2
Do Not Stuff Do Not Stuff
1 VSB CLKRUN#/GPIO4/SINT# 13
DY
Do Not Stuff
SCD1U16V2KX-3GP
1

1
C9105
C9106
SC4D7U6D3V3KX-GP

SPI_SO_ROM_TPM 24 2
SPI_SI_ROM_TPM LAD0/MISO NC#2
21 7
2

SPI_IRQ# LAD1/MOSI NC#7

18 LAD2/SPI_IRQ# NC#10 10
15 LAD3 NC#11 11
B
NC#25 25 B
SERIRQ_TPM 27 26
SPI_CLK_ROM_TPM SERIRQ NC#26
19 LCLK/SCLK NC#31 31
28 LPCPD#
[18] SPI_CS2#_R 20 LFRAME#/SCS#
[17,24,31,40,55,61,68,73] PLT_RST# 17 SRESET#/LRESET#/SPI_RST# GND 9
GND 16
4 PP GND 23
5 TEST GND 32
12 RESERVED GND 33

NPCT650JAAYX-GP

071.00650.0A03
<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
TPM2.0
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 91 of 105
5 4 3 2 1
 5 4 3 2 1

SSID = Finger Print

Vinafix.com
D D

A00 Change

Do Not Stuff 1 2 R9203 USB_PN3_C

[16] USB_CPU_PN3
Do Not Stuff 1 2 R9204 USB_PP3_C
[16] USB_CPU_PP3

PTW O-CON6-21-GP

C 7 C
1

2
3 USB_PP3_C
4 USB_PN3_C
5
6 FP_PW R R9201 2 1 Do Not Stuff
8
DY 5V_S5
R9202 1 2 Do Not Stuff 5V_S0
1

FPR1
C9201 C9202
020.K0002.0006
2

2
SCD1U16V2KX-3GP

SC1U10V2KX-1GP

2nd = 20.K0824.006
For EMI Reserved

USB_PN3_C
USB_PP3_C
2

2
EC9201 DY EC9202 DY
1

1
Do Not Stuff

Do Not Stuff

FP_PW R 1 AFTP8902 Do Not Stuff

B USB_PN3_C 1 AFTP8903 Do Not Stuff B
USB_PP3_C 1 AFTP8904 Do Not Stuff

Layout Note:
close to FPR1

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Finger Print (Reserved)
Size Document Number Rev
A3
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 92 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 93 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 94 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 95 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 96 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

LVDS_Switch
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 97 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D Firmware SW D

Default setting:pull high

DY for production
MESW1
1

[19,24] ME_FWP_EC C

C1

MESW1_B B MESW
2

1
C C
R9804 Do Not Stuff
Do Not Stuff Do Not Stuff
MESW

2
A B

High Low
ME_FWP_SOC
Normal Operation Override
(Default)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Firmware SW
Size Document Number Rev
A4
Loveland SKL-U A00
Date: Tuesday, September 15, 2015Sheet 98 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = Debug

CFG[19:0]
[6] CFG[19:0]

[4] XDP_BPM[3:0]
XDP_BPM[3:0]
Vinafix.com
D D

[18] PCIE_CLK_XDP_P 1 TP9908 Do Not Stuff

[18] PCIE_CLK_XDP_N 1 TP9909 Do Not Stuff
[17] PM_RSMRST# 1 TP9903 Do Not Stuff
[17] XDP_DBRESET# 1 TP9923 Do Not Stuff
[6] ITP_PMODE 1 TP9922 Do Not Stuff
[18] XDP_SPI0_IO2 1 TP9921 Do Not Stuff
1 TP9905 Do Not Stuff
[18] SPI0_MOSI_XDP TP9910 Do Not Stuff
[4] XDP_TRST# 1
1 TP9917 Do Not Stuff
[4] PCH_JTAG_TCK TP9918 Do Not Stuff
[16] XDP_PREQ# 1
[16] XDP_PRDY# 1 TP9919 Do Not Stuff

R9926 1 DY 2 Do Not Stuff XDP_PW RBTN# 1 TP9904 Do Not Stuff

[17,24] SIO_PW RBTN#
R9918 1 DY 2 Do Not Stuff XDP_SMBDAT 1 TP9906 Do Not Stuff
[12,13,18,65,66,67] PCH_SMBDATA
R9920 1 DY 2 Do Not Stuff XDP_SMBCLK 1 TP9907 Do Not Stuff
[12,13,18,65,66,67] PCH_SMBCLK

[4] PCH_JTAG_TMS 1 R9927 2 1 TP9911 Do Not Stuff

Do Not Stuff
C [4] XDP_TMS C

[4] PCH_JTAG_TDI 1 R9928 2 1 TP9914 Do Not Stuff

Do Not Stuff
[4] XDP_TDI

[4] XDP_TCLK 1 R9930 2 1 TP9915 Do Not Stuff

Do Not Stuff XDP_BPM0 1 TP9947 Do Not Stuff
[4] XDP_TCK_JTAGX XDP_BPM1 TP9944 Do Not Stuff
1
XDP_BPM2 1 TP9946 Do Not Stuff
[4] XDP_TDO_CPU 1 R9935 2 1 TP9916 Do Not Stuff XDP_BPM3 1 TP9945 Do Not Stuff
[4] PCH_JTAG_TDO Do Not Stuff

CFG0 1 TP9933 Do Not Stuff

CFG1 1 TP9925 Do Not Stuff
CFG2 1 TP9929 Do Not Stuff
CFG3 1 TP9926 Do Not Stuff
CFG4 1 TP9928 Do Not Stuff
CFG5 1 TP9924 Do Not Stuff
CFG6 1 TP9932 Do Not Stuff
CFG7 1 TP9930 Do Not Stuff
CFG17 1 TP9931 Do Not Stuff
B CFG16 TP9927 Do Not Stuff B
1
CFG8 1 TP9943 Do Not Stuff
CFG9 1 TP9935 Do Not Stuff
CFG10 1 TP9939 Do Not Stuff
CFG11 1 TP9936 Do Not Stuff
CFG19 1 TP9938 Do Not Stuff
CFG18 1 TP9934 Do Not Stuff
CFG12 1 TP9942 Do Not Stuff
CFG13 1 TP9940 Do Not Stuff
CFG14 1 TP9941 Do Not Stuff
CFG15 1 TP9937 Do Not Stuff

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_XDP;PCH_XDP
Size Document Number Rev
A3
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 99 of 105
5 4 3 2 1
 5 4 3 2 1

CLK Block Diagram

Vinafix.com Intel CPU

D
Haswell/Broadwell ULT D

M_A_DIMA_CLK_DDR0
CK0 SA_CLK0
M_A_DIMA_CLK_DDR#0
CK0# SA_CLK#0
DDR3L DIMM1
M_A_DIMA_CLK_DDR1
CK1 SA_CLK1
M_A_DIMA_CLK_DDR#1
CK1# SA_CLK#1 CLK_PCIE_WLAN_P3
CLKOUT_PCIE_P2 REFCLKP0
WLAN
CLK_PCIE_WLAN_N3
CLKOUT_PCIE_N2 REFCLKN0 NGFF

LAN
CLK_PCIE_LAN_P4
RTL8106E/RTL8111G
CLKOUT_PCIE_P3 REFCLK_P

FBA_CLK0P CLK_PCIE_LAN_N4
C CK CLKOUT_PCIE_N3 REFCLK_N C

VRAM1 FBA_CLK0N
VGA
CK#
N15V-GM-S-A2
LANXIN
FBA_CLK0P
GB2-64 (23x23) CKXTAL1
CLK_PCIE_VGA#
CK
FBA_CLK0N ‧ FBA_CLK0 PEX_REFCLK# CLKOUT_PCIE_N4
VRAM2 CK# ‧ FBA_CLK0# X3001
25MHz
CLK_PCIE_VGA
PEX_REFCLK CLKOUT_PCIE_P4
LANXOUT
CKXTAL2
FBA_CLK1P
CK 27MHZ_IN
XTAL_IN
VRAM3 CK#
FBA_CLK1N

X7601
27MHz
FBA_CLK1P
CK
FBA_CLK1N ‧ FBA_CLK1
27MHZ_OUT Audio
VRAM4 CK# ‧ FBA_CLK1# XTAL_OUT

RN2102
Realtek
HDA_BITCLK HDA_CODEC_BITCLK
HDA_BCLK/I2S0_SCLK BITCLK ALC3223
B SRN33J-5-GP-U B

RTC_X1
RTCX1

X1901
R5815
0R2J-2-GP
SUSCLK_NGFF
SUS_CLK NGFF
32.768KHz

RTC_X2
RTCX2
XTAL24_IN KBC
XTAL24_IN
NPCE285P
SUS_CLK_PCH R1710 SUS_CLK R2441 SUS_CLK_KBC
X1801 SUSCLK/GPIO62
0R2J-2-GP ‧ 0R2J-2-GP
GPIO0/EXTCLK/F_SDIO3
24MHz CLK_PCI_KBC_R R1805 CLK_PCI_KBC
CLKOUT_LPC_1 LCLK/GPIOF5
0R2J-2-GP
XTAL24_OUT CLKOUT_LPC_0 CLK_PCI_LPC_R R1804 CLK_PCI_LPC
XTAL24_OUT 0R2J-2-GP
LPC

CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P
Test Point
A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CLK Block Diagram
Size Document Number Rev
A2
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 100 of 105
5 4 3 2 1
 5 4 3 2 1

Change notes -
DATE VERSON DATE Page Modify List OWNER

Vinafix.com
D D

C C

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Change History
Size Document Number Rev
A3
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 101 of 105

5 4 3 2 1
 5 4 3 2 1

SKL-U/Y Timing Diagram for G3 to S0/M0 [Deep Sx Platform]

[#543016 Rev0.9]
(DC mode) Red Words: Controlled by EC GPIO Tulip Skylake POWER UP SEQUENCE DIAGRAM (Deep Sx Platform)
Red: Power Rail
+RTC_VCC t01 >9ms
Orange: Output from KBC
1D0V_S5 5V_S5
RTC_RST# Light Blue: Output from CPU

DCBATOUT
Vin VDD
3D3V_AUX_S5 DC SI7121DN-T1-GE3
BT+ Page43
Battery EN SW +V1.00U_CPU(VCCST)
a Page43 Page43
Sense the power button status Press Power button SLG59M1470VTR
KBC_PWRBTN# Platform to KBC PSL_IN2 V8P10-5300M3-86A d Page40
PSL_OUT#(GPIO71) keep low AC +DC_IN SI7121DN-T1-GE3
3D3V_S5_KBC a Adapter in S5_ENABLE 3D3V_S5
KBC GPIO34 control power on by 3V_5V_EN Page43
Page43

Vinafix.com
S5_ENABLE
AD+ 3D3V_S5
5V_S5 IN 1D5V_S0
5V_S5 & 3D3V_S5 need meet 0.7V difference Out
V5REF_Sus must be powered up before EN1 EN2
VccSus3_3, or after VccSus3_3 within 3D3V_S5 3D3V_S5
D
0.7 V. Also, V5REF_Sus must power 5V_S5 & 3D3V_S5 need meet 0.7V difference TLV70215DBVR D
down after VccSus3_3, or before Charger EN Vin +VCCIO_VR
VccSus3_3 within 0.7 V. +5VA_PCH_VCC5REFSUS Ta DCBATOUT TPS51225RUKR Lx
BQ24770RUYR VIN
KBC GPIO43 to PCH DC/DC Page54
4 PM_SLP_S3# RT8068AZQWID
PM_RSMRST#(RSMRST#_RST) t05 >10ms (3.3V/5V) 5V_S5 EN VCCIO_PWRGD
t07 >100ms ACOK Page44 PGOOD
In case of a non-Deep S4/S5 Platform PCH to KBC GPIO00
timing t42 should be added to t07 PCH_SUSCLK_KBC Page45 Page52 5
which will make it 100mS minimum.
b PWR_CHG_ACOK

KBC GPIO20 to PCH 3D3V_AUX_S5 e PM_SLP_S4# S5 1D35V_S3

PM_PWRBTN# 2N7002 3

PM_SLP_S4#

PM_SLP_S3#
Page45 SWITCH 3V_5V_POK TPS51716RUKR
DDR_VTT_PG_CTRL 0D675V_S0
Page24 S3

1D35V_VTT_PWRGD
PSL_OUT# 3D3V_S5_KBC PM_SLP_SUS# PGOOD

PM_PWRBTN# g Page51
DC
After Power Button
3 4 4 5
PCH to KBC GPIO44
c SLP_S4# SLP_S3# DDR_PG_CTL

PM_SLP_S4# GPIO71 GPIO05 H_VR_ENABLE

t10 PCH to KBC GPIO01 VR_EN
KBC_PWRBTN#
PM_SLP_S3# >30us PSL_IN2# S5_ENABLE DPWROK 7
KBC GPIO47 to LAN GPIO34
1
PM_LAN_ENABLE d
Enable by PM_SLP_S4# The DSW rails must be stable for at least
1D5V_S3 10 ms before DSW_PWROK is asserted to PCH.
KBC_DPWROK
GPIO66 DSW_PWROK
DDR_VREF_S3(0.75V)
5V_S0 & 3D3V_S0 need meet 0.7V difference f

TBD
5V_S0 AC_IN# b PM_PWRBTN# Skylake-U MCP
PSL_IN1# GPIO20 PWRBTN#
V5REF must be powered up before 3D3V_S0 RSMRST_PWRGD#
TBD KBC 2
Vcc3_3, or after Vcc3_3 within 0.7 j ALL_SYS_PWRGD and VR_RDY assert,
3D3V_S5

Delay 10ms
V. Also, V5REF must power down
after Vcc3_3, or before Vcc3_3
within 0.7 V.
+5VS_PCH_VCC5REF Tb MEC1404 delay 10ms; PCH_PWROK assert.
RSMRST#_KBC: Delay 10 ms after receive 8 PCH_PWROK
1D5V_S0 RSMRST_PWRGD# and PM_SLP_SUS#. AND APWROK 4 PM_SLP_S3#

AND
Vcc
RSMRST#_KBC k AND Gate
1D8V_S0 PCH_PWROK PM_SLP_S0# VCCSTG_EN
GPIO36 GPIO93 PCH_PWROK SLP_S0# U74LVC1G08G-AL5 Y

0D75V_S0 VR_RDY 6
1D8V_S0 & 1D5V_S3 power ready 7 TBD PM_SUSWARN# 5
GPIO02 SUSWARN# PROCPWRGD
RUNPWROK
ALL_SYS_PWRGD l
6 GPIO26 9 1D0V_S5 5V_S5
1D05V_PCH PM_SUSACK#
GPIO81 SUSACK#
PLTRST# 11 PCI_PLTRST#
VCCP_CPU m AND VIN VDD
It is recommended that SYS_PWROK be asserted after RSMRST#_KBC VCCSTG_EN
both PWROK assertion and processor core VR PWRGD assertion. RSMRST# EN +V1.00DX(VCCSTG)
1D05_VTT_PWRGD VOUT
k
0D85V_S0 SY6288C10CAC
PM_SLP_S4#
GPIO44 Page41
3

Delay 100ms
PM_SLP_S3#
4 GPIO01 H_VCCST_PWRGD ALL_SYS_PWRGD
0D85V_S0 6 Level Shifter
D85V_PWRGD 10 74LVC1G07GW Page17
C SYS_PWROK C
GPIO77 SYS_PWROK
CPU SVID BUS SetVID ACK 50us< t36 <2000us EXT_PWR_GATE#
Page24 1D35VTT_PWRGD
VCC_CORE EXT_PWR_GATE# 5
ALL_SYS_PWRGD assert, SLP_SUS#
g ALL_SYS_PWRGD
VCC_GFXCORE delay 100ms; SYS_PWROK assert. VCCIO_PWRGD
t37
3D3V_S5 5 6
<5ms
g
IMVP_PWRGD
VIN

PM_SLP_SUS# 3D3V_S5_PCH
PCH_CLOCK_OUT SVID Transanctions EN SW

ALL_SYS_PWRGD=D85V_PWRGD t14 >99ms KBC GPIO77 to PCH

SY6288C10CAC
This signal represents the Power
Good for all the non-CORE and PWROK(S0_PWR_GOOD) Page41
non-graphics power rails.
t18
D85V_PWRGD >0us PCH to CPU
DRAMPWROK(VDDPWRGOOD) 2ms<t17 <650ms IMVP8 3D3V_S5
>1ms
CPU SVID Rails
t19
6 ALL_SYS_PWRGD SA/Core/GT/GTx
VR_ON
1D8V_S0
t20 >2ms
5ms<t13 <650ms VR_RDY VR_READY VIN
PCH to CPU PM_SLP_SUS#
UNCOREPWRGOOD(H_CPUPWRGD) 7 VCCPRIM_CORE
EN LX

SYS_PWROK t21+t22 >1ms+60us RT8068AZQWID VCCPRIMCORE_PWROK

PGOOD

1ms< t25 <100ms PCH to all system 1D0V_S5 5V_S5 Page52 h

PLT_RST#
t39 <200us
3D3V_S5 5V_S5
DMI
Vin VDD

+VCCMPHYGTAON_1P0_LS_SIP
EXT_PWR_GATE# EN SW
Vin VCNTL
g PM_SLP_SUS#
SLG59M1470VTR 1D8V_S5
EN Vout
Page17
APL5930KAI 1D8V_S5_PWROK
PGOOD

Page54 h

3V_5V_POK
e 0R 0402
PWR_DCBATOUT_1D0V
VCCPRIMCORE_PWROK RSMRST_PWRGD#
h 0R 0402

1D8V_S5_PWROK
j VIN
h 0R 0402
1D0V_S5
LX
1D0V_S5_PWRGD VCCPRIMCORE_PWROK EN
i
0R 0402
SY8208DQNC
[dGPU] N16x Power-Up/Down Sequence [dGPU] GC6 2.0 Power-Up/Down Sequence h PGOOD

Page53
1D0V_S5_PWRGD

i
B B

[DG-07158-001_v03]

a b c d e f g h i j k l m

1 2 3a 4 4a 4b 5 6 7 8 9 10 11 12

A A

<Core Des ign>

Wistron Corporation
21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih,
Taipei Hs ien 221, Taiwan, R.O.C.

Title

Size Docum ent Num ber

Power Sequence Rev
A0
Loveland SKL-U A00
Date: Tues day, Septem ber 15, 2015 Sheet 102 of 105
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Power Block Diagram
Size Document Number Rev
A2
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 103 of 105
5 4 3 2 1
 A B C D E

PCH SMBus Block Diagram KBC SMBus Block Diagram

3D3V_S5_PCH 3D3V_S0
TP_VDD
‧ ‧
3D3V_S0 ‧
SRN2K2J-1-GP SRN10KJ-5-GP

Vinafix.com
‧
DIMM 1 SRN10KJ-5-GP

1 SMBCLK MEM_SMBCLK
‧ ‧PCH_SMBCLK 1

SMBDATA MEM_SMBDATA
‧ ‧ PCH_SMBDATA
SCL

SDA
TouchPad Conn.
PSDAT1 TPDATA
‧ TPDATA TPDATA

SMBus Address:0xA0 PSCLK1 TPCLK

‧ TPCLK TPCLK
2N7002SPT
3D3V_S5_KBC
DIMM 2
PCH_SMBCLK
SCL
PCH_SMBDATA
SDA
‧
3D3V_S5_PCH
SMBus Address:0XA4 SRN4K7J-8-GP

‧
TPAD SRN33J-7-GP Battery Conn.
PCH_SMBCLK
GPIO010/SMB01_CLK ‧‧SMBCLK1 PBAT_SMBCLK1 CLK_SMB
SRN2K2J-1-GP SCL
GPIO007/SMB01_DATA SMBDA1 PBAT_SMBDAT1 DAT_SMB SMBus address:16
PCH_SMBDATA
SDA
‧ ‧

SML0CLK SML0_CLK SMBus Address:0x58/0x59

SML0DATA SML0_DATA HPA02224RGRR
RTD2168 SCL
PCH_SMBCLK VDDA33_DP KBC SDA SMBus address:12
PCH_SMBDATA
TMS MEC1404
SMBus Address:0x64/0x65
2
SMBus Address:0x68/0x69 2

GPIO013/SMB02_CLK

FFS GPIO012/SMB02_DATA

PCH_SMBCLK

PCH PCH_SMBDATA
SCL

SDA SMBus Address:

0x94/0x95/0x96/0x97
SMBus Address:0X52h/0X53h

3D3V_S0
3D3V_S5_PCH
‧
3D3V_S0
SRN2K2J-8-GP

‧ SRN2K2J-8-GP

SML1CLK
‧ ‧ SML1_SMBCLK
‧ THM_SML1_CLK
SCL Thermal
SML1DATA
‧ ‧ SML1_SMBDATA
‧ THM_SML1_DATA
SDL
NCT7718W
SMBus Address:0x82/0x83 SMBus Address:0x98/0x99
2N7002SPT
3D3V_VGA_S0
3 3

‧SRN4K7J-8-GP
3D3V_VGA_S0

‧
dGPU
SMBC_Therm_NV I2CS_SCL
‧
SMBD_Therm_NV I2CS_SDA
‧
SMBus Address:0x9E/0x9F

3D3V_S0 5V_S0

‧ ‧
3D3V_S0
SRN2K2J-1-GP SRN2K2J-1-GP
‧

DDPB_CTRLCLK ‧CPU_DP1_CTRL_CLK DDC_CLK_HDMI ‧

4
DDPB_CTRLDATA ‧ CPU_DP1_CTRL_DATA ‧‧ DDC_DATA_HDMI ‧ HDMI CONN 4

2N7002DW-1-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

SMBUS Block Diagram

Size Document Number Rev
A2 Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 104 of 105
A B C D E
 A B C D E

Thermal Block Diagram Audio Block Diagram

Vinafix.com
1 1

3D3V_S5_PCH 3D3V_S0
PAGE28 D+ NCT7718_DXP
PCH MMBT3904-3-GP
SPKR_L+
SPKR_L-

D- NCT7718_DXN
SC2200P50V2KX-2GP SPKR_R-
SPKR_R+ SPEAKER
Thermal Place near CPU
SML1_DATA THM_SML1_DATA
NCT7718 PWM CORE
Codec
SML1DATA/GPIO74 ‧ ‧‧ 2N7002 ‧ SDA

SML1CLK/GPIO75 SML1_CLK
‧‧ ‧ THM_SML1_CLK
‧ SCL
MMBT3904-3-GP
ALC3223
T8 AUD_HP1_JACK_L HP MIC
SML1_DATA

AUD_HP1_JACK_R
SML1_CLK

PAGE20
3D3V_S0
T_CRIT# THERM_SYS_SHDN#
2N7002
S
D
PURE_HW_SHUTDOWN#

PCH_PWROK
EN 3V/5V SLEEVE COMBO
G RING2
2 2
‧ Put under CPU(T8 HW shutdown)

PAGE27 PAGE86
GPIO74

KBC GPIO73
R2714
Digital
NPCE285P 2N7002
SMBD_THERM_NV I2CS_SCL
VGA GPIO0/DMIC_DATA
DMIC_DATA_R
0R2J-2-GP
DMIC_DATA
MIC
SMBC_THERM_NV I2CS_SDA DMIC_CLK_R R2716 DMIC_CLK
GPIO1/DMIC_CLK
0R2J-2-GP

GPIO4
N15V-GM-S-A2
GPIO94 GPIO56
GB2-64 (23x23)
FAN_TACH1
FAN1_DAC_1

3 3
TACH

FAN
VIN
FAN_VCC1

5V

VIN VSET VOUT

FAN CONTROL
APL5606AKI
PAGE28

4 4
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
Thermal/Audio Block Diagram
Document Number Rev
Custom
Loveland SKL-U A00
Date: Tuesday, September 15, 2015 Sheet 105 of 105
A B C D E