09-05-2024

Computer Arithmatic
Prof. Atul Barve
Prestige Institute of Engineering, Management & Research,
Indore

● Addition
● Subtraction,
● Two’s Compliment
Representation,
● Signed Addition and Subtraction
Topics ● Multiplication and Division
● Booths Algorithm,
● Division Operation,
● Floating Point Arithmetic
Operation
● Design of Arithmetic unit

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INTRODUCTION
● Based on the number system two basic data types are implemented in the
computer system: fixed point numbers and floating point numbers.
● Representing numbers in such data types is commonly known as fixed point
representation and floating point representation, respectively.
● Depending on the design, the hardware can interpret number as an integer
or fraction.
● In integer number radix point is fixed and the number system is referred to
as fixed point number system. We can represent positive or negative integer
numbers.
● Floating point number system allows the representation of numbers having
both integer part and fractional part.

ADDITION AND SUBTRACTION OF SIGNED

NUMBERS
● We can relate addition and subtraction operations of numbers by the
following Relationship:
(± A) - (+B) = (± A) + (-B) and
(± A) - (- B) = (± A) + (+B)
● Therefore, we can change subtraction operation to an addition operation by
changing the sign of the subtrahend.

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1's Complement Representation

● The 1’s complement of a binary number is the number that results when we
change all 1’s to zeros and the zeros to ones.
● 1’s complement of (11000100)2.

1 1 0 0 0 1 0 0
       
0 0 1 1 1 0 1 1

2's Complement Representation

● The 2’s complement is the binary number that results when we add 1 to the
1's Complement.
2’s complement of a number= 1’s complement of a number + 1
● The 2’s complement form’ is used to represent negative numbers. Find 2’s
complement of (11000100)2.
Solution  1 1 0 0 0 1 0 0
      
0 1 1 1 0 1 1 1' s Comp lim ent
0 0 1 1 1 0 1 1 1' s Comp lim ent
 1 2' s Comp lim ent
0 1 1 1 1 0 0

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Additions by 1’s Complement:

Case-1: Addition of positive and negative number when positive number
has greater magnitude:
● When positive number has greater magnitude, then take simply 1’s
complement of negative number and the end-around carry of the sum is
added to the least significant bit (LSB).
● Example: Add 1110 and -1101.

So, take 1’s complement of 1101, which will be 0010, then add with given
number. So, 1110+0010=1 0000 , then add this carry bit to the LSB,
0000+1=0001 , which is the answer.

Additions by 1’s Complement:

Case-2: Addition of positive and negative number when negative number
has greater magnitude:
● When the negative number has greater magnitude, then take 1’s
complement of negative number and add with given positive number. Since
there will not be any end-around carry bit, so take 1’s complement of the
result and this result will be negative.
● Example: Add 1010 and -1100 in five-bit registers.
Note that there are five-bit registers, so these new numbers will be 01010 and -
01100.
Now take 1’s complement of 01100 which will be 10011 and add
01010+10011=11101 . Then take 1’s complement of this result, which will be
00010 and this will be negative number, i.e., -00010, which is the answer.

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Additions by 1’s Complement:

Case-3: Addition of two negative numbers:
● You need to take 1’s complement for both numbers, then add these 1’s
complement of numbers. Since there will always be end-around carry bit, so add
this again to the LSB of result. Now, take 1’s complement also of previous result,
so this will be negative number.
● Alternatively, you can add both negative number directly, and get this result
which will be negative only.
● Example: add -1010 and -0101 in five bit-register.
These five bit numbers are -01010 and -00101. Add complements of these
numbers, 10101+11010 =1 01111 . Since, there is a carry bit 1, so add this to the
LSB of result, i.e., 01111+1=10000 . Now take the 1’s complement of this result,
which will be 01111 and this number is negative, i.e, -01111, which is answer.

Subtractions by 1’s Complement

● Take 1’s complement of the subtrahend
● Add with minuend
● If the result of above addition has carry bit 1, then add it to the least
significant bit (LSB) of given result
● If there is no carry bit 1, then take 1’s complement of the result which will be
negative

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Subtractions by 1’s Complement

● Example (Case-1: When Carry bit 1): Evaluate 10101 - 00101
 Take 1’s complement of subtrahend 00101, which will be 11010,
 then add both of these. So, 10101 + 11010 =1 01111 .
 Since, there is carry bit 1, so add this to the LSB of given result, i.e.,
01111+1=10000 which is the answer.

● Example (Case-2: When no Carry bit): Evaluate 11110 with 1110

 Take 1’s complement of subtrahend 11110, which will be 00011.
 Then add both of these, So, 11001 + 00011 =11100 .
 Since there is no carry bit 1, so take 1’s complement of above result,
which will be 00011, and this is negative number, i.e, 00011, which is
the answer.

Additions by 2’s Complement:

Case-1: Addition of the positive and a negative number when the positive
number has a greater magnitude:
● Initially find the 2's complement of the given negative number.
● Sum up with the given positive number.
● If we get the end-around carry 1 then the number will be a positive number
and the carry bit will be discarded and remaining bits are the final result.

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Additions by 2’s Complement:

Case-1: Example: 1101 and -1001
● First, find the 2's complement of the negative number 1001. So the 2's
complement of number 1001 is 0110+1=0111
● Add both the numbers, i.e., 1101 and 0111;
1101+0111=1 0100
● By adding both numbers, we get the end-around carry 1. We discard the end-
around carry. So, the addition of both numbers is 0100.

Additions by 2’s Complement:

Case-2: Addition of the positive and a negative number when the negative
number has a higher magnitude:
● Initially, add a positive value with the 2's complement value of the negative
number.
● Here, no end-around carry is found. So, we take the 2's complement of the
result to get the final result.
● Note: The resultant is a negative value.

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Additions by 2’s Complement:

Case-2: Example: 1101 and -1110
● First, find the 2's complement of the negative number 1110. So, for finding
2's complement, 0001+1=0010
● Add both the numbers, i.e., 1101 and 0010;
1101+0010= 1111
● Find the 2's complement of the result 1111 that is the final result. So, the 2's
complement of the result 1111 is 0001, and add a negative sign before the
number so that we can identify that it is a negative number.

Additions by 2’s Complement:

Case-3: Addition of two negative numbers:
● In this case, first, find the 2's complement of both the negative numbers, and
then we will add both these complement numbers.
● In this case, we will always get the end-around carry, which will be
discarded, we will take the 2's complement of the result to get final result.
● Note: The resultant is a negative value.

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Additions by 2’s Complement:

Case-3: Example: -1101 and -1110 in five-bit register
● Firstly find the 2's complement of the negative numbers 01101 and 01110.
So, 2's complement of the number 01110 is 10010, and 01101 is 10011.
● We add both the complement numbers, i.e., 10001 and 10010;
10010+10011= 1 00101
● By adding both numbers, we get the end-around carry 1. This carry is
discarded and the final result is the 2’s complement of the result 00101. So,
the 2's complement of the result 00101 is 11011, and we add a negative sign
before the number so that we can identify that it is a negative number.

Subtraction using 2's complement

● In the first step, find the 2's complement of the subtrahend.
● Add the complement number with the minuend.
● If we get the carry by adding both the numbers, then we discard this carry
and the result is positive else take 2's complement of the result which will be
negative.

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Subtraction using 2's complement

Example 1: 10101 - 00111
● We take 2's complement of subtrahend 00111, which is 11001. Now, sum
them. So,
10101+11001 =1 01110.
● In the above result, we get the carry bit 1. So we discard this carry bit and
remaining is the final result and a positive number.
Example 2: 10101 - 10111
● We take 2's complement of subtrahend 10111, which comes out 01001.
Now, we add both of the numbers. So,
10101+01001 =11110.
● In the above result, we didn't get the carry bit. So calculate the 2's
complement of the result, i.e., 00010. It is the negative number and the final
answer.

Subtraction using 2's complement

Example 1: 10101 - 00111
● We take 2's complement of subtrahend 00111, which is 11001. Now, sum
them. So,
10101+11001 =1 01110.
● In the above result, we get the carry bit 1. So we discard this carry bit and
remaining is the final result and a positive number.
Example 2: 10101 - 10111
● We take 2's complement of subtrahend 10111, which comes out 01001.
Now, we add both of the numbers. So,
10101+01001 =11110.
● In the above result, we didn't get the carry bit. So calculate the 2's
complement of the result, i.e., 00010. It is the negative number and the final
answer.

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Addition / Subtraction Logic Unit

● Hardware to implement integer addition and subtraction consists of n-bit
adder, 2’s complement circuit, overflow detector logic circuit and AVF
(overflow flag).
● Number a and number b are the two inputs for n-bit adder.

Addition / Subtraction Logic Unit

● For subtraction, the subtrahend (number from B register) is converted
into its 2's complement form by making Add/ Subtract control signal to
the logic one.
● When Add/Subtract control signal is one, all bits of number b are
complemented and carry zero (C0) is set to one. Therefore, n-bit adder
gives result as R = a + b(bar) + 1, where b (bar) +1 represents 2's
complement of number b.
● Overflow=an-1bn-1R’n-1+a’n-1b’n-1Rn-1

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ADDITION AND SUBTRACTION ALGORITHM & FLOWCHART

● There are three ways of representing negative fixed-point binary

numbers:
1. Signed magnitude
2. Signed- 1’s complement
3. Signed-2's complement.
● Most computers use the signed-2's complement representation when
performing arithmetic operations with integers.
● For floating-point operations, most computers use the signed-magnitude
representation for the mantissa.

ADDITION AND SUBTRACTION WITH SIGNED MAGNITUDE DATA

● There are eight different conditions to consider, when the signed numbers
are added or subtracted
Subtract Magnitudes
Operation Add Magnitudes
When A>B When A<B When A=B
(+A)+(+B) +(A+B)
(+A)+(-B) +(A-B) -(B-A) +(A-B)
(-A)+(+B) -(A-B) +(B-A) +(A-B)
(-A)+(-B) -(A+B)
(+A)-(+B) +(A-B) -(B-A) +(A-B)
(+A)-(-B) +(A+B)
(-A)-(+B) -(A+B)
(-A)-(-B) -(A-B) +(B-A) +(A-B)

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Hardware Implementation
● To implement the two arithmetic operations with hardware, it is first
necessary that the two numbers be stored in registers.
● Let A and B be two registers that hold the magnitudes of the numbers, and
AS and BS be two flip flops that hold the corresponding signs.
● The result of the operation may be transferred to a third register.
● Algorithm:
● First, a parallel adder is needed to perform the micro operation A + B.
● Second, a comparator circuit is needed to establish if A>B, A=B, or A< B.
● Third, two parallel subtractor circuits are needed to perform the micro
operations A-B and B- A.

Flowchart

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Addition and Subtraction with Signed-2's Complement Data

● The addition of two numbers in signed 2's complement form consists of

adding the numbers with the sign bits treated the same as the other bits of
the number.
● A carry out of the sign bit position is discarded.
● The subtraction consists of first taking the 2’s complement of the
subtrahend and then adding it to the minuend.
● When two numbers of n digits each are added and the sum occupies n+ 1
digit, we say that an overflow occurred.
● An overflow can be detected by inspecting
the last two carries out of the addition.

Addition and Subtraction with Signed-2's Complement Data

Algorithm for adding and subtracting numbers in signed-2's complement

form representation.
● The sum is obtained by adding the contents of AC and BR (including their
sign bits).
● The overflow bit V is set to 1 if the Exclusive-OR of the last two carries is l,
and it is cleared to 0 otherwise.
● The subtraction operation is accomplished by adding the content of AC to
the 2’s complement of BR.
● Taking the 2’s complement of BR has the effect of changing a positive
number to negative, and vice versa.

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Addition and Subtraction with Signed-2's Complement Data

● An overflow must be checked during this operation because the two

numbers added could have same sign.
● The programmer must realize that if an overflow occurs, there will be an
erroneous result in the AC register.
● Comparing this algorithm with its signed-magnitude counterpart, it is
much simpler to add and subtract numbers if negative numbers are
maintained in signed 2’s complement representation

MULTIPLICATION ALGORITHM & FLOWCHART

● Multiplication of two fixed-point binary numbers in signed magnitude
representation is done by a process of successive shift and adds
operations.
● The process consists of looking at successive bits of the multiplier, LSB
first. If the multiplier bit is a 1 multiplicand is copied down otherwise,
zeros are copied down.
● The numbers copied down in successive lines are shifted one position to
the left from the previous number. Finally, the numbers are added and
their sum forms the product.
● The sign of the product is determined from the sign of the multiplicand
and multiplier. If they are alike, the sign of the product is positive. If they
are unlike, the sign of the product is negative.

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MULTIPLICATION ALGORITHM & FLOWCHART

MULTIPLICATION ALGORITHM & FLOWCHART

● Initially, the multiplicand is in B and the
multiplier in Q.
● Their corresponding signs are in BS and
QS respectively.
● The signs are compared, and both A and
Q are set to correspond to the sign of the
product since a double length product
will be stored in registers A and Q.
● Registers A and E are cleared and the
sequence counter SC is set to a number
equal to the number of bits of the
multiplier.

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MULTIPLICATION ALGORITHM & FLOWCHART

● We are assuming here that operands are
transferred to registers from a memory
unit that has words of n bits.
● Since operand must be stored with its
sign, one bit of the word will be
occupied by the sign and the magnitude
will consist of n-1 bits.
● After the initialization, the low order bit
of the multiplier in Q is tested. If it is 1
the multiplicand in B is added to the
present partial product in A. If it is 0,
nothing is done.

MULTIPLICATION ALGORITHM & FLOWCHART

● Register EAQ is then shifted once to the
right to from the new partial product.
● The sequence counter is decremented
by 1 and its new value checked. If it is
not equal to zero, the process is
repeated and a new partial product is
formed. The process stops when SC= 0.
● Note that the partial product formed in
A is shifted into Q one bit at a time and
eventually replaces the multiplier. The
final product is available in both A and
Q, with A holding the MSB and Q holding
the LSB.

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Binary Multiplication example

Booth Multiplication Algorithm

● Booth algorithm gives a procedure for multiplying binary integers in
signed 2’s complement representation.
● It requires less number of additions/subtractions.
● It operates on the fact that strings of 0’s in the multiplier require no
addition but just shifting and a string of 1’s in the multiplier from bit
weight 2^k to weight 2^m can be treated as 2^(k+1 ) to 2^m.
● As in all multiplication schemes, booth algorithm requires examination
of the multiplier bits and shifting of the partial product.

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Booth Multiplication Algorithm

● Prior to the shifting, the multiplicand may be added to the partial
product, subtracted from the partial product, or left unchanged
according to following rules:
 The multiplicand is subtracted from the partial product upon
encountering the first least significant 1 in a string of 1’s in the
multiplier
 The multiplicand is added to the partial product upon encountering
the first 0 (provided that there was a previous ‘1’) in a string of 0’s in
the multiplier.
 The partial product does not change when the multiplier bit is
identical to the previous multiplier bit.

Booth Multiplication Algorithm

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Booth Multiplication Algorithm Example

Qn Qn + 1 BR = (0111) AC QR Qn +1 SC
BR' + 1 = (1001) & Operation

1 0 Initial 0000 0011 0 4

Subtract (BR' + 1) 1001

1001
Perform Arithmetic Right Shift operations (ashr) 1100 1001 1 3
1 1 Perform Arithmetic Right Shift operations (ashr) 1110 0100 1 2
0 1 Addition (AC + BR) 0111

0101 0100

Perform Arithmetic right shift operation 0010 1010 0 1

0 0 Perform Arithmetic right shift operation 0001 0101 0 0

Booth Multiplication Algorithm

● Advantages:
 Faster than traditional multiplication
 Efficient for signed numbers
 Lower hardware requirement
 Widely used in hardware

● Disadvantages:
 Complex to understand
 Limited applicability
 Higher latency
 Higher power consumption

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Booth Multiplication Algorithm

● Application of Booth’s Algorithm:
 Chip and computer processors
 Digital Signal Processing (DSP)
 Hardware Accelerators
 Cryptography
 High-Performance Computing (HPC)

DIVISION ALGORITHM & FLOWCHART

● The Division of two fixed-point
binary numbers in the signed-
magnitude representation is done
by the cycle of successive compare,
shift, and subtract operations.

● The binary division is easier than

the decimal division because the
quotient digit is either 0 or 1. Also,
there is no need to estimate how
many times the dividend or partial
remainders adjust to the divisor.

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DIVISION : Hardware Implementation

● The hardware implementation in the division operation is identical to
that required for multiplication and consists of the following
components:
● Registers B is used to store
divisor, and the double-length
dividend is stored in registers A
and Q
● The information for the relative
magnitude is given in E.
● A sequence Counter register
(SC) is used to store the number
of bits in the dividend.

DIVISION : FLOWCHART

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DIVISION ALGORITHM
The hardware divide algorithm:
● The dividend is in A and Q and the divisor in B.
● The sign of the result is transferred into QS to be part of the quotient.
● A constant is set into the sequence counter SC to specify the number of bits in the
quotient.
● adding As in multiplication, we assume that operands are transferred to registers
from a memory unit that has words of n bits.
● Since an operand must be stored with its sign, one bit of the word will be occupied
by the sign and the magnitude will consist of n-1 bits.
● A divide overflow condition is tested by subtracting the divisor in B from half of the
bits of the dividend stored in A.
● If A > B, the divide overflow flip-flop DVF is set and the operation is terminated
prematurely.
● If A <B, no divide overflow occurs so the value of the dividend is restored by B to A.

DIVISION : Example

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FLOATING POINT REPRESENTATION

● To accommodate very large integers and very small fractions, a computer must be
able to represent numbers and operate on them in such a way that the position of
the binary point is variable and is automatically adjusted as computation proceeds.
● The binary point is said to float, and the numbers are called floating-point numbers.
● The floating point representation has three fields: sign, significant digits and
exponent.
● To represent the number 111101.1000110 in floating point format, first binary
point is shifted to right of the first bit and the number is multiplied by the correct
scaling factor to get the same value.
● The number is said to be in the normalized form and is given as shown in below
format.
111101.1000110 1. 11101100110 x 25<----- Exponent
Significant digits Scaling Factor

FLOATING POINT REPRESENTATION

● Number represented in normalized form
● The base in the scaling factor is fixed 2.
● The string of the significant digits is known as mantissa.
● In the example: 1. 11101100110 x 25
● Sign = 0, Mantissa = 11101100110, Exponent = 5
● Single precision numbers have 1-bit S, 8-bit E, and 23-bit M. Double precision
numbers have 1-bit S, 11-bit E, and 52-bit M. Since a double precision number has
29 more bits for mantissa, the largest error for representing a number is reduced to
1/229 of that of the single precision format

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