4-Vlsi Lecture Chapter 4

RF Microelectronics
Laboratory (iCOE)
SAB24103 VLSI DESIGN
Associate Prof. Basir Saibon (UNIKLMSI Kulim Malaysia)
08.01.2017 ASSOC.PROF.BASIR SAIBON

VLSI DESIGN
1
Chapter 4
Design Rules, Layout & Stick
Diagram
2
Roadmap for the term:
Major Topics
 VLSI Overview
 CMOS Processing & Fabrication
 Components: Transistors, Wires, & Parasitics
 Design Rules & Layout
 Lab Tutorials
 Design Project
3
VLSI DESIGN ASSOC.PROF.BASIR SAIBON
Review - CMOS Mask Layers
 Determine placement of
layout objects
 Color coding specifies
layers
 Layout objects:
 Rectangles
 Polygons
 Arbitrary shapes
 Grid types
n well
 Absolute (“micron”) P substrate
wafer
 Scaleable (“lambda”)
4
CMOS Layers
 n-well process
 p-well process
 Twin-tub process
5
n-well process
Gate NMOS NMOS PMOS PMOS
FOX
n+ n+ n+ n+ p+ p+ p+ p+
n-well
p-substrate
MOSFET Layers in an n-well process
6
Layer Types
 p-substrate
 n-well
 n+
 p+
 Gate oxide
 Gate (polycilicon)
 Field Oxide
 Insulated glass
 Provide electrical isolation
7
Top view of the FET pattern
NMOS NMOS PMOS PMOS
n+ n+ n+ n+ p+ p+ p+ p+
n-well
8
Metal Interconnect Layers
 Metal layers are electrically isolated from

each other
 Electrical contact between adjacent
conducting layers requires contact cuts and
vias
9
Metal Interconnect Layers
Ox3
Via
Metal2
Active Ox2
contact
Metal1
Ox1
n+ n+ n+ n+
p-substrate
10
Layout Design
 Layout can be very time consuming

 Design MOS layout to fit together nicely
 Build a library of standard cells
 Must follow a technology rule
 Standard cell design methodology

 VDD and GND should abut (standard height)
 Adjacent gates should satisfy design rules
 nMOS at bottom and pMOS at top
 All gates include well and substrate contacts
11
Example: Inverter
12
Layout of Different Size of Inverter
13
Example: NAND3
 Horizontal N-diffusion and p-diffusion strips
 Vertical polysilicon gates
 Metal1 VDD rail at top
 Metal1 GND rail at bottom
 32  by 40 
14
NAND3
15
Interconnect Layout Example
Gate contact
Metal1
Metal2
Metal1
MOS
Active contact
16
Designing MOS Arrays
A B C
x y
A B C
17
Parallel Connected MOS
Patterning
x
x
A B
A B
X X X
y y
18
Alternate Layout Strategy
x
x
X X
A B
A B
X X
y y
19
Basic Gate Design
 Both the power supply and ground are routed
using the Metal layer
 n+ and p+ regions are denoted using the
same fill pattern. The only difference is the n-
well
 Contacts are needed from Metal to n+ or p+
20
The CMOS NOT Gate
Contact
Cut
Vp Vp
X n-well
X
x x x x
X
X
Gnd Gnd
21
Alternate Layout of NOT Gate
Vp
Vp
X X
x x
X X
Gnd
x Gnd
x
22
NAND2 Layout
Vp Vp
X X X
a.b
Gnd
a.b
a b
X X
a b
Gnd
23
NOR2 Layout
Vp
Vp
X X
ab
ab
a b X
Gnd X X
a b
Gnd
24
NAND2-NOR2 Comparison
Vp
X X
X
X
X
Gnd
Vp
X
X
MOS Layout X
Wiring X X
Gnd
25
General Layout Geometry
Vp
Shared drain/
source
Individual Shared Gates

Transistors
Gnd
26
Mask Generation
 Mask Design using Layout Editor
 user specifies layout objects on different layers
 output: layout file
 Pattern Generator
 Reads layout file
 Generates enlarged master image of each mask layer
 Image printed on glass
 Step & repeat camera

 Reduces & copies image onto mask
 One copy for each die on wafer
 Note importance of mask alignment
27
Symbolic Mask Layers
 Key idea:
 Reduce layers to those that describe design
 Generate physical layers as needed
 Cadence EDA / Magic EDA Layout Editor: "Abstract Layers”

 metal1 (blue) - 1st layer metal (equiv. to physical layer)
 Poly (red) - polysilicon (equivalent to physical layer)
 ndiff (green) - n diffusion (combination of active, nselect)
 ntranistor (green/red crosshatch) - combined poly, ndiff
 pdiff (brown) - p diffusion (combination of active, pselect)
 ptransistor (brown/red crosshatch) - combined poly, pdiff
 contacts: combine layers, cut mask
28
About Cadence EDA / Magic EDA
 Scalable Grid for Scalable Design Rules
 Grid distance:  (lambda)
 Value is process-dependent:
 = 0.5 X minimum transistor length
 Painting metaphor
 Paint squares on grid for each mask layer
 Layers to interact to form components (e.g.
transistors)
29
Mask Layers in Cadence EDA /
Magic EDA
 Poly (red)
 N Diffusion (green)
 P Diffusion (brown)
 Metal (blue)
 Metal 2 (purple)
 Well (cross-hatching)
 Contacts (X)
30
Cadence EDA / Magic EDA User-
Interface
 Graphic Display Window Cursor
 Cursor
 Box - specifies area to paint
 Command window
(not shown)
 accepts text commands Box
:paint poly
: paint red
:paint ndiff
:paint green
Paint Paint Paint
:write (poly) (ntransistor) (pdiff)
 prints error & status
messages
31
Layer Interaction in Cadence EDA
/ Magic EDA
 Transistors - where poly, diffusion cross
 poly crosses ndiffusion - ntransistor
 poly crosses pdiffusion - ptransistor
 Vias - where layers connect

 Metal 1 connecting to Poly - polycontact
 Metal 1 connecting to P-Diffusion (normal) - pdc
 Metal 1 connecting to P-Diffusion (substrate contact) -

psc
 Metal 1 connecting to N-Diffusion (normal) - ndc
 Metal 1 connecting to N-Diffusion (substrate contact) -

nsc
 Metal 1 connecting to Metal 2 - via
32
Cadence EDA / Magic EDA
Layers - Example
nsc p-transistor
metal1
nwell pdc
polycontact
metal1
poly
polycontact
poly
metal1
psc ndc ndc

ntransistor
33
Why We Need Design Rules!
 Masks are tooling for manufacturing.
 Manufacturing processes have inherent
limitations in accuracy.
 Design rules specify geometry of masks
which will provide reasonable yields.
 Design rules are determined by experience.
34
Manufacturing Problems
 Photoresist shrinkage, tearing.
 Variations in material deposition.
 Variations in temperature.
 Variations in oxide thickness.
 Impurities.
 Variations between lots.
 Variations across a wafer.
35
Transistor Problems
 Varaiations in threshold voltage:
 oxide thickness;
 ion implanatation;
 poly variations.
 Changes in source/drain diffusion overlap.
 Variations in substrate.
36
Wiring Problems
 Diffusion: changes in doping -> variations in
resistance, capacitance.
 Poly, metal: variations in height, width ->
variations in resistance, capacitance.
 Shorts and opens:
37
Oxide Problems
 Variations in height.
 Lack of planarity -> step coverage.
metal 2
metal 2 metal 1
38
Via Issues
 Via may not be cut all the way through.
 Undersize via creates too much resistance.
 Via may be too large and create shorts,
parasitic capacitance, and sheet resistance.
Metal
Wire
Via Via
Metal Wire
39 DESIGN
VLSI ASSOC.PROF.BASIR SAIBON
 & Design Rules
  is the size of a minimum feature.
 Specifying  particularizes the scalable rules.
 Parasitics are generally not specified in
 units
40
Design Rules
 Typical rules:
 Minumum size
 Minimum spacing
 Alignment / overlap
 Composition
 Negative features
41
Types of Design Rules
 Scalable Design Rules (e.g. SCMOS)
 Based on scalable “coarse grid” -  (lambda)
 Idea: reduce  value for each new process, but keep

rules the same
 Key advantage: portable layout
 Key disadvantage: not everything scales the same
 Not used in “real life”
 Absolute Design Rules

 Based on absolute distances (e.g. 0.75µm)
 Tuned to a specific process (details usually proprietary)
 Complex, especially for deep submicron
 Layouts not portable
Scientific CMOS (sCMOS) is a breakthrough technology that offers an advanced set of performance features that render it
ideal to high fidelity, quantitative scientific measurement. The multi-megapixel sensors offers a large field of view and high
resolution, without compromising read noise, dynamic range or frame rate
42
SCMOS Design Rules
 Intended to be Scalable
 Original rules: SCMOS
 Submicron: SCMOS-SUBM
 Deep Submicron: SCMOS-DEEP
 Pictorial Summary: Book Fig. 2-24, p. 27
 Authoritative Reference: www.mosis.org
43
MOSIS SCMOS Design Rules
 Designed to scale across a wide range of
technologies.
 Designed to support multiple vendors.
 Designed for educational use.
 Ergo, fairly conservative.
44
SCMOS Design Rule Summary
 Line size and spacing:
 metal1: Minimum width=3, Minimum Spacing=3
 metal2: Minimum width=3, Minimum Spacing=4
 poly: Minimum width= 2, Minimum Spacing=2
 ndiff/pdiff: Minimum width= 3, Minimum Spacing=3,

minimum ndiff/pdiff seperation=10
 wells: minimum width=10,
min distance form well edge to source/drain=5
 Transistors:
 Min width=3
 Min length=2
 Min poly overhang=2

45
SCMOS Design Rule Summary
 Contacts (Vias)
 Cut size: exactly 2 X 2
 Cut separation: minimum 2
 Overlap: min 1 in all directions
 Cadence EDA / Magic EDA approach: Symbolic contact

layer min. size 4 X 4
 Contacts cannot stack (i.e., metal2/metal1/poly)
 Other rules
 cut to poly must be 3 from other poly
 cut to diff must be 3 from other diff
 metal2/metal1 contact cannot be directly over poly
 negative features must be at least 2 in size
 CMP Density rules (AMI/HP subm): 15% Poly, 30% Metal

46
Design Rule Checking in
Cadence EDA / Magic EDA
 Design violations
displayed as error paint
 Find which rule is
violated with ":drc
why”
Poly must overhang
transistor by at
least 2 (MOSIS rule
#3.3)
47
Scaling Design Rules
 Effects of scaling down are positive
 See book, p. 78-79 - if “everything” scales,
scaling circuit by 1/x increases performance
by x
 Problem: not everything scales proportionally
48
Aside Note - About MOSIS
 MOSIS - MOS Implementation Service
 Rapid-prototyping for small chips
 Multi-project chip idea - several designs on the same
wafer
 Reduced mask costs per design
 Accepts layout designs via email
 Brokers fabrication by foundries

(e.g. AMI, Agilent, IBM, TSMC)
 Packages chips & ships back to designers
 Our designs will use AMI 1.5µm process

(more about this later)
49
Aside Note - About MOSIS
 Some Typical MOSIS Prices (from www.mosis.org)
 AMI 1.5µm “Tiny Chip” (2.2mm X 2.2mm) $1,080
 AMI 1.5µm 9.4mm X 9.7mm $17,980

 AMI 0.5µm 0-5mm2 $5,900
 TSMC 0.25µm 0-10mm2 $15,550
 TSMC 0.18µm 0-7mm2 $24,500
 TSMC 100-159mm2 $63,250 + $900 X size
 MOSIS Educational Program (what we use)
 AMI 1.5µm “Tiny Chip” (2.2mm X 2.2mm) FREE*
 AMI 0.5mm “Tiny Chip” (1.5mm X 1.5mm) FREE*
*sponsored by Semiconductor Industry Assn., Semiconductor Research Corp., |

AMI, Inc., DuPont Photomasks, and MOSIS
50
Layout Considerations
 Break layout into interconnected cells
 Use hierarchy to control complexity
 Connect cells by
 Abutment
 Added wires
 Key goals:
 Minimize size of overall layout
 Meet performance constraints
 Meet design time deadlines
51
Hierarchy in Layout
 Chips are constructed as a hierarchy of cells
 Leaf cells - bottom of hierarchy
 Root cells - contains overall cell
 Example - hypothetical “UART”
 Pad frame - “ring” that contains I/O pads
 Core - contains logic organized as subcells
 Shift register
 FSM
 Other cells
52
Hierarchy Example
 Root Cell: UART
Root Cell:
UART
Pad
Core
Frame
Shift Other
Pad 1 Pad 2 ... Pad N FSM
Register Cells
53
Wires
6 metal 3
3 metal 2
3 metal 1
3 pdiff/ndiff
2 poly
54
Transistors
2
2
3
3
1
5
55
Vias
 Types of via: metal1/diff, metal1/poly,
metal1/metal2.
4 4
1
56
Metal 3 via
 Type: metal3/metal2.
 Rules:
 cut: 3 x 3
 overlap by metal2: 1
 minimum spacing: 3
 minimum spacing to via1: 2
57
Tub tie
4
1
58
Spacings
 Diffusion/diffusion: 3
 Poly/poly: 2
 Poly/diffusion: 1
 Via/via: 2
 Metal1/metal1: 3
59
Overglass
 Cut in passivation layer.
 Minimum bonding pad: 100 m.
 Pad overlap of glass opening: 6
 Minimum pad spacing to unrelated metal2/3:
30
 Minimum pad spacing to unrelated metal1,
poly, active: 15
60
STICK DIAGRAM
Schematic vs Layout
VDD
VDD
M2
In Out
M1
Out
In
Inverter circuit
GND
62
Schematic vs Layout
VDD 2-input NAND gate

VDD
B
A B
Out
A
GND
63
Stick Diagram
 A stick diagram is a graphical view of a
layout.
 Does show all components/vias (except
possibly tub ties), relative placement.
 Does not show exact placement, transistor
sizes, wire lengths, wire widths, tub
boundaries.
64
Stick Diagram
 Represents relative positions of transistors

 Stick diagrams help plan layout quickly
 Need NOT be to scale
 Draw with color pencils or dry-erase markers
VDD VDD
Inverter
NAND2
Out Out
In A B
GND GND 65
Stick Diagram
Layers
Metal (BLUE)
Polysilicion (RED)
N-Diffusion (Green)
P -Diffusion (Brown)
Contact / Via
66
Stick Diagram of C • (A + B)
A C B A B C
VDD VDD
X X
GND GND
67
Graph Theory:
(Describe State Machine Flow from Supply Voltage to Ground
And Device interconnects ) : Euler Path
Used to find Optimal Layout Design Vp
x Vertex b c
x
Edge a
Out
y
y c
Vertex a
Gnd
68
Graph:
The Theoretical Approach
 To reduce the size of an array and an uninterrupted
diffusion strip we need to find this “Euler path” talked
about previously. This is defined as the path through all
nodes or vertices (source and drain signals) such that
each edge( transistor gate inputs) is only visited exactly
once. (vertices maybe visited more than once).
 Euler paths are not unique.
 Euler paths must be consistent (same ordering in both
PUN (pull up network) and PDN (pull down network).
 Can Run in linear time3.
69
Consistent Euler Path
VDD
X
PUN
A
j C C
B
X i VDD
X = C • (A + B)
C B j A
i PDN
A B GND A B C
A
B
C
70
Consistent Euler Path
X i VDD
B A
j
GND A B C
71
Example
VDD
Logic Graph / Euler Path
X
A
j C C H/L (Pull Up Network)
B PUN
i VDD
X X
C
i B H/L AH/L
B j
A B PDN
C (Pull Down Network)
GND
GND
72
Example
X
A C
B D D C PUN
X VDD
X = (A+B)•(C+D)
C D
B A
PDN
A B
A GND
B
C
D
73
STICK DIAGRAM
Weinberger Methodology
 Also called “Weingberger approach” [weinberger67]
this method a (structured approach) was traditionally
used in the 1980s where the data wires are routed in
parallel to the supply rails and perpendicular to the
diffusion areas.
 This technique was most efficient for bit sliced
datapaths, because of the “over the cell wiring”.
 Figure 1 on the next slide shows this technique.
74
STICK DIAGRAM
Weinberger Methodology
Figure1  A more efficient technique

 Weinberger (using a single has been introduced called
metal layer m1) the “standard-cell
technique”, where signals
are now routed vertically
and polysilicon can serve for
both Nmos and Pmos
devices. This has given been
the focus of using the
Euler Approach.
ASSOC.PROF.BASIR SAIBON VLSI DESIGN 75

Optimized Approach (Euler Path)
 The Euler path technique has Figure 2

been used in what is called the
“standard cell technique”,
which results in a dense layout
for CMOS gates and one
polysilicon strip that can serve
as the input to both NMOS
and PMOS devices.
 Our main aim is to have a
single strip of diffusion in both
NMOS and PMOS devices.
This depends on the
“ordering” of the inputs. How
do we determine the best
order?

Two Versions of C • (A + B)
(Observe the input order)
77
The General Algorithm
1. Enumerate all possible  Therefore for the previous
decompositions to find the consistent Euler path for the
minimum number of Euler logic structure we achieve the
paths that cover the graph. optimal layout below.
2. Chain by means of diffusion Figure 3
area according to the order of
edges in Euler path.
3. If more than 2 edges are
necessary to cover the graph
model, then provide a
separation area between each
pair of chains.

Heuristic Algorithm
(of course life not being so easy)
The Heuristic Algorithm
Theorem: 1) To every gate with an even
number of inputs add a “pseudo”
input.
1) The following example and 2) The “pseudo” input does not
any circuit will have a single contribute to separation area. But
Euler path if the number of this input is added so that there is
inputs to every AND/OR a minimal combination between
element is odd. Inaddition, “pseudo” and real inputs.
2) There exist a graph model 3) Construct the graph model
such that the sequence of according to the vertical order of
edges on an Euler path inputs on logic diagram.
corresponding to the vertical 4) Chain together the gates by
order of the inputs on a means of diffusion areas as
indicated by the sequence of
planar representation of the edges on the Euler path. A
logic diagram. “pseudo" input gives a separation
between diffusions.
5) Delete “Pesudo” edges in parallel
and contacting “pseudo” edges in
series with other edges for final
circuit.
79
Example
We consider the following logic
Circuit (a and b), the derived
Euler Path (c) and the
corresponding Layout. For our
Euler path the PUN- and the
PDN -----.

Heuristic Works
We apply our Heuristic
approach to the previous
example and we obtain the
following sequence
(p1,2,3,1,4,5,p2) where we
remove the “pseudo” inputs
to get the same layout
previously shown in slide
11. (Note we choose the
combination with the
minimum interlaced with real
inputs) hence circuit (b).

Analysis
1. It must be noted that the
heuristic algorithm may not
always give the optimal
layout but if the resulting
sequence. However, if no
separation areas are
obtained then this is
the optimal solution.
2. The heuristic gives excellent

results for circuits which do not
have a Euler path. This is
Illustrated in the four-bit carry
look-ahead adder3 circuit
shown in this slide.

Analysis (continued)
Here in (b) we see the final
Euler Path interpretation
the corresponding circuit
diagram (c) and the a final
layout.

Stick Diagram Summary
 This Presentation has given a brief incite into optimizing

the layout of complex CMOS gates
 Using the Euler path approach and a heuristic algorithm.

The results show that by using this approach we can
optimize on layout area considerably
 Further work can be done to simulate the “real/actual”

benefits of this method in terms of power and
performance of a particular design.
84
References
1. Digital integrated circuits 2nd edition
2. Uehara, T. and Vancleemput, W. M “optimal layout
of CMOS Functional Arrays”.
3. Robert Sedgewick “Algorithms in C third edition”.
4. Forbes, B. E. “Silicon-on Sapphire Technology
Produces High-Speed Single- Chip Processor,
“Hewlett-Packard Journal, April 1977,pp 2-8.
85
LAYOUT DESIGN
RULES
3D View
87
Design Rules
 Interface between designer and process
engineer
 Guidelines for constructing process masks
 Unit dimension: Minimum line width
 scalable design rules: lambda parameter
 absolute dimensions (micron rules)
88
CMOS Process Layers
Layer Color Representation
Well (p,n) Yellow

Active Area (n+,p+) Green
Select (p+,n+) Green
Polysilicon Red
Metal1 Blue
Metal2 Magenta
Contact To Poly Black
Contact To Diffusion Black
Via Black
89
Layers in 0.25 m CMOS Process
90
Intra-Layer Design Rules
Same Potential Different Potential

9 2
0
Well or Polysilicon
6
10 2
3 3
Active Metal1
Contact
or Via 2
3 Hole 3
2 2 4
Metal2
Select
91
Transistor
Transistor Layout
3 2
92
Vias & Contacts
2
4
Via
1 1
5
Metal to
Metal to 1 Poly Contact
Active Contact 3 2
2
2
93
Select Layer
2
Select
3
2
1
3 3
2 5
Well
Substrate
94
CMOS Inverter Layout
GND In VDD
Out
(a) Layout
95
Stick diagrams (1/3)
 A stick diagram is a cartoon of a layout.
 Does show all components/vias (except
possibly tub ties), relative placement.
 Does not show exact placement, transistor
sizes, wire lengths, wire widths, tub
boundaries.
96
Stick Diagrams (2/3)
 Key idea: "Stick figure cartoon" of a layout
 Useful for planning layout
 relative placement of transistors
 assignment of signals to layers
 connections between cells
 cell hierarchy
97
Stick Diagrams (3/3)
98
Example - Stick Diagrams (1/2)
Alternatives - Pull-up Network
Circuit Diagram. Pull-Down Network Complete Stick Diagram

(The easy part!)
99
Example - Stick Diagrams (2/2)
100
Dynamic Latch Stick Diagram
VDD
in out
VSS
phi
phi’
101
Stick Diagram XOR Gate
Examples
102
Hierarchical Stick Diagrams
 Define cells by outlines & use in a hierarchy
to build more complex cells
103
Cell Connection Schemes
 External connection - wire cells together
 Abutment - design cells to connect when
adjacent
 Reflection, mirroring - use to make abutment
possible
104
Example: 2-input Multiplexer
 First cut:
105
Sticks Design of Multiplexer
 Start with NAND gate:
106
NAND Sticks
VDD
out
VSS
107
Refined one-bit Mux Design
 Use NAND cell as black box
 Arrange easy power connections
 Vertical connections for allow multiple bits
108
3-Bit Mux Sticks
select’ select
select’ select VDD
a2 ai m2(one-bit-mux) oi o2
b2 bi VSS

b1 bi VSS

b0 bi VSS
109
Multiple-Bit Mux
110
Cell Mirroring, Overlap
 Use mirroring, overlap to save area
111
Example: Layout / Stick Diagram
 Create a layout for a NAND gate given
constraints:
 Use minimum-size transistors
 Assume power supply lines “pass through” cell
from left to right at top and bottom of cell
 Assume inputs are on left side of cell
 Assume output is on right side of cell
 Optimize cell to minimize width
 Optimize cell to minimize overall area
112
Layout Example
Circuit Diagram. Exterior of Cell
113
Example - Cadence EDA / Magic EDA
Layout
 Overall Layout: 52 X 16
114
Review - VLSI Levels of
Abstraction
Specification
(what the chip does, inputs/outputs)
Architecture
major resources, connections
Register-Transfer
logic blocks, FSMs, connections
Logic
gates, flip-flops, latches, connections
Circuit
transistors, parasitics, connections
You are Here
Layout
mask layers, polygons
115
Levels of Abstraction -
Perspective
 Right now, we’re focusing on the “low level”:
 Circuit level - transistors, wires, parasitics
 Layout level - mask objects
 We’ll work upward to higher levels:
 Logic level - individual gates, latches, flip-flops
 Register- transfer level - Verilog HDL
 Behavior level - Specifications
116
The Challenge of Design
 Start: higher level (spec)
 Finish: lower level (implementation)
 Must meet design criteria and constraints
 Design time - how long did it take to ship a
product?
 Performance - how fast is the clock?
 Cost - NRE + unit cost
 CAD tools - essential in modern design
117
EDA / CAD Tool Survey: Layout
Design
 Layout Editors
 Design Rule Checkers (DRC)
 Circuit Extractors
 Layout vs. Schematic (LVS) Comparators
 Automatic Layout Tools
 Layout Generators
 ASIC: Place/Route for Standard Cells, Gate
Arrays
118
Layout Editors
 Goal: produce mask patterns for fabrication
 Grid type:
 Absolute grid (Cadence Layout Editor, MAX, LASI,
LEdit, Mentor ICStation, other commercial tools)
 Cadence EDA / Magic EDA: lambda-based grid - easier
to learn, but less powerful
 Mask description:
 Absolute mask (one layer for each mask)
 Cadence EDA / Magic EDA: symbolic masks (layers
combine to generate actual mask patterns)
119
Design Rule Checkers
 Goal: identify design rule violations
 Often a separate tool (built in to Cadence
EDA / Magic EDA)
 General approach: “scanline” algorithm
 Computationally intensive, especially for
large chips
120
Circuit Extractors
 Goal: extract netlist of equivalent circuit
 Identify active components
 Identify parasitic components
 Capacitors
 Resistors
121
Layout Versus Schematic (LVS)
 Goal: Compare layout, schematic netlists
 Compare transistors, connections (ignore
parasitics)
 Issue error if two netlists are not equivalent
 Important for large designs
122
Automatic Layout Tools
 Layout Generators - produce cell from spec.
 Simple: Procedural specification of layout
 (see book Fig. 2-33, p. 95)
 Complex: Netlist - places & wires individual
transistors
 ASIC - Place, route modules with fixed shape
 Standard Cells - use predefined cells as "cookie
cutters"
 Gate Arrays - configurable pre-manufactured
gates (only change metal masks)
 FPGAs - electrically configurable array of gates
123
Layout Design & Analysis Tools
 Layout editors are interactive tools.
 Design rule checkers are generally batch---
identify DRC errors on the layout.
 Circuit extractors extract the netlist from the
layout.
 Connectivity verification systems (CVS)
compare extracted and original netlists.
124
Automatic Layout (Digital IC Design)
 Cell generators (macrocell generators) create
optimized layouts for ALUs, etc.
 Standard cell/sea-of-gates layout creates
layout from predesigned cells + custom
routing.
 Sea-of-gates allows routing over the cell.
125
Standard Guideline:
for Cell Layout Floor Plan
METAL routing area (GROUND RAIL: GND)

METAL routing area (SUPPLY RAIL: VDD)
SUB METAL VDD routing area
Device Device Device Device
Active Active Active Active
Area Area Area Area
SUB METAL Signal Routing Area

Area Area Area Area

Area Area Area Area
SUB METAL GND routing area

126
Standard Guideline: Example
Cell Layout Floor Plan
127
Top Hierarchy Layout: ESD IO Pad
128
Top Hierarchy Layout Floor Plan:
Example
129
Top Hierarchy Layout Floor Plan:
Example
130
Top Hierarchy Layout: Example
131
Top Hierarchy Layout Pad Ring
Cadence
Layout Editor
132
Actual Final IO Pad
Being Probed by IC Tester
133
Actual Final SMT Package
Example
134
Actual Final SMT Package
Example
End of Chapter4
135

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RF Microelectronics

SAB24103 VLSI DESIGN

Associate Prof. Basir Saibon (UNIKLMSI Kulim Malaysia)

08.01.2017 ASSOC.PROF.BASIR SAIBON

MOSFET Layers in an n-well process

 Metal layers are electrically isolated from

 Layout can be very time consuming

 Standard cell design methodology

Individual Shared Gates

 output: layout file

 Generates enlarged master image of each mask layer

 Image printed on glass

 Step & repeat camera

 One copy for each die on wafer

 Note importance of mask alignment

 Generate physical layers as needed

 Cadence EDA / Magic EDA Layout Editor: "Abstract Layers”

 Poly (red) - polysilicon (equivalent to physical layer)

 ndiff (green) - n diffusion (combination of active, nselect)

 ntranistor (green/red crosshatch) - combined poly, ndiff

 pdiff (brown) - p diffusion (combination of active, pselect)

 ptransistor (brown/red crosshatch) - combined poly, pdiff

 contacts: combine layers, cut mask

 poly crosses pdiffusion - ptransistor

 Vias - where layers connect

 Metal 1 connecting to P-Diffusion (normal) - pdc

 Metal 1 connecting to P-Diffusion (substrate contact) -

 Metal 1 connecting to N-Diffusion (substrate contact) -

psc ndc ndc

 Idea: reduce  value for each new process, but keep

 Key disadvantage: not everything scales the same

 Not used in “real life”

 Absolute Design Rules

 Tuned to a specific process (details usually proprietary)

 Complex, especially for deep submicron

 Layouts not portable

 metal2: Minimum width=3, Minimum Spacing=4

 poly: Minimum width= 2, Minimum Spacing=2

 ndiff/pdiff: Minimum width= 3, Minimum Spacing=3,

 Min poly overhang=2

 Cut separation: minimum 2

 Overlap: min 1 in all directions

 Cadence EDA / Magic EDA approach: Symbolic contact

 cut to diff must be 3 from other diff

 metal2/metal1 contact cannot be directly over poly

 negative features must be at least 2 in size

 CMP Density rules (AMI/HP subm): 15% Poly, 30% Metal

 Accepts layout designs via email

 Brokers fabrication by foundries

 Our designs will use AMI 1.5µm process

 AMI 1.5µm 9.4mm X 9.7mm $17,980

 AMI 0.5mm “Tiny Chip” (1.5mm X 1.5mm) FREE*

*sponsored by Semiconductor Industry Assn., Semiconductor Research Corp., |

VDD 2-input NAND gate

 Represents relative positions of transistors

Figure1  A more efficient technique

ASSOC.PROF.BASIR SAIBON VLSI DESIGN 75

 The Euler path technique has Figure 2

ASSOC.PROF.BASIR SAIBON VLSI DESIGN 76

ASSOC.PROF.BASIR SAIBON VLSI DESIGN 78

ASSOC.PROF.BASIR SAIBON VLSI DESIGN 80

ASSOC.PROF.BASIR SAIBON VLSI DESIGN 81

2. The heuristic gives excellent

ASSOC.PROF.BASIR SAIBON VLSI DESIGN 82