Unit 1

Introduction to 16-bit microprocessor

8086 is the first 16-bit microprocessor developed by Intel and launched in 1978.

8086 microprocessor has a much more powerful instruction set along with the architecture
developments which imparted substantial programming flexibility and improvement in
speed over 8-bit microprocessor.

It is available in a 40 pin IC and operates at 5 volts DC supply.

Its electronic circuitry consists of 29000 transistors. It is implemented in N-channel. silicon

gate technology and available in three version i.e. 8086(5 MHz), 8086-2(8 MHz) and 8086-
1(10 MHz).

The 8086 microprocessor is no longer used, but the concept of its principles and structure
is very much useful for the understanding of other advanced Intel microprocessors.

Features of 8086
 Provides 20 address lines so, IMbytes of memory can be addressed.
 Multiplexed 16 bit address and data bus AD, AD, to minimize numbers of pin on IC.
 Operating Clock frequencies are 5 MHz, 8 MHz, 10 MHz.
 Arithmetic operation can be performed on 8 bit or 16 bit signed and unsigned data
including multiplication and division.
 Can operate in single processor and multiprocessor configuration i.e. operating
modes.
 Provide 6 byte instruction queue for pipelining of instructions execution.
 Generate 8 bit of 16 bit I/O address so it can access maximum 64 K I/O devices.
 Operate in maximum and minimum mode to achieve high performance level.

8086 microprocessor pin diagram

The 8086 pin signals can be categorized in three groups. The first are the signals having
common functions in minimum as well as maximum mode, the second are the signals which
have special functions in minimum mode and third are the signals having special functions
for maximum mode

The following signal description are common for both the minimum and maximum modes.

AD15-AD0: These are the time multiplexed memory I/O address and data lines i.e. it carry
both address and data according to time. Like in T 1 clock cycle it carry 16-bit address lines
& in T2, T3, T4 they carry 16 bit data.

A19/S6, A18/S5, A17/S4, A16/S3: These are the time multiplexed address and status lines.
During T1, these are the most significant address lines or memory operations. During I/O
operations, these lines are low. During memory or I/O operations, status information is
available on those lines for T2, T3, TW and T4 . The S4 and S3 combinedly indicate which
segment register is presently being used for memory accesses as shown in Table

S4 S3 Segment register
0 0 Extra segment
0 1 Stack segment
1 0 Core Segment
1 1 Data segment

̅̅̅̅̅̅ /S7-Bus High Enable/Status: The bus high enable signal is used to indicate the transfer
of data over the higher order (D15-D8) data bus. ̅̅̅̅̅̅ along with A0, determines whether a
byte or word will be transferred from/to memory locations. The ̅̅̅̅̅̅ /S7, is a time
multiplexed line, so during T2 to T4 the status signal S7 is transmitted on this line.

̅̅̅̅̅̅ A0 Word/Byte Access

0 0 Whole word from even address
0 1 Upper byte from/to odd address
1 0 Lower byte from/to even address
1 1 None
̅̅̅̅̅-Read: It is active low signal issued by the processor to indicate that processor is
performing read operation with memory or I/O depending on the status of M/ ̅̅̅ signal. The
signal remains tri-stated during the 'hold acknowledge'.

READY: It is used to synchronise Microprocessor with slow peripheral. When High, it

inticates that the peripheral devices are ready to transfer data.

RESET: When this signal goes high, processor enter into reset state and terminate the
current activity and start execution from FFFF0 H. The signal is active high and must be
active for at least four clock cycles.

INTR-lnterrupt Request: This is a level triggered request input & checked during the last
clock cycle of each instruction to determine the availability of request. If any interrupt
request is occured, the processor enters the interrupt acknowledge cycle.

̅̅̅̅̅̅̅̅: This input is examined by a 'WAIT' instruction. If the TEST input goes low, execution
will continue, else, the processor remains in an idle state.

NMI Non-maskable Interrupt: This is an edge-triggered input which causes a Type 2

interrrupt. The NMI is not maskable internally by software.

CLK- Clock Input: The clock input provides the basic timing for processor operation and bus
control activity. Its an asymmetric square wave with 33% duty cycle. The range of frequency
for different 8086 versions is from 5MHz to 10MHz.

VCC : +5V power supply for the operation of the internal circuit.

GND: ground for the internal circuit.

MN/̅̅̅̅̅: The logic level at this pin decides whether the processor is to operate in either
minimum (single processor) or maximum (multiprocessor) mode. When this pin is
connected to Vcc, the processor operates in minimum mode and when this pin is connected
to ground, the processor operates in maximum mode.

M/̅̅̅̅ - Memory/IO: When it is low, it indicates the CPU is having an I/O operation, and when
it is high, it indicates that the CPU is having a memory operation.

̅̅̅̅̅̅̅̅ -Interrupt Acknowledge: This signal is used as a read strobe for interrupt
acknowledge cycles. In other words, when it goes low, it means that the processor has
accepted the interrupt.

ALE-Address latch Enable: This output signal indicates the availability of the valid address
on the address/data lines, and is connected to latch enable input of latches 8282. This signal
is active high.

DT/ ̅ Data Transmit/Receive: This output is used to decide the direction of data flow
through the transceivers (bidirectional buffers). When the processor sends out data, this
signal is high and when the processor is receiving data, this signal is low.
̅̅̅̅̅̅̅ -Data Enable This signal indicates the availability of valid data over the address/data
lines. It is used to enable the transreceivers (bidirectional buffers) to separate the data from
the multiplexed address/data signal.
HOLD, HLDA- Hold/Hold Acknowledge: When the HOLD line goes high, it indicates to the
processor that another master is requesting the bus access. The processor, after receiving
the HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the
next clock cycle after completing the current bus (instruction) cycle. At the same time, the
processor floats the local bus and control lines. When the processor detects the HOLD line
low, it lowers the HLDA signal

̅̅̅̅, ̅̅̅̅, ̅̅̅̅ - Status Lines: These are the status lines which reflect the type of operation,
being carried out by the processor and required by the bus controller 8288 to generate all
memory or I/O access control signels. These become active during T4 of the previous cycle
and remain active during T1 and T2 of the current bus cycle.
These status lines are encoded

̅̅̅̅, ̅̅̅̅ ̅̅̅̅ Status

0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 Interrupt Acknowledge
1 I/O Read
0 I/O Write
1 Halt
0 Op-Code Access
1 Read memory
0 Write memory
1 Passive

̅̅̅̅̅̅̅̅: This output pin indicates that other system bus masters will be prevented from
gaining the system bus, while the LOCK signal is low. The LOCK signal is activated by the
'LOCK' prefix instruction and remains active until the completion of the next instruction.

QS1, QS0 - Queue Status: These lines give information about the status of the code-prefetch
queue. These are active during the CLK cycle after which the queue operation is performed.
These are encoded as shown in Table.
QS1 QS0 STATUS
0 0 No operation
0 1 First byte of opcode from the queue
1 0 Empty queue
1 1 Subsequent byte from the queue

̅̅̅̅̅̅̅̅̅̅̅̅, ̅̅̅̅̅̅̅̅̅̅̅̅- Request/Grant: Its main function is to provide control over bus
controller in maximum mode when co processor wants to get control over bus controller
for data read/ write operation. In maximum mode, Co processor issue request signal RQ on
receiving this signal CPU sends acknowledgment signal i.e. Grant signal GT to provide grant
for bus controller.

INTERNAL ARCHITECTURE OF 8086 CPU:

The internal architecture 8086 microprocessor is as shown in the fig. The 8086 CPU is
divided into two independent functional parts, the Bus interface unit (BIU) and execution unit
(EU). The Bus Interface Unit contains Bus Interface Logic, Segment registers, Memory
addressing logic and a Six byte instruction object code queue. The Execution unit contains
the Data and Address registers, the Arithmetic and Logic Unit, the Control Unit and flags.

FUNCTIONS OF EXECUTION UNIT:

1.To tell BIU to fetch the instructions or data from memory
2.To decode the instructions.
3.To generate different internal and external controls signal.
4.To execute the instructions.
5.To perform Arithmetic and Logic Operations

FUNCTIONS OF BUS INTERFACE UNIT:

1.Communication with External devices and peripheral including memory via bus.
2.Fetch the instruction or data from memory.
3.Read data from the port.
4.Write the data to memory and port.
5.Calculation of physical address for accessing the data to and from memory

Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor
instructions. The processor uses CS segment for all accesses to instructions referenced by
instruction pointer (IP) register. CS register cannot be changed directly. The CS register is
automatically updated during far jump, far call and far return instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with program
stack. By default, the processor assumes that all data referenced by the stack pointer (SP)
and base pointer (BP) registers is located in the stack segment. SS register can be changed
directly using POP instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with program
data. By default, the processor assumes that all data referenced by general registers (AX,
BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be
changeddirectly using POP and LDS instructions.
Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with
program data. By default, the processor assumes that the DI register references the ES
segment in string manipulation instructions. ES register can be changed directly using POP
and LES instructions.

All general registers of the 8086 microprocessor can be used for arithmetic and logic
operations.
The general registers are:
Accumulator register consists of 2 8-bit registers AL and AH, which can be combined
together and used as a 16-bit register AX. AL in this case contains the low-order byte of the
word, and AH contains the high-order byte. Accumulator can be used for I/O operations and
string manipulation.
Base register consists of 2 8-bit registers BL and BH, which can be combined together and
used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH
contains the high-order byte. BX register usually contains a data pointer used for based,
based indexed or register indirect addressing.
Count register consists of 2 8-bit registers CL and CH, which can be combined together and
used as a 16-bit register CX. When combined, CL register contains the low-order byte of the
word, and CH contains the high-order byte. Count register can be used as a counter in
string manipulation and shift/rotate instructions.
Data register consists of 2 8-bit registers DL and DH, which can be combined together and
used as a 16-bit register DX. When combined, DL register contains the low-order byte of the
word, and DH contains the high-order byte. Data register can be used as a port number in
I/O operations. In integer 32-bit multiply and divide instruction the DX register contains
high-order word of the initial or resulting number.

The following registers are both general and index registers:

Stack Pointer (SP) is a 16-bit register pointing to program stack.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is
usually used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register
indirect addressing, as well as a source data address in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register
indirect addressing, as well as a destination data address in string manipulation
instructions.

Memory Segmentation
The memory in an 8086 based system is organized as segmented memory. In this scheme,
the complete physically available memory may be divided into a number of logical
segments. Each segment is 64 Kbytes in size and addressed by one of the segment register.
To address a specific memory location within a segment, we need an offset address or
displacement. The offset address is also 16-bit long so that the maximum offset value can be
FFFF H and the maximum size of any segment is thus 64K locations

Advantages of segmentation:

1. The address associated with any instruction or data is only 16-bits though the 8086
has 20 bits physical address
2. Segmentation can be used in multi-user time shared system.
3. Programs and data can be stored separately from each other in segmentation.
4. We can have program of more than 64 Kbytes or data more than 64 Kbytes by using
more than one code or data segments.
5. Segmentation makes it possible to write programs which are position independent
or dynamically re-locatable.
6. Segmentation allows two processes to share data.
7. Segmentation allows you to extend the addressability of a processor.

Flag Register of 8086

Conditional /Status Flags

C-Carry Flag : It is set when carry/borrow is generated out of MSB of result. (i.e D7 bit for
8-bit operation, D15 bit for a 16 bit operation).

P-Parity Flag This flag is set to 1 if the lower byte of the result contains even number of 1’s
otherwise it is reset.

AC-Auxiliary Carry Flag This is set if a carry is generated out of the lower nibble, (i.e. From
D3 to D4 bit)to the higher nibble

Z-Zero Flag This flag is set if the result is zero after performing ALU operations. Otherwise
it is reset.
S-Sign Flag This flag is set if the MSB of the result is equal to 1 after performing ALU
operation , otherwise it is reset.

O-Overflow Flag This flag is set if an overflow occurs, i.e. if the result of a signed operation
is large enough to be accommodated in destination register.

Control Flags

T-Trap Flag If this flag is set, the processor enters the single step execution mode.

I-Interrupt Flag it is used to mask(disable) or unmask(enable)the INTR interrupt. When this

flag is set, 8086 recognizes interrupt INTR. When it is reset INTR is masked.

D-Direction Flag It selects either increment or decrement mode for DI &/or SI register
during string instructions.

PIPELINING : A technique used in 8086 microprocessors where the microprocessor begins

executing a second instruction before the first has been completed. That is, several
instructions are in the pipeline simultaneously, each at a different processing stage.

The pipeline is divided into segments and each segment can execute its operation
concurrently with the other segments. When a segment completes an operation, it passes
the result to the next segment in the pipeline and fetches the next operation from the
preceding segment. The final results of each instruction emerge at the end of the pipeline in
rapid succession
Minimum mode of operation
 Maximum mode of operation
Sr no Minimum mode
1 MN/MX pin is connected to Vcc.
2 No separate bus controller is required.
3 Control signals M/IO, RD, WR are
available on 8086 directly.
4 Control signals such as IOR, LOW,
MEMW, MEMR can be generated using
control signals M/IO, RD, WR are
available on 8086 directly.
5 ALE, DEN, DT/ R and INTA signals are
directly available.
6 Status of the instruction queue is not
available
7 In this mode of operation single
microprocessor is used
Maximum mode
MN/MX pin is grounded
Separate bus controller (8288) is
required.
Control signals M/IO, RD, WR are not
available on 8086 directly but status of the
control signals are available on status
pins S0, S1, and S2
Control signals such as, MRDC, MWTC.
AMWC, IORC, LOWC, AIOWC.are generated
by bus controller 8288 using status
signals S0 S1 and S2
ALE, DEN, DT/R and INTA signals are not
directly available and are generated by
bus controller 8288.
Status of the instruction queue is
available on pins QS and QS
In this mode of operation multiple co
processor is used.