2

MOS Inverters: Static Characteristics

Contents

2.1 Introduction
2.2 Voltage Transfer Characteristic (VTC)
2.3 Noise Immunity and Noise margins
2.4 Power and Area Considerations
2.5 Resistive-Load Inverter
2.6 Inverters with n-Type MOSFET Load
2.7 CMOS Inverter
2.8 DC Calculation of VIL, VIH, VOL, VOH and Vth
2.9 Design of CMOS Inverters

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2.1 Introduction

The MOS inverter is very basic digital gate used to invert the input signal. i.e logic 1 to
0 and logic 0 to 1.The logic 1 and 0 are symbols. In real digital circuits logic 1 and 0
are denoted as different voltage values. The MOS inverter can be implemented using
either positive or negative logic.

Positive logic means logic 1 refers to VDD and 0 refers to 0 volt while in case of
negative logic it is reverse. The voltage Vth is called threshold voltage or switching
voltage. When input voltage is between 0 to Vth (logic 0) output is VDD(logic 1) and
when input is between Vth to VDD(logic 1) output is 0(logic 0).The Ideal voltage
transfer characteristics(VTC), symbol and truth table of Inverter is shown below.

Fig.2.1 Logic symbol and truth table of the inverter and Voltage transfer characteristic (VTC)
of the ideal inverter.

The general structure of inverter is shown below. The nMOS transistor is driver or
switching device and the load may be passive (resistor) or active (nMOS/pMOS
devices).The input voltage is VGS while output voltage is VDS. Terminals which are
connected to ground are source and substrate. Since source and substrate are connected
to ground VSB is zero. As shown in fig. below current IL is load current and ID is driver
current. The output node is loaded with capacitive load if next stage is nMOS transistor.

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 Fig.2.2General circuit structure of an nMOS inverter.

2.2 Voltage Transfer Characteristic (VTC):

Applying KCL, it can be said that ID(Vin, Vout) = IL(VL). The voltage transfer
characteristic describing Vout as a function of Vin under DC conditions can then be found
by solving above equation for various input voltage values. The VTC in case of
practical inverter is shown below. The possible input and output voltage levels can be
represented as follows by referring the VTC below.
• When input VIL(minimum input logic low) the output would be
VOH(maximum output logic high)
• When input VIH( maximum input logic high) the output would be
VOL(minimum output logic low)
When the input voltage is at logic 0, the nMOS transistor is in cutoff mode. In this case
no current conducted by the driver and as a result the voltage drop across the load is
very small consequently the output node is charged to VDD. When input voltage is
increased from Vth to VDD slowly the nMOS start conducting current ID and voltage
drop across load increases with a finite slope consequently output voltage discharges
from VDD toward zero. Here there are two critical points on VTC where the slope is -
1.i.e the rate of change of input and output is same, one is increasing and other is
decreasing. The slope in the beginning and end is dvout/dvin = -1

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 .
Fig.2.3 Typical voltage transfer characteristic (VTC) of a realistic nMOS inverter.

VOH: Maximum output voltage when the output level is logic " 1"
VOL Minimum output voltage when the output level is logic "0"
VIL: Maximum input voltage which can be interpreted as logic "0"
VIH: Minimum input voltage which can be interpreted as logic " 1"

2.3 Noise immunity and noise margin:

An important performance criterion for any digital gate is its ability to interpret an input
signal within a voltage range as either a logic "0" or as a logic " 1 " allows digital circuits
to operate with a certain tolerance to external noise signal which causes variations in
the signal level is due to circuit noise which tends to corrupt the input/ output signals.
Here the circuit noise refers to unwanted signals that are coupled to some part of the
circuit from neighbouring lines usually interconnection lines by capacitive or inductive
coupling, or from outside of the system. The result of this interference is that the signal
level at one end of an interconnection line may be significantly different from the signal
level at the other end. Now consider the chain of inverter as shown below. Here the
output of first and second inverter is sent to next inverter via interconnect line. Now
consider that the signal while travelling along the interconnect line is affected by noise
may change the voltage levels from VOL/VOH to VIL/VIH. In this case the circuit
performance is not affected by noise. If noise is adversely affecting the circuit than the
voltage level at the input and output of particular interconnects line may be changed
from VOL to VIH and VOH to VIL. From this discussion the noise tolerance capability
(Noise Margin) for an inverter can be defined as follows.

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 Fig.2.4Propagation of digital signals under the influence of noise.

Fig.2.5Definition of Noise Margins

The noise immunity of the circuit increases with NM.
Two noise margins can be defined as follows.
1. Noise margin for low signal levels (NML) i.eNMH = VOH – VIH
2. Noise margin for high signal levels (NMH) i e NML = VIL – VOL

2.4 Power and Area Consideration:

Two other issues that play significant roles in inverter design are: power consumption
and the chip area occupied by the inverter circuit. More than one million logic gates
can be accommodated on a very large scale integra ted (VLSI) chip and the circuit
density is expected to increase even further in future-generation chips. Since each gate
on the chip dissipates power and thus generates heat, the removal of this thermal energy,
i.e., cooling of the chip, becomes an essential and usually very expensive task.
Most of the portable systems, such as cellular communication devices and laptop and
palmtop computers, operate from a limited power supply, and the extension of battery-
based operation time is a significant design goal. Therefore, it is very important to
reduce the amount of power dissipated by the circuit in both DC and dynamic operation.
The DC power dissipation of an inverter circuit can be calculated as the product of its

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power supply voltage and the amount of current drawn from the power supply during
steady state.
PDC = VDD ID

To reduce the chip area occupied by the inverter circuit, it is necessary to reduce the
area of the MOS transistors used in the circuit. As a practical measure, we use the gate
area of the MOS transistor, i.e., the product of W and L. Thus, an MOS transistor has
minimum area when both gate (channel) dimensions are made as small as possible
within the constraints of the technology. It follows that the ratio of the gate width to
gate length (W/L) should also be as close to unity as possible, to achieve minimum
transistor area. This requirement, however, usually contradicts other design criteria,
such as the noise margins, the output current driving capability, and the dynamic
switching speed.

2.5 Resistive load inverter and derivation of input/output voltage levels

For input voltages smaller than the threshold voltage Vth.,the transistor is in cut-off,
and does not conduct any drain current. Since the voltage drop across the load resistor
is equal to zero, the output voltage must be equal to the power supply voltage, VDD.As
the input voltage is increased beyond Vth.,the driver transistor starts conducting a
nonzero drain current. Note that the driver MOSFET is initially in saturation, since its
drain-to source voltage. (VDS = Vout)is larger than (Vin-VTO.).Thus,

Fig.5.6Resistive-load inverter circuit

With increasing input voltage, the drain current of the driver also increases, and the
output voltage V0,, starts to drop. Eventually, for input voltages larger than Vut+ V.,
the driver transistor enters the linear operation region. At larger input voltages, the
transistor remains in linear mode, as the output voltage continues to decrease.

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The various operating regions of the driver transistor and the corresponding input-
output conditions are listed in the following table.

Calculation of VOH

Referring to the resistive load inverter shown in fig. above Vout can be written as ,
Vout= VDD- IR RL

When Vin is lower than Vtho the driver current ID=IL=0 so,

VOH = VDD

Calculation of VOL
To derive expression of VOLcorresponds to logic 0 at the output ,the input voltage is
equal to VDD.
i.e., Vin = VDD. Now for the nMOS driver the input voltage (Vin- Vtho) >Voutwhich
operates nMOS in the linear region. The load current IRis given as,

Now from the circuit of resistive load inverter current IR = ID

where ,drain current ID is the linier mode drain current can be equated to IR as below.

The above equation can be rewritten as follows.

The above equation is a simple quadratic equation in VOLwhich can be solved to find
the value of VOL.
The product (kn RL)is one of the important design parameters which determine the
value of VOL.

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Calculation of VIL

VILis input low logic voltage at which the slope of the VTC becomes equal to (-
1),i.e., dVout/dVin, = - 1. When the input is equal to VIL,the Vout is slightly
smaller than VOH..HereVout> V1n – VthonMOS driver transistor operates in
saturation mode. So,IL =ID can be written as follows.

Now differentiate above equation with respect to vin

and put the value of dVout/dVin, = - 1 in the above equation

Rearranging above equation VIL can be written as below.

If we put value of vin=VIL in first equation vout can be calculated as below.

Calculation of VIH

VIHis input high logic voltage at which the slope of the VTC becomes equal to (-1),i.e.,
dVout/dVin, = - 1. when the input is equal to VIH,the Vout is slightly larger than
VOL..HereVout<V1n – VthonMOS driver transistor operates in linear mode. So,IL =ID
can be written as follows.

Now differentiate above equation with respect to vin

and put the value of dVout/dVin, = - 1 in the above equation

Rearranging above equation VIH can be written as below

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If we put value of vin=VIH in first equation vout can be calculated as below.

The four critical voltage points VOL, VOH ,VIL and VIH can now be used to
determine the noise margins, NML and NMH, of the resistive-load inverter circuit.

Fig.2.7VTC for Resistive load inverter using design parameter KnRL

The above expression depends on VDD, Vto and (knRL).Now the other parameters
such as the power supply VDDand the driver nMOSthreshold voltage Vthoare
determined by circuit and process technology used for the silicon implementation, the
term (kn RL)remains as the only design parameter which can be adjusted by the circuit
designer todetermining the shape of the VTC.
Looking to the VTC given in figure it can be said that as we go on increasing the value
of (knRL) the VTC tend to be more ideal however, may add other trade-offs with the
area and
the power consumption of the circuit.
Power Consumption and Chip Area
The average DC power consumption of the resistive-load inverter circuit is found by
considering two cases, Vin. = VOL (low) and Vin = VOH (high). When the input voltage

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is equal to VOL, the driver transistor is in cut-off. Consequently, there is no steady-
state current flow in the circuit (ID = IR = 0), and the DC power dissipation is equal to
zero.When the input voltage is equal to VOHon the other hand, both the driver
MOSFET and the load resistor conduct a nonzero current. Since the output voltage in
this case is equal to VOL the current drawn from the power supply can be found as

Assuming that the input voltage is "low" during 50% of the operation time, and "high"
during the remaining 50%, the average DC power consumption of the inverter can be
estimated as follows:

2.6 Inverter with n-type MOSFET load (Enhancement and Depletion load)
The resistive load inverter is not used because on silicon chip it occupies a large area
as well as higher power dissipation. In actual practice the resistor is replaced by nMOS
load device. The load device may be enhancement or depletion type nMOS. The nMOS
load inverter is shown in figure a and b using enhancement nMOS load as below. The
load device can be connected as either diode connected nMOS load or current source
nMOS load. In the diode connected case in fig. a the nMOS load device is always held
in saturation mode while in second case nMOS load device is always held in linear
mode. This gives higher voltage swing in the second case(current source biased nMOS
VOH=VDD) compared to first case(diode connected nMOS).The disadvantage of the
second case is it require two batteries to complete the biasing.ThenMOS load both type
gives higher DC(stand by) power dissipation so it is not used for large scale integration.

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 Fig.2.8 nMOS load Enhancements inverters a.diode connected load inverter b.current source load inverter

Several of the disadvantages of the enhancement-type load inverter can be avoided by

using a depletion-type nMOS transistor as the load device.-The fabrication process for
producing an inverter with an enhancement-type nMOS driver and a depletion-type
nMOS load is slightly more complicated and requires additional processing steps
especially for the channel implant to adjust the threshold voltage of the load device.
The resulting improvement of circuit performance and integration possibilities,
however easily justifies the additional processing effort required for the fabrication of
depletion load inverters. The immediate advantages of implementing this circuit
configuration are:(i) sharp VTC transition and better noise margins, (ii) single power
supply, and (iii)smaller overall layout area.

Fig.2.9nMOSDepletion load inverters

2.7 CMOS Inverter

CMOS inverter consists of an enhancement-type nMOS transistor and an enhancement-
type pMOS transistor named due to its complementary mode operation. The circuit

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topology is also named push-pull because for high input, the nMOS transistor drives
(pulls down) the output node while the pMOS transistor acts as the load, and for low
input the pMOS transistor drives (pulls up) the output node while the nMOS transistor
acts asthe load. As a result, both devices contribute equally to the circuit operation
characteristics. Figure 2.11 along with the table given below clearly denotes operation
of CMOS inverter which can be divided in to five regions A,B,C,D and E.

Fig.2.10 (a) CMOS inverter circuit. (b) Simplified view of the CMOS inverter, consisting
of two complementary non ideal switches.
The CMOS inverter has two important advantages over the other inverter
configurations.
• The steady-state power dissipation of the CMOS inverter circuit is theoretically
negligible, except for small power dissipation due to leakage currents. In all
other inverter structures examined results in a significant DC power
consumption.
• The voltage transfer characteristic (VTC) exhibits a full output voltage swing
between 0 V and VDD. Thus, the VTC of the CMOS inverter matches with the
VTC of an ideal inverter.
Since nMOS and pMOS transistors must be fabricated on the same chip side-
by-side,the CMOS process is more complex than the standard nMOS-only
process.

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 Fig.2.11Operating regions of the nMOS and the pMOS transistors.

One important requirement for fabrication of CMOS process is as follows.

• It must provide an n-type substrate for the pMOS transistors and a p-type
substrate for the nMOS transistors.
• In addition, the neighborhoodof nMOS and a pMOS transistor on chipin case of
CMOS process may lead to the formation of two parasitic bipolar transistors,
causing a latch-up condition. In order to prevent this undesirable effect,
additional guard rings must be built around the nMOS and the pMOS transistors
as well.
• The increased process complexity of CMOS fabrication may be considered as
the price being paid for the improvements achieved in power consumption and
noise margins.

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Exercises:

Detailed Questions
1. What is inverter? Discuss resistive load inverter using VTC.
2. Derive the formula of VOH,VOL, VIH and VIL in case of resistive load inverter.
3.Discuss the significance of noise margin in case of resistive load inverter.
4.Give drawbacks of resistive load inverter and hence discuss the solution to overcome
the said problem.
5.Compare nMOS depletion and enhancement load inverter using circuit diagram.
6.Compare nMOS load inverter with CMOs load inverter using circuit diagram
7.Compare all different inverters discussed in this chapter.

Brief Questions
1.What is VTC? What is its significance?
2.Define 1.lower noise margin 2.Upper noise margin.
3.What is KnRL? Discuss its impact on inverter performance?
4.Discuss speed area and power trade-offs in case of inverters.

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