AIR UNIVERSITY

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

EXPERIMENT NO 3

Lab Title: Finite State Machine and Time Shared Architecture

Student Name: Abdur Rehman, M. Muneeb Khan Reg. No: 210312, 210276

Objective: To get better understanding of time shared architecture and working

of state machines with FPGA Sparton6 Boards.

LAB ASSESSMENT:

Excellent Good Average Satisfactory Unsatisfactory

Attributes (5) (4) (3) (2) (1)
Ability to Conduct
Experiment
Ability to assimilate the
results
Effective use of lab
equipment and follows
the lab safety rules

Total Marks: ________________________ Obtained Marks: _______________________

LAB REPORT ASSESSMENT:

Excellent Good Average Satisfactory Unsatisfactory

Attributes
(5) (4) (3) (2) (1)

Data presentation

Experimental results

Conclusion

Total Marks: ________________________ Obtained Marks: _______________________

Date: ______________________________ark Signature: _______________________

 Lab Tasks:

Code:
module task1(out,in,clk,rst);
parameter s0=0;
parameter s1=1;
parameter s2=2;
parameter s3=3;
input in, clk, rst;
output reg out;
reg[1:0] NS, CS;
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
CS<=s0;
end
else
begin
CS<=NS;
end
end
always@(*)
begin
case(CS)
s0:
begin
if(in==0)
begin
NS=CS;
out=0;
end
else

begin
NS=s1;
out=0;

end
end

s1:
begin
if(in==0)
begin
NS=CS;
out=0;
end
else

begin
NS=s2;
out=0;

end
end
s2:
begin
if(in==0)
begin
 NS=CS;
out=0;
end

else

begin
NS=s3;
out=0;

end
end
s3:
begin
if(in==0)
begin
NS=CS;
out = 0;
end
else
begin

NS=s0;
out=1;
end
end
endcase
end

endmodule
Simple traffic signal controller
Design a state machine for the given scenario on paper and write RTL Verilog for
it. Main road has normally a green light, and minor road a red light. If a car is
detected on minor road (sensor), semaphores changes values, a timer is started
which asserts a signal ‘TIMED’ at the end of counting. When TIMED is asserted,
the semaphores go back to default values.

module TrafficLightController(
input wire clk,
input wire reset,
input wire carDetected,
output reg [1:0] mainRoad, // 00: Red, 01: Green
output reg [1:0] minorRoad, // 00: Red, 01: Green
output reg timed
);
parameter RED = 2'b00;
parameter GREEN = 2'b01;

reg [15:0] timerCount;

 always @(posedge clk or negedge reset) begin
if (!reset) begin
mainRoad <= GREEN;
minorRoad <= RED;
timerCount <= 16'h0000;
timed <= 1'b0;
end else if (carDetected && mainRoad == GREEN) begin
mainRoad <= RED;
minorRoad <= GREEN;
timerCount <= 16'h0000; // Reset the timer count when car is detected and light changes.
end else if (timerCount == 16'hFFFF) begin
timed <= 1'b1;
end else if (timed) begin
mainRoad <= GREEN;
minorRoad <= RED;
end else begin
timerCount <= timerCount + 1'b1; // Increment the counter every clock cycle.
timed <= 1'b0;
end
end
endmodule

module traffic_light_tb;
reg clk;
reg reset;
reg carDetected;
wire [1:0] mainRoad;
wire [1:0] minorRoad;
wire timed;

TrafficLightController uut (
.clk(clk),
.reset(reset),
.carDetected(carDetected),
.mainRoad(mainRoad),
.minorRoad(minorRoad),
.timed(timed)
);

initial begin
clk = 0;
reset = 0;
carDetected = 0;
#100;
reset = 1; #50;
reset = 0; #50;
carDetected = 1; #100;
carDetected = 0; #100;
carDetected = 1; #100;
carDetected = 0; #100;
$finish;
end

always #10 clk = ~clk;

endmodule
 Draw a state machine for Generating 1 at the output after counting four
number of 0’s on a serial interface. Both MOORE and MEALY
machines.

Moore Machine:
module moore_fsm (
input wire clk,
input wire reset,
input wire serial_in,
output reg out
);

parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;

reg [1:0] state, next_state;

always @(posedge clk or negedge reset) begin

if (!reset) state <= S0;
else state <= next_state;
end

always @* begin
case (state)
S0: if (serial_in == 0) next_state = S1; else next_state = S0;
S1: if (serial_in == 0) next_state = S2; else next_state = S0;
S2: if (serial_in == 0) next_state = S3; else next_state = S0;
S3: if (serial_in == 0) next_state = S0; else next_state = S0;
default: next_state = S0;
endcase
end

always @* begin
case (state)
S0: out = 0;
S1: out = 0;
S2: out = 0;
S3: out = 1;
default: out = 0;
endcase
end

endmodule

Moore Machine Testbench:

module Moore_machine_tb;
reg clk;
reg reset;
reg serial_in;
wire out;

moore_fsm uut (
.clk(clk),
.reset(reset),
.serial_in(serial_in),
.out(out)
);

initial begin
clk = 0;
reset = 0;
serial_in = 0;
 #100;
reset = 1; #50;
serial_in = 0; #100;
reset = 0; #50;
serial_in = 0; #100;
reset = 1; #50;
serial_in = 1; #100;
reset = 0; #50;
serial_in = 1; #100;
reset = 1; #50;
serial_in = 0; #100;
reset = 0; #50;
serial_in = 1; #100;
reset = 1; #50;
serial_in = 1; #100;
reset = 0; #50;
serial_in = 0; #100;

end

always #10 clk = ~clk;

endmodule
Mealy Machine:
module mealy_fsm (
 input wire clk,
input wire reset,
input wire serial_in,
output reg out
);
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
reg [1:0] state, next_state;

always @(posedge clk or negedge reset) begin

if (!reset) state <= S0;
else state <= next_state;
end

always @* begin
case (state)
S0: if (serial_in == 0) next_state = S1; else next_state = S0;
S1: if (serial_in == 0) next_state = S2; else next_state = S0;
S2: if (serial_in == 0) next_state = S3; else next_state = S0;
S3: if (serial_in == 0) next_state = S0; else next_state = S0;
default: next_state = S0;
endcase
end

always @* begin
case (next_state)
S0: out = 0;
S1: out = 0;
S2: out = 0;
S3: out = 1;
default: out = 0;
endcase
end

endmodule

Mealy Machine Testbench:

module mealy_machine_tb;
reg clk;
reg reset;
reg serial_in;
wire out;

mealy_fsm uut (
.clk(clk),
.reset(reset),
.serial_in(serial_in),
.out(out)
);

initial begin
clk = 0;
reset = 0;
serial_in = 0;
#100;
reset = 1; #50;
serial_in = 0; #100;
reset = 0; #50;
serial_in = 0; #100;
reset = 1; #50;
serial_in = 1; #100;
reset = 0; #50;
serial_in = 1; #100;
 reset = 1; #50;
serial_in = 0; #100;
reset = 0; #50;
serial_in = 1; #100;
reset = 1; #50;
serial_in = 1; #100;
reset = 0; #50;
serial_in = 0; #100;

end

always #10 clk = ~clk;

endmodule
1. What is the difference between mealy and MOORE state machines?
Mealy vs Moore State Machines:
A Mealy Machine is a type of finite state machine where the output is determined by both its
current state and current inputs. This means the output can change as soon as the input changes,
making it react faster to inputs.

A Moore Machine, on the other hand, is a type of finite state machine where the output is
determined only by its current state. This means the output changes only when the state changes,
typically at the clock edge.

2. What is difference between latch and flipflop?

Latch vs Flip-Flop:
A Latch is a basic memory device that changes its output immediately based on the applied input
when it is enabled. It is level triggered, meaning it checks the inputs continuously and responds to
the changes in inputs immediately.

A Flip-Flop is also a basic memory device, but it changes its output based on the applied input and
a clock or control signal. It is edge triggered, meaning it checks the inputs and changes the output
only at times defined by the clock signal.
3. Shifting Contents of Register:
When the contents of a register are shifted left, each bit moves one position to the left, and the
leftmost bit is lost. The rightmost bit (least significant bit) is filled with zero. This operation is
equivalent to multiplying the original number by 2.

When the contents of a register are shifted right, each bit moves one position to the right, and the
rightmost bit is lost. The leftmost bit (most significant bit) is filled with zero. This operation is
equivalent to dividing the original number by 2.
Conclusion:

In this lab, we learnt how to design and implement finite state machines and time-shared
architectures using FPGA Spartan6 Boards. We explored the principles of state machine operation
and the efficiency of time-shared architectures, enhancing our practical understanding of these
fundamental concepts in digital system design.