Final Project: Hierarchical Design and Characterization of a 3-bit

Thermometric CMOS DAC with Latched Input

I. INTRODUCTION
In your final laboratory project, you will complete a guided hierarchical design of a 3-bit digital-
to-analog converter (DAC). This project will encompass all of your CMOS circuit design learnings,
introductory DAC system knowledge, and use of LTspice. The DAC system will have the following
features:
A. A thermometric decoder that converts 3-bit binary input to 8-bit thermometer code;
B. An 8-bit resettable latch based register (with asynchronous reset) that temporarily stores
the thermometer code at clock high phase,
C. A DAC with 8 evenly spread analog output current settings based on thermometric digital
input (9 settings including the reset setting when all inputs are ‘low’),
D. Output Transimpedance amplifier stage to amplify and convert DAC output to voltage.

II. DESIGN and ANALYSIS

System architecture and some of the important specifications are depicted in Figure 7.1. The
figure shows the interface signals that consist of five digital inputs including a CLK and active-
low Reset signal, and a single-ended analog output. The lowest output voltage (~ -1.8 V) of the
DAC corresponds to Reset state achieved when RST is asserted (0). When RST is not asserted,
eight higher voltage levels are achieved, depending on input bits b2b1b0, with maximum voltage
(~ -0.6 V) corresponding to b2b1b0 = 111.

CLK
RST

8
Resettable Trans-
3 3-to-8 8 DAC Iout
b2b1b0 8-bit Latch- impedance Vout
Thermometric core
Based 8 Amplifier
Decoder
Register

Specifications:
Supply voltage 2.5 V (Also -2.5 V to supply Amplifier stage only)
Input Range: 8 (0-7) Analog Output Range: 1.2 V (min -1.8 V, max -0.6 V)
Figure 7.1. 3-Bit DAC system architecture, supply, and operation range

You will be guided through the design in the following sections, using a 2μm MOSFET technology
with MOSFET process parameters VTN= 0.8 V, VTP= -0.8 V, Kn’=50μA/V2, Kp’=20μA/V2,
Lmin=2μm, and Wmin=2 μm (minimum MOSFET Length and Width allowed in this technology) as
described in the Appendix. The scope of the project does not include a transimpedance amplifier
design. You will use an off-the-shelf CMOS amplifier instead.

A. 3-to-8 Thermometric Decoder

Design a 3-to-8 thermometric decoder using the truth table in Figure 7.2. You may use K-
maps or inspection of the truth table to derive simplified Boolean equations (minimum cost
design) for each of the eight outputs in terms of inputs. Your implementation should be
constructed from your library of AND2, AND3, OR2, and OR3 gates, all of which you will
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implemented in standard CMOS with minimum size MOSFETs and symmetrical HL and LH
transitions using longest path method. You may generate your own library of components
by designing each gate as an LTspice .asc file with interface pins (remember to include VDD
as an I/O interface pin) and then selecting from menu ‘Hierarchy’ → ‘Open this Sheet’s
Symbol’. When there is no symbol file (.asy) for your uniquely named gate, LTspice will offer
to generate a symbol using the defined interface pins. You can then edit the symbol file by
moving the pins to your liking, and save. Once you are done with your design entry and
simulation to convince yourself of correct functionality with 2.5 V supply, you may create a
symbol for your decoder (remember to include VDD as an I/O interface pin). Although the
symbol in Figure 7.2 uses bus notation, it is recommended that you use individual interface
pins for each input and output bit and avoid using buses in your LTspice circuits for simplicity.
EN b2-0 D7-0
0 000 00000000
1 000 00000001
1 001 00000011
EN 3-to-8
1 010 00000111
3 Thermometric 8
b2-0 D7-0 1 011 00001111
Decoder
with 1 100 00011111
Enable Input 1 101 00111111
1 110 01111111
1 111 11111111

Figure 7.2. 3-to-8 thermometric decoder symbol and truth table

B. 8-bit Latch-Based Register with Active-Low Reset

Design a robust D-latch with active-low RST. The latch should be transparent during the high
phase of the input CLK. There are few different approaches to D-latch design in standard
CMOS, as discussed in lectures. One of the simple approaches to incorporate an active-low
reset is to convert the inverter that determines Q’ output into a NAND2 gate. Use minimum
size MOSFETs, but the latch should have balanced HL and LH output. After you generate a
component for the 1-bit latch (remember to include VDD as an I/O interface pin), use it to
build an 8-bit latch based register with active-low reset, as shown in Figure 7.3. Once you
have run simulations to verify correct behavior, you can create a symbol for the register.
Again, use individual bits at interfaces instead of trying to create buses in LTspice. You may
use a clock frequency of 100 kHz for the rest of the project.

RST 8
Resettable Q7-0
8 8-bit Latch-
D7-0
Based 8
CLK Register
Q -0

Figure 7.3. Interface signals fort he 8-bit latch-based register with active low reset

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C. D-A Converter Core

Consider the current divider D-A converter core depicted in Figure 7.4. Upon assertion of
active-low reset all Q’x inputs are high, and Qx inputs are low. Under this condition
superposition of all sourced currents (Imain) are pulled from the Main Load PMOS on the right,
and Vcontrol will reach its lowest value at steady-state. Switches connected to Ibalancing are OFF,
and minimum current is pulled from the Balancing Load PMOS on the left. When Imain is
maximized, Iout is also maximized due to current mirror relationship. As more Qx inputs are
turned ON (Q’x inputs turned OFF), the Imain reduces and Ibalancing increases by the same
amount. The switching of current between the Main Load and Balancing Load ensures that
voltage controlled current sources at the bottom of the circuit, which are implemented
through MOSFETs, will always sink the same current and any errors due to changing voltage
between the current source terminals (i.e. MOSFET VDS) will be eliminated.

Balancing Main Vcontrol

(W/L)bal Load Load (W/L)main 3x(W/L)main

Imain
Ibalancing
Iout

Q0 Q0 ... Q7 Q

4f(vbias) 4f(vbias)
f(vbias) ... f(vbias)

Figure 7.4. D-A converter core with 8-bit differential input (inverted and non-inverted), and
current output (Iout)

In analog portions of the design, we need to ensure the MOSFETs are comfortably in the
region of operation that serves our purpose. There is often not a single solution, hence the
design we will walk trough for the DAC core will represent one of the possible solutions. As
is the case of any analog design, robust IC design procedures dictate that all DAC core
MOSFETs are constructed from series/parallel combinations of unit sized building
blocks, which will be a (W/L)u = 2μm/2μm MOSFET in this case.
i. vbias Generator
Robust DC bias (or DC reference) generator circuits that are tolerant to PVT (Process-
Voltage-Temperature) variations are beyond the scope of this project. Design a simple
DC bias generator that will provide vbias = 2/5*VDD= 1 V through a self-biased CMOS
inverter circuit with input connected to output, and W/L ratios of PMOS and NMOS
balanced such that equilibrium VM= 1 V. Otherwise, target lowest cost allowed by the
technology. Show your calculations. Since the generated vbias will connect to MOSFET
gates with negligible current load, this circuit should suffice for our purpose.
ii. f(vbias) Voltage-Controlled-Current-Source
Design each f(vbias) = 1μA current source in Figure 7.4 using a MOSFET (NMOS or PMOS?)

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with vbias as the controlling voltage. Since non-linear MOSFETs will be used to implement
low cost current sources, f will be a non-linear function of vbias, VT, K’, and W/L. Derive
this function, and solve for W/L to determine the MOSFET sizes you need to use. Explain
which region of operation you assumed for the MOSFET, and why. Note, once you
determine the W/L value for f(vbias) switched current, the MOSFET size that will generate
the non-switched base 4f(vbias) current can also be determined.
iii. Switches
For lowest cost, switches can be implemented using single pass-transistors. Since, we
assumed in the above discussion that a switch will be closed when its control voltage is
‘high’, you can consider implementation using minimum size N-channel MOSFETs.
a) Which region of operation should we assume for MOSFETs operated as switches?
Why?
b) Explain why we donot need to invest in a transmission gate to implement these
switches i.e. why is a pass transistor sufficient? Consider your assumptions in part ii
above in answering this question.
iv. Main and Balancing Current Load MOSFETs, and Current Mirror
Since we assumed in the design of voltage-controlled-current-sources that biasing gate
voltage was 1 V, we will start with a similar assumption for Current Load MOSFETs when
the corresponding switches are OFF (for simplicity) in the worst case. When switches
connected to a Load MOSFET start turning on more current is delivered by the load
MOSFET and gate voltage goes further down i.e. the risk of shutting off the load MOSFET
reduces. After the design is complete, we will check all switch positions in simulations to
ensure the load MOSFET stays in the desired region of operation.
a) Which region of operation are Main and Balancing Current Load MOSFETs in? Explain.
b) Assume all corresponding switches tied to the Main Load PMOS are OFF. Using the
current magnitude that corresponds to 4f(vbias) drawn by the non-switching base
source, calculate (W/L)main, such that gate voltage is 1 V less than VDD. Same
assumptions will lead to the same size for (W/L)bal. Remember the main circuit and
balancing circuit are exact copies of each other in order to keep the total current
flowing into the DAC core constant.
c) What is the Iout value from the DAC core when minimum current is delivered by the
Main Current Load MOSFET? What happens to this current as switches connected to
the Main Current Load MOSFET start turning on one by one? What is the expected
change in Iout with every step?
Generate a symbol for the DAC Core after you are done with your design.

D. Transimpedance Amplifier
Use LTC2054 operational amplifier from the library in negative feedback configuration with
+2.5 and -2.5V voltage supplies and a feedback resistor to convert and amplify Iout from DAC
Core output into Vout. Determine the closest value of feedback Resistor to obtain the output
voltage range in the specifications based on the range of Iout values predicted in section
C(iv).c. Show your calculations. Complete your simulations to verify functionality.

Generate a symbol fort he transimpedance amplifier after you are done with the design, use the

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symbols of all four units in Sections A-D to construct the overall system as in Figure 7.1. Simulate
to make sure the system works as expected. You may use a clock frequency of 100 kHz. Is this
DAC monotonic by design or could there be non-monotonic output? Explain your answer.

III. PROJECT REPORT

After completing design and analysis portions highlighted in the previous section with blue fonts,
submit the following in your final project report:
1. Objectives.
2. Hierarchical design and analysis (calculated design parameters, explanations to
address the questions in the previous section), schematics of each block (sections
II.A-D) in the system with annotated values for all MOSFETs, simulations to
demonstrate correct block functionality. Since the DAC Core unit (Section II.C) has
analog features, it is important to be more diligent in measuring analog parameters in
DAC Core simulations:
a. Simulation based verification that MOSFETs in the DAC Core (used as current
sources, switches, and current loads) are in their intended region of operation for all
input settings – comment on simulation measurements, and explain any
discrepancies.
b. Simulations results and comparison with expected values of important voltage
and current parameters in the DAC Core, including full scale voltage range, full range
of DAC output and current load values.
3. Ideal and simulated DAC system transfer function (output voltage vs. digital
input settings) in a single plot. These simulations should represent the results
after you integrate the full system – you may use Excel to get these plots after you
enter the results from each input setting into a table.
4. Tabulate the following performance parameters based on your theoretical
expectations and simulation results. Comment on any discrepancies and errors.
Theoretical Simulated
Resolution / Average Step (mV)
Resolution %
MSB Size (V)
Simulated Gain Error (if any)
Simulated Offset voltage (if any)
Simulated DAC INL
Simulated DAC DNL
5. Comment on how different sources of errors have been addressed in the design of
this DAC. Use lecture notes to identify what the sources of errors may be in DAC design.
6. Conclusions.

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APPENDIX: LTSPICE 2μm MOSFET device models

* MOSFET 2um N model with minimum W and L values as default
.MODEL MyN NMOS(
+ LEVEL=3
+ L=2E-6
+ W=2E-6
+ KP=50E-6
+ VTO=0.8
+ TOX=2.00E-6)

* MOSFET 2um P model with minimum W and L values as default

.MODEL MyP PMOS(
+ LEVEL=3
+ L=2E-6
+ W=2E-6
+ KP=20E-6
+ VTO=-0.8
+ TOX=2.00E-6)

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