Journal of Physics: Conference Series

PAPER • OPEN ACCESS You may also like

- SOC Balance Control Method for
Pseudo-random noise generator based on FPGA Cascaded Energy Storage System Based
on Nearest Level Modulation
Yong-Qi li, Hua-Long yu, Man Chen et al.
To cite this article: TanZheng Yang et al 2022 J. Phys.: Conf. Ser. 2189 012014
- Reliability performance of up-scaling
DSSC into sub-module in series design
using hermetic sealing
P N Anggraini, L Retnaningsih and J
Hidayat
View the article online for updates and enhancements.
- A multi-model method for tool wear
prediction with deep temporal features and
correlation alignment
Jingchuan Dong, Tao Chen, Yubo Gao et
al.

This content was downloaded from IP address 49.37.227.94 on 19/01/2024 at 13:39

ICCTIT-2021 IOP Publishing
Journal of Physics: Conference Series 2189 (2022) 012014 doi:10.1088/1742-6596/2189/1/012014

Pseudo-random noise generator based on FPGA

TanZheng Yang1*, Qin Zhang2, PengHui Li3

1
School of Mechanical and Electrical Engineering, Chengdu University of Technology,
Sichuan, Chengdu, China
2
School of Mechanical and Electrical Engineering, Chengdu University of Technology,
Sichuan, Chengdu, China
3
School of Mechanical and Electrical Engineering, Chengdu University of Technology,
Sichuan, Chengdu, China
*Corresponding author’s e-mail: ytz@stu.cdut.edu.cn

Abstract. This paper proposes a novel pseudo-random noise generator based on FPGA. The
system architecture is written by Verilog, and each sub-module is designed in Vivado software.
Modelsim is employed to co-simulate the sub-modules and the saved data is imported to
Matlab for spectrum analysis. Consequently, the proposed design can be applied to practical
noise generating with great scalability and flexibility.

1. Introduction
In the field of communication, noise played a critical role in affecting the performance of the
communication process. For instance, noise is often used to interfere with signals. Specifically, in
electronic warfare, in order to prevent the target from obtaining the correct information, noise is
widely utilized to interfere with the reception of the target signal. There are various kinds of noises in
nature, but to apply it to the communication, well-designed noise are artificially created to meet the
demand. Therefore, how to generate the required noise remains a problem that needs to be study and
settled. Man-made noise is not simply "random" noise, which means the randomness of the noise shall
be enhanced in other ways. Field Programmable Gate Array (FPGA) is a product of further
development on the basis of programmable devices such as PAL and GAL. It appears as a
semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only
solves the problem of custom circuits, but also overcomes the shortcomings of the limited number of
gate circuits of the original programmable device[1]. In recent years, rich literature focus on
pseudo-random noise, such as "Design of Active Noise Control System Based on FPGA." by Jun Yuan
et. al. and "Modular design and implementation of field-programmable-gate-array-based Gaussian
noise generator" published by Li, Lee, and Hwang[2]. This paper proposes a pseudo-random noise
generator with strong randomness and scalability based on FPGA.

2. Design Architecture
The system architecture diagram proposed in this paper is shown in Figure 1. The whole band-limited
pseudo-random noise generator includes a PN sequence generation module, a pseudo-random noise
generation module, a FIR filter module, and a CIC filter module. In this work, the designed symbol
rate ranges from 1KHz~1MHz, in which the supported symbol rate must be an integer multiple of 10.
In subsequent applications, the supported symbol rate can be modified by adjusting the filter
Content from this work may be used under the terms of the Creative Commons Attribution 3.0 licence. Any further distribution
of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI.
Published under licence by IOP Publishing Ltd 1
ICCTIT-2021 IOP Publishing
Journal of Physics: Conference Series 2189 (2022) 012014 doi:10.1088/1742-6596/2189/1/012014

coefficient. The input pseudo-random noise signal is uniformly yielded corresponding to the symbol
rate at a data rate of 100MHz.

Figure 1. Overall design architecture diagram

3. Detailed design
The Register Transfer Level (RTL) schematic of this design is shown in Figure 2. The output noise
signal is designed to be 32bit, which is also divided into two 16bit channels from the CFIR module, I
and Q channels, respectively.

Figure 2. RTL schematic of the overall design

3.1.PN sequence generation module

Recently, FPGA-based PN sequence generation and associated theoretical work is conducted by many
research teams[4]. The random sequence is generated by a certain device or algorithm, with the output
sequence being statistically independent and unpredictable[7]. The PN sequence generation module
used in this article refers to the PN sequence function in the official Matlab document, as shown in
Figure 3. The PN sequence generation module supports the generation of PN sequences with primitive
polynomials of order 6 to 25. The input of the module consists of enabling, initial value setting, and
primitive polynomial order and coefficient value setting.

Figure 3. PN sequence generation module diagram

3.2.Pseudo-random noise generation module

The pseudo-random noise generation module is shown in Figure 4, including three sections, four local
noise ROMs, noise synthesis processing, and noise data rate control, respectively. In detail, 4 different
noise data with the same upper and lower limits are stored in 4 local noise ROMs, which are generated
in MATLAB. The Gaussian white noise with specified length is generated using the randn function in
MATLAB, and then packaged into coe files. Subsequently, the files are sent to the ROM IP core in
Vivado to initialize the ROM. In this work, a ROM with a depth of 4096 is used, where the depth can

2
ICCTIT-2021 IOP Publishing
Journal of Physics: Conference Series 2189 (2022) 012014 doi:10.1088/1742-6596/2189/1/012014

also be adjusted according to actual needs. The noise data rate control will count by the input symbol
rate and determine when to output data and data valid flags.

Figure 4. Pseudo-random noise generation module

In order to enhance the randomness of the output noise data in the noise synthesis process, the
pseudo-random sequence data sent from the previous stage is used to construct the address generation
algorithm and the data output algorithm, as the algorithms both relate to the input PN sequence. The
read address of the local noise ROM is a 12-bit address. The input PN sequence data would be shifted
and registered three times by the address generation algorithm: For the first time 1-bit PN sequence is
expanded into 4 bit; for the second time, the 4-bit data is transferred into 12 bit; and for the third time,
the 12-bit data is transferred into 48 bit. Finally, the 48-bit data is divided into 4 addresses as local
noise ROM address. The I and Q noise signals are the accumulation of the noise data read by the 4
local noise ROMs, and the current 4bit data of the shift register determines whether to use the read
noise data. Moreover, each bit of the 4-bit shift register data corresponds to a local noise ROM. Take I
noise data as an example, "1" means that the read local noise ROM data is used for accumulation, and
"0" disables the accumulation. The accumulation rule of the Q signal is opposite to that of the I signal.

3.3.FIR filter module

The FIR filter is a filtering device that converts the input continuous-time signal into a discrete-time
signal according to a predefined algorithm[9]. Two FIR modules are used in this article, which are
located in the front and back stages of the CIC filter module. As shown in Figure 5a, the first FIR filter
module forms a cascade connection with the subsequent CIC filter module, which yields a 5-fold
interpolation on the noise data output by the previous pseudo-random noise generation module. The
second FIR filter module is shown in Figure 6a. It interpolates the noise data at the 50MHz data rate
by 2 times. After the interpolation, the data rate of the noise will become 100MHz.
The FIR IP core is used in these two FIR modules, but their parameter settings and filter
coefficients are different. The design of filter coefficient uses FilterDesigner tool in MATLAB, shown
in figure 6a and 6b. The data output by the FIR IP core is truncated before being output to the next
stage, with the mean value remaining a sign bit.

3
ICCTIT-2021 IOP Publishing
Journal of Physics: Conference Series 2189 (2022) 012014 doi:10.1088/1742-6596/2189/1/012014

Figure 5. The first FIR module and its parameter settings

Figure 6. The second FIR module and its parameter settings

3.4.CIC filter module

Two CIC IP cores are called in the CIC filter module to interpolate and filter the noise signal of
channel I and channel Q, respectively. The interpolation coefficient is determined by the input
duc_rate. The interpolation coefficient can be obtained by duc_rate divided by the product of the
interpolation multiples of the previous and subsequent stages, which happens to be 10. And the
product of the interpolation multiple of the subsequent stage. The CIC filter module is shown in Figure
7.

4
ICCTIT-2021 IOP Publishing
Journal of Physics: Conference Series 2189 (2022) 012014 doi:10.1088/1742-6596/2189/1/012014

Figure 7. CIC filter module

4. Simulation Verification
The analog signals output of all levels of modules is presented in Figure 8. In the simulation, the data
type is signed to be decimal number and the automatic simulation is enabled. According to the
time-domain waveform, two pseudo-random noise signals, I and Q, are generated.

Figure 8. Output waveforms of each module

It can be seen from Figure 9 that the spectrum of the saved output data at all levels is printed using
the fvtool tool in MATLAB. When drawing the spectrogram, the I and Q signals are combined into a
complex signal. According to the spectrogram, the spectrum of the pseudo-random noise signal
conforms to our expected design.

5
ICCTIT-2021 IOP Publishing
Journal of Physics: Conference Series 2189 (2022) 012014 doi:10.1088/1742-6596/2189/1/012014

Figure 9. The normalized spectrum of the output noise signal of each level

5. Conclusion
In this article, a scheme of a pseudo-random noise generator based on FPGA is proposed, and
corresponding simulation verification is conducted through Modelsim and MATLAB. The simulation
results indicate that the design of this article has realized the generation of pseudo-random noise,
which can be configured with different symbol rates. In future works, the filter coefficients can be
adjusted to match more symbol rates; the depth of the local noise ROM can be adjusted to enhance the
randomness of the generated noise data.

References
[1] Li, H.P., Kong, X.C. (2010) Design and Implementation of UART Based on FPGA. Journal of
Graduate University of Chinese Academy of Sciences, 27(02):199-203.
[2] Yuan, J., Li, J., Zhao, Q., Meng, X.S. (2021) Design of Active Noise Control System Based on
FPGA. Scientific Journal of Intelligent Systems Research, 3(2).
[3] Li, Y.P., Lee, T.S., Hwang, J.K. (2016) Modular design and implementation of
field-programmable-gate-array-based Gaussian noise generator. International Journal of
Electronics, 103(5).
[4] Ding, Q., Pang, J., Fang, J., et al. (2017) Designing of Chaotic System Output Sequence Circuit
Based on FPGA and Its Applications in Network Encryption Card. Int.Inovative
Com-puting, Information and Control, 13:449-456.
[5] Mao, Y., Liu, C., Liu, W. (2006) Design and FPGA Implementation of a Pseudo-random Bit
Sequence Generator using Spatiotemporal Chaos[A].International Conference on
Communications, Circuits and Systems, ICCCAS, Proceedings, 3:2 114-2 118.
[6] Yu S., Luj, H. (2007) Order Chua's Circuit and Its FPGA Real-ization Al.Proceedings of the 26th
Chinese Control Con-ference.pp.26-31.
[7] Chen, G.L., Wu, Z.Q., Pu. L.H. (2011) Design of m-sequence generator based on FPGA.
Electronic Test, 08:45-47.
[8] Han, C.Y., Xu, N., Wang, G.Y. (2009) Design and implementation of a pseudo-noise bit sequence
generator. Modern Electronic Technology, 32(05):75-77.

6
ICCTIT-2021 IOP Publishing
Journal of Physics: Conference Series 2189 (2022) 012014 doi:10.1088/1742-6596/2189/1/012014

[9] Guo Y., Yang H. (2017) Design and FPGA implementation of FIR filter based on IP core. Radio
Engineering, 47(01): 79-82.
[10] Song, Z.D., Wang, Z.Q., Li, J.R., Shen, C.W., Liu, S.X. (2020) Design and implementation of FIR
digital filter based on FPGA. Liquid Crystal Display, 35(10):1073-1078.