Operating Systems Computer Architecture

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OSCA-05 Register

SECTION A
Exercises

1. What is a Register?
 Small, permanent storage locations within the CPU used for a particular
purpose.
 Manipulated directly by the Control Unit.
 Wired for specific function.
 Size in bits or bytes (not MB like memory).
 Can hold data, an address or an instruction.

2. Describe briefly the operations of a register are.

The operations of the registers are
 Storing values from other locations (The register can be loaded with values
from other registers or from memory locations. This operation overwrites
previous value stored in the register.)
 Addition and subtraction.( Data from either other register or memory
location can be added to or subtracted from the value stored in the register,
leaving a sum or a difference in the register.)
 Shifting or rotating data. (Data in the register can be shifted or rotated right
or left by one or more bits. The shift operation is used to implement multiply
and divide arithmetic operations.)
 Testing contents for conditions such as zero or positive.

3. Identify these processor registers used in the data exchange process.

a. Used for exchange of data between I/O module and processor.
I/O BR – Input Output Branch Register
b. Contains data to be written into memory and receives data from memory.
MBR – Memory Buffer Register
c. Specifies the address in memory for the next read or write.
MAR – Memory Address Register
d. I/O address register to specify a particular I/O device.
I/O AR – Input output Address Register

4. What are the two main classes of processor registers?

 User-visible registers
 Control and status registers

5. Identify these user-visible registers.

a. Contain main memory addresses of data and instructions.
Address registers
b. Dedicated register that points to the top of the stack.
Stack pointer
c. Can be assigned to a variety of functions by the programmer.
Data registers
d. Contains an index into main memory, calculated from a base address.
Index register

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e. Holds the address of the starting location of a segment.

Segment register

6. Identify these control and status registers(or parts thereof).

a. Contains the most recently fetched instruction.
Instruction register (IR)
b. Holds the address of the instruction to be fetched next.
Program counter (PC)
c. Contains status information.
Program status word (PSW)
d. Bits set by the processor or hardware as the result of operations.
Condition codes (flags)

7. Describe functions of General Purpose Register (GPR) in the Intel architecture. You
are required to provide function of each register.
 Accumulator (AX): is a preferred register to use in arithmetic, logic and data
transfer instructions.
 Base register (BX): serves as an address register.
 Count register (CX): Program loop constructions are facilitated by the use of
CX, which serves as a loop counter.
 Data register (DX): is used in multiplication and division. It is also used in
I/O operations

8. Describe the function of registers in the set of User Invisible Registers (UIR).
 Memory Address register (MAR): Holds address of memory location and
connected to address bus.
 Memory Data register (MDR): Holds data being transferred to/from memory
- connected to data bus
 Instruction register (IR): The fetched instruction is loaded into the IR
 Program Counter (PC): The PC is updated by the CPU after each instruction
fetch
 Program Status Word (PSW):
a) contain individual bit fields indicating status information from
program execution, often error conditions
b) shows status of CPU and currently executing program

9. Explain in Register Transfer Language detail what a CPU would go through in

Adding a piece of data from a computer’s memory at a specific memory location.

Transfer Instruction Description

PC -> MAR Transfer the address from the PC to the MAR
MDR -> IR Transfer the instruction to the IR
IR(address) -> MAR Address portion of the instruction loaded in MAR
A+MDR -> A Contents of MDR added to contents of accumulator
PC + 1 -> PC Program Counter incremented

10. In the following 8-bit addition, what are the states of the Carry Flag (CF), Sign Flag
(SF), Zero Flag (ZF) and Overflow Flag (VF) after the arithmetic operation has been

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carried out. In the case of each flag describe what are condition(s) required for each of
the flags to be set.
11001100 + 01101011

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S 0 1 P 0 1 Z HC 1 1 0 C 1 0 V 0

Solution

Decimal Binary
24 00011000
18 00010010

24: 0001 1000

18: 0001 0010
42: 0010 1010

Decimal 2’s Complements

24 11101000
18 11101110

1110 1000
+ 1110 1110

1 11010110

00101001
+ 1

00101010 = 42

Sign Flag (S) =0

Zero Flag (Z) =0
Half-Carry (HC) Flag =0
Carry (C) Flag =0
Overflow (V) Flag =0
Parity (P) Flag =1

Sign Flag

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This Flag is set (assigned a value of 1) if the result of the arithmetic operation is
negative.

Zero Flag
This Flag is set (assigned a value of 1) if the result of the arithmetic operation is
zero.

Carry (C) Flag

This Flag is set (assigned a value of 1) if there is a carry from the MSB (Most
Significant Bit position). Otherwise it is reset ( assigned a value of 0).

Overflow (V) Flag

This Flag is set (assigned a value of 1) if there is a carry from the MSB ( Most
Significant Bit position) or the MSB’s value is 1 but not both.

Parity (P) Flag

For Even Parity, this Flag is set (assigned a value of 1) if the number of 1s in the
result inclusive of parity is even. Otherwise it is reset (assigned a value of 0).

Half-Carry (HC) Flag

This Flag is set (assigned a value of 1) if there is a carry from the HSB (Half
Significant Bit position). Otherwise it is reset (assigned a value of 0).

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S 0 1 P 0 1 Z HC 1 1 0 C 1 0 V 0
0 0 1 1 0 1 0 0 1 1 0 0 1 0 0 0
3 4 C 8

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