Announcements

• Exam 2 in class on Monday 5/19

– Chapters 4.1‐4.6, 4.9‐4.10, 6.1‐6.2, and 6.4‐6.8
– MOSFET device behavior
– MOSFETs in circuits and NMOS inverters/logic
– HWs 4‐6

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham

 Transistor alternatives to load resistor
• (a,b) X
• c: saturated load √
• d: linear load √
• e: depletion‐mode
load √
• f: pseudo NMOS √

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham

 NMOS saturated load inverter

• Common substrate for load and

, 0 switching device
⇒ • Body terminal connected to
⇒ Always in saturation ground
– 0 for MS
– 0 for ML ! In fact,

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham

 Design of (Load transistor)
Kn’=100μA/V2 , MS triode, ML saturation
VTO=0.6V • Use the same conditions as before:
80 μA, 2.5 V, 0.20 V
• Saturation region equation for ML:

• 2.3 V
• Body effect for ML:
• 2 2
• 0.2V, 2 0.6V,
, 0.6V, 0.5 V ⇒ 0.66V

Current determined by •
.
permissible power dissipation
of the NMOS,
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
 Calculation of
, , MS Cutoff
• When , MS is cutoff, ML
saturated (on) and charging the
capacitor.
• As capacitor gets charged,
– increases
– for ML decreases
• Charging stops when ML turns
off ( ), and

Imagine a capacitive load • VH reaches maximum of one VT

attached in parallel with MS below VDD
• Substantial degradation in VH
for the saturated load inverter!
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
 Calculation of
, , MS Cutoff •
• Without Body effect,
2.5 V 0.6 V 1.9 V
• Body effect makes the
situation even worse!
• Use and solve
2 2
• We get
Imagine a capacitive load 1.55 V
attached in parallel with MS

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham

 Design of (Switching transistor)
Kn’=100μA/V2 , MS triode, ML saturation
VTO=0.6V • Use the same conditions as before:
80 μA, 0.20 V
• Except 1.55 V !
• Triode region equation for MS:

2
• 1.55 V,
.
0.2 V, 0.6 V ⇒
,

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham

 Noise margin analysis

Completed inverter
design and SPICE
simulation of VTC for
NMOS inverter with
saturated load

• 0.6 V, 1.55 V
• 1.12 V, 0.38 V
• NM 0.43 V, NM 0.22 V
• NMH is significantly reduced, NML is similar
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
 NMOS linear load inverter
Kn’=100μA/V2 • For ML:
VTO=0.6 V

⇒ Always in triode (linear)

region.

• Body effect exists for ML

– 0 for ML ! In fact,
Choose such that

ML: Always in triode region

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham

 NMOS depletion‐mode load inverter
Kn’=100μA/V2 • , MS is off, ML conducts
VTO=‐1 V current until 0( ),
thus
• , , for ML
–
–
– As long as , ML in
saturation
For ML: 0, 0 • Body effect exists for ML
⇒ Always on
(designed to be saturated) – 0 for ML ! In fact,

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham

 Design of and
Kn’=100μA/V2 , MS triode, ML saturation
VTO=‐1 V • 80μA, 0.20V, 2.5V
• Saturation region equation for ML:
0
2
• Body effect for ML:
• 2
2 0.94 V
For ML: 0, 0 .
⇒ Always on • This gives
(designed to be saturated) • For MS, the same as in the resistive
.
load case, thus

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham

 Noise margin analysis

Completed inverter
design and SPICE
simulation of VTC for
NMOS inverter with
depletion‐mode load

• 0.93 V, 2.35 V
• 1.45 V, 0.50 V
• NM 0.90 V, NM 0.43 V
• NMH is high as in resistive load, NML is improved
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
 Pseudo NMOS inverter
Kn’=100μA/V2 • For ML:
VTO=‐1 V ⇒ On
When , |
| ⇒ saturated
⇒ no degradation of VH
• No body effect for ML !
– Bulk and source are connected for ML

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham

 NMOS Inverter Comparison
Pros Cons
Resistive Load Simple Takes too much area
Degradation of VH
Saturated Load Simple
Poor speed
Additional power
Linear Load faster speed
supply
Saves area
Depletion‐mode Process complexity
Best Noise Margin
load (Implant)
High speed
Smallest area Process complexity
Pseudo NMOS
Best speed (PMOS, Implant)
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham