2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON) | 979-8-3503-3250-6/22/$31.
00 ©2022 IEEE | DOI: 10.1109/UPCON56432.2022.9986388
Low Power Implementation of Compensated and
Sharpened CIC Decimation Filter
Neeraja P.K., Graduate Student Member, IEEE∗ , Bindiya T. S., Senior Member, IEEE† ,
Raghu C.V.‡ , Member, IEEE
Department of Electronics and Communication Engineering
National Institute of Technology Calicut, Kerala, India
Email: ∗ neerajapkn@gmail.com, † bindiyajayakumar@nitc.ac.in
‡ raghucv@nitc.ac.in
Abstract—This paper presents implementation of minimax
Sharpened Cascaded Integrator Comb (SCIC) decimation filter
using polyphase decomposition. By employing polyphase decom-
position, which is an efficient parallel processing technique, the
power consumption of the CIC filter realization is significantly
reduced at the cost of increased area. To enhance the passband
characteristics of the SCIC filter, a multilplier-less compensator
is cascaded. The ASIC synthesis result demonstrate that the
polyphase realization results reduction in the total power con-
sumption. This makes the design useful for low power sampling
rate conversion (SRC) applications.
Index Terms—Sampling Rate Conversion, Polyphase Decom-
position, Cascaded Integrator Comb Filter, Power Consumption
I. I NTRODUCTION
Processing of signals at different sampling rates, known as
multirate signal processing is very essential in many appli-
cations. Decimation and interpolation are the two approaches
employed to achieve different sampling rates. Cascaded Inte-
grator Comb (CIC) filter is an efficient class of decimation
filters and considered highly economical due to their inherent
multiplier-less architecture [1]. The basic structure of CIC
decimation filter is illustrated in Fig. 1. It consists of three
blocks namely integrator, comb and a decimation stage placed
in between them. The transfer function of the CIC filter can
Integrator Decimator Comb
1 N
R (1-z-1 )N
R (1-z-1 )
Fig. 1. The basic architecture of a CIC Decimation filter
be expressed as :
N
1 1 − z −R

H(z) =
R 1 − z −1
where, R is the decimation ratio and N is the filter order.
The zero-phase frequency response or the amplitude response
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takes the form given by
 N
1 sin(ωR/2)
H(ω) = (2)
R sin(ω/2)
The two main performance measures of the CIC filter
response are the passband droop and folding band or stopband
attenuation. The CIC filter’s amplitude response given by Eq.
(1), has a monotonically decreasing passband response. As
a result of that, it displays a droop in the passband that is
not tolerable in a number of digital signal processing (DSP)
applications. For minimizing the passband droop, the CIC
structure is to be modified by cascading it with an additional
filter called CIC compensator. Various techniques are dis-
cussed in the literature for the design of efficient compensators
[2]–[4]. Authors in [2] presented a wideband compensator
with an increase of complexity. In [3], a maximally flat
error criterion-based narrow band compensator is developed
in which the compensator coefficients are found by solving
a linear system of equations. At the bottom edge of the
initial folding band, folding band attenuation is observed.
Improvement in the stopband attenuation rejection is also
important while designing a CIC decimation filter. So it is nec-
essary to use techniques that help improving the folding band
response of the filter. To enhance the folding band response
of CIC filters and produce Sharpened Cascaded Integrator
Comb (SCIC) filters, a polynomial sharpening technique is
mentioned in paper [5]. Kaiser-Hamming (KH) sharpening
is incorporated in the SCIC filters by Kwentus in [6] in an
attempt to enhance both the passband and stopband response
by employing several instances of the same prototype filter.
Coleman in [7] presents Chebyshev polynomial sharpening
method that can make equiripple stopbands as well as merge
them into single wide folding band. But the method has got
signal to noise ratio (SNR) tapper loss while using in one
dimensional (1D) and two dimensional (2D) applications. The
SCIC filter with coefficients expressed as Sum of Powers of
Two (SPT) is designed in [8] using global optimization based
on interval analysis. It shows similar response compared to
(1) the Chebyshev sharpening method also. Implementation of
these conventional recursive CIC filters having large register
widths leads to high power consumption. Also as the integrator
sections operate at maximum sampling rate, it limits the
1
 operating speed of the filter. Hence it is essential to use SCIC filter design. By utilising the minimax error criterion in
techniques for power reduction in the implementation aspect. the folding bands, SCIC filters are designed in [8]. The M th
The polyphase representation is considered to be an efficient order sharpening polynomial is expressed as [12]
tool for rearranging the computations associated with the M
filtering operation and thereby reducing the computational load X
f (x) = am xm (3)
per unit time [9]. Some Polyphase structure realizations of m=0
CIC filters are discussed in [10], [11]. However, the polyphase
implementations for the Sharpened CIC filters are rare in where am represents the coefficient terms in the sharpening
the literature. The work in [14] discusses the power efficient polynomial. The SCIC filter’s amplitude response is presented
polyphase realizations of SCIC filters. However, the filter as
frequency characteristics are compromised in this approach. M
X
Polyphase decomposition in non-recursive realization of the HSCIC (ω) = am H m (ω) (4)
SCIC filter can eliminate the need of power hungry integrators m=0
at the input side. Recently, some works on multi stage CIC
where H(ω) is considered as first order CIC filter (N = 1)
decimation filters have been discussed in [15]–[18]. [16]
response given in Eq. (2). As a compensator will be cascaded
presents a framework for multi-stage decimation filter design
to the output of SCIC filter, it corrects the SCIC filter’s
requiring minimum number of additions per output sample
amplitude response corresponding to the low sampling rate,
(APOS). But it lacks the reconfigurability in the structure for
where the respective amplitude response is given as [4]
different decimation factors. Works in [17], [18] are based on (PM
two stage decimation filter structures incorporating KH and m=0 am ,h ω=0
SR sharpening techniques. It offers reconfigurability but filter HSCIC (ω) = PM 1 sin(w/2)
im (5)
m=0 am R sin(w/2R)
, otherwise
responses need further improvement. In this paper, polyphase
structure is employed for the realization of a passband com- To improve the response HSCIC (ω) in the passband region
pensated minimax sharpened CIC decimation filter with an Ω = [−ωp , ωp ], multiplier-less compensator using odd number
aim to decrease the power consumption without compromis- of coefficients is designed in [13] which has higher compen-
ing the performance characteristics. The compensated SCIC sation capability in wider passband (ωp ≥ 0.226π). Fig. 2 de-
polyphase realization proposed is found to result in lower picts the structure of a symmetric CIC passband compensator
dynamic power than the non-polyphase design along with having an odd number of coefficients. The amplitude response
comparable speed of operation, but with a trade-off in the of the compensator is given by [12]
area requirements due to the additional multiplier units in the
(L−1)/2
polyphase structure. X
The rest of this paper is structured as follows. The back- G (ω, c) = c0 + 2 ck cos (kω) (6)
ground of the existing works on the SCIC filters and the k=1

design of multiplier-less passband compensator are discussed where the passband compensator’s coefficients
T are represented
in Section II. The design of the proposed polyphase realization

by the vector, c = c0 , c1 , c2 , ...c(L−1)/2 where L is the
of passband compensated SCIC filter is explained in Section number of coefficients. These coefficients are calculated using
III. Design example in Section IV illustrates the features of the an objective function that estimates the maximum deviation
proposed work with the simulation results. Section V provides in the passband normalized to the gain of the compensator at
the synthesis results and Section VI concludes this paper. ω = 0 and is given by
II. OVERVIEW OF THE EXISTING WORK HSCIC (ω) G (ω, c) HSCIC (ω) G (ω, c)
ε (c) = max − min
Even though CIC filters have a great advantage of zero coef- ω∈Ω G (0, c) ω∈Ω G (0, c)
ficient storage requirements due to its inherently multiplier-less (7)
architecture and high folding band attenuation in the narrow
The coefficients are taken as variables and are further ex-
band [1], these filters have a high passband droop in their
magnitude response, which is undesirable in various applica-
tions. For wideband applications, both passband droop and Multiple Constant Multiplier
c(L-1)/2 c1 c0
stopband attenuation of conventional CIC filter deteriorates
and so sharpening techniques are to be employed. As the
passband droop and stopband attenuation rejection are trade- z-1 + z-1 + z-1 + z-1 +
off parameters, proper design criteria is essential to find an
optimum decimation filter. Fig. 2. Structure of symmetric CIC compensator having odd number of
Polynomial sharpening is an established method for im- coefficients [12]
proving the folding band attenuation rejection [12]. Finding
the optimum polynomial coefficients that can be expressed pressed as SPT terms to realize them as multiplier-less with a
as real, integer and in SPT form is an important task in the constraint on the overall number of SPT terms to be restricted

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 TABLE I
P OLYPHASE COMPONENTS

M 2 3 4
R 2 4 8 2 4 8 2 4 8
F0 (z) (1,1) (1,3) (1,7) (1,3) (1,12,3) (1,42,21) (1,6,1) (1,31,31,1) (1,161,315,35)
F1 (z) (2,0) (2,2) (2,6) (3,1) (3,12,1) (3,46,15) (4,4,0) (4,40,20,0) (4,204,284,20)
F2 (z) (3,1) (3,5) (6,10,0) (6,48,10) (10,44,10,0) (10,246,246,10)
F3 (z) (4,0) (4,4) (10,6,0) (10,48,6) (20,40,4,0) (20,284,204,4)
F4 (z) (5,3) (15,46,3) (35,315,161,1)
F5 (z) (6,2) (21,42,1) (56,336,120,0)
F6 (z) (7,1) (28,36,0) (84,344,84,0)
F7 (z) (8,0) (36,28,0) (120,336,56,0)

to a particular value. The optimum coefficients can be then be For N = 1, the recursive transfer function of the CIC filter
determined by solving the optimization problem given by provided in Eq. (1) will become:

1 1 − z −R


ĉ = arg minc [ε (c)]
H(z) = (10)
PW −1 R (1 − z −1 )
subject to ck = r=0 bk,r 2r ; k = 0, 1, 2, ...(L − 1)/2
(8) It is possible to express the aforementioned transfer function
P(L−1)/2 PW −1 in the non-recursive form, x as given by [10]
k=0 r=0 |bk,r | = B
R−1
1 X −k
G (0, c) ̸= 0 x= z
R (11)
k=0
where bk,r ∈ {−1, 0, 1} given in signed digit (SD) rep- 1  
resentation. Here, each bk,r ̸= 0 indicates one SPT term. = 1 + z −1 + z −2 + ... + z −(R−1)
R
Here, the input parameters for the compensator design are
ω, HSCIC , L, W, B where ω is the vector consisting the By substituting x of Eq. (11) in the place of H in Eq. (4)
frequency grid, HSCIC is the sharpened CIC filter response to obtain SCIC filter as
assessed on ω. W denotes the word length and B denotes the HSCIC = a0 + a1 x + a2 x2 + ... + aM xM (12)
limit on the total number of SPT terms. It can be noticed that
the optimization in Eq. 8 does not force unity gain in compen- A DSP system’s typical power consumption depends on the
sator when compared with the maximally flat compensation. number of operations carried out per sample, the sampling
This increases the compensation capability. Overall additions frequency and the wordlength. The polyphase filters can be
per output sample (APOS) of the compensated and minimax shifted to a lower rate through the use of polyphase de-
sharpened CIC decimation filter can be calculated as [15] composition, as described in [9, 10] and thereby reducing
P the power consumption. Performing the Rth level polyphase
decomposition of Eq. (11), we have
X
AP OS = M N (R + 1) + P − 1 + A (l) + NA (9)
l=1 R−1
X
z −i Fi z R .


where R is the decimation factor, N is the comb order, x= (13)
and M is the degree of the sharpening polynomial. P is i=0

the total number of sharpening coefficients that are not zero,
and A(l) indicates number of adders needed to implement
the lth sharpening coefficient. The number of adders needed
to implement the compensator is denoted by NA . The next
section describes the proposed polyphase implementation of
the sharpened CIC filter.
III. P ROPOSED WORK
In this paper, the polyphase implementation of compensated
minimax SCIC filter is presented with an intention of obtain-
ing the same magnitude response as that of non-polyphase
architecture, with a lower power consumption. Analysis of
implementation factors like area, power, and delay is the
main area of focus in this work. The proposed method of
implementation is detailed below.
Here, Fi (z) are the polyphase components that function at a
rate of fs /R given fs is the input sampling rate. Polyphase
components for the decimation filter with different values
of R such as 2, 4, 8 corresponding to different orders of
sharpening polynomial such as M = 2, 3, 4 are derived and
shown in Table I. Here, the polyphase components of the form
p0 + p1 z −1 + ... are listed using the notation p0 , p1 , ..etc.
For example, for M = 2, R = 2, the polyphase component,
F0 (z) is (1 + z −1 ), which is shown in the table as (1,1). The
resultant polyphase structure is cascaded with the multiplier-
less compensator given by Eq. (6) for improving the passband
droop characteristics. The proposed methodology is shown in
Fig. 3.
The next section illustrates the advantages of the polyphase
SCIC filter using a design example.

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CIC Filter design for specified order N and
Decimation factor R
Applying Minimax Sharpening to
generate SCIC filter for improving stopband
attenuation rejection
Polyphase Decomposition of
Sharpened CIC filter
Cascading a compensator to improve
the passband characteristics
Fig. 3. The proposed methodology
IV. D ESIGN E XAMPLE
To demonstrate the characteristics of the proposed realiza-
tion, a design example is discussed in this section. Matlab
R2021a version is used to do the design. The polyphase SCIC
filter is coded in Verilog, simulated and verified using Xilinx
Vivado 2020.2 version.
The design specifications for the SCIC decimation filter
are given below.
Passband edge frequency, ωp : π/4
Stopband attenuation rejection, As > 45dB
Passband droop, Ap < 0.05dB
In this example, the SCIC filter given in Eq. (12) is
employed with sharpening polynomial of order M = 4. To
obtain minimum adder requirements along with the similar
features as the compensated Chebyshev polynomial in [8], the
coefficients are taken as a2 = −2−6 , a4 = 1 and zero for all
other values of a. Thus, the response of the SCIC filter given
by Eq. (12) is modified as
HSCIC = x4 − 2−6 x2
where x is given in Eq. (11). For a decimation factor R = 8,
x can be written using Eq. (11) as
1 the passband characteristics with a reduced droop of 0.035dB
1 + z −1 + z −2 + ... + z −7


x= (15)
R while maintaining the stopband attenuation rejection within the
Substituting (15) in (14),


4
 realization, the number of operations per second is reduced
1 −1 −2 −7
HSCIC = 1 + z + z + ... + z
8

2
 
1 using application specific integrated circuit (ASIC) synthesis
− 2−6 1 + z −1 + z −2 + ... + z −7
8 results in the next section.
= 2−12 [( 1 + z −1 + z −2 + ... + z −7 )4
− (1 + z −1 + z −2 + ... + z −7 )2 ]
The direct realization of the SCIC filter given by Eq. 16 is
illustrated in Fig. 4, where the delays are realized using the
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TABLE II
A NALYSIS OF M AGNITUDE C HARACTERISTICS OF SCIC FILTER
STRUCTURES
Stopband
Passband Droop
Characteristics Attenuation
in dB, Ap
in dB, As
Uncompensated SCIC 0.85 50.33
Compensated SCIC 0.035 45.64
D flip flops. This is non-recursive architecture and the filters
described in each stage of it works at an operating frequency
of fs . As overall power consumption of the filter depends
on the number of operations carried out per sample and the
sampling frequency, operating at high rate results in increase
in power consumption. In order to overcome this demerit,
polyphase decomposition is introduced as shown in Fig. 5,
which helps to lower the operating frequencies of the sub-
filters, thereby achieving significant power reduction. Now, the
polyphase decomposition of Eq. 16 is performed using Eq. 13,
where the first term is decomposed with M = 4, R = 8 and
the second term is decomposed with M = 2, R = 8. The
polyphase decomposed SCIC filter is shown in Fig. 5.
For passband compensation in the resulting SCIC deci-
mation filters, compensator given by Eq. (6) is designed.
By proper analysis, it is found that the parameter values of
L = 3, B = 3 and W = 5 gives optimum compensator
coefficients
 as [15, -2],
 which can be represented in the SPT
form as 24 − 1, −21 . This compensator structure’s overall
adder requirement can be calculated as [12]
(L−1)/2
X
NA = L − 1 + NA (ck ) (17)
k=0
where ck is the vector of coefficients of the passband compen-
sator. Hence, only 3 adders are required for the compensator
design.
Simulation results of the uncompensated SCIC filter re-
sponse, passband compensated SCIC filter and compensated
polyphase decomposed SCIC filter are displayed in Fig. 6.
(14) Table II describes the analysis of the magnitude characteris-
tics of SCIC filter structures. Compared to the uncompensated
SCIC filter, which has a passband droop of 0.85dB, the
compensated SCIC filter provides a significant improvement in
given specifications. At the same time, due to the polyphase
resulting in a reduction in the power consumption when com-
pared to the non-polyphase architecture, which is demonstrated
V. S YNTHESIS R ESULTS
(16)
The design is synthesized onto the Application Specific In-
tegrated Circuit (ASIC) and the synthesis results are analyzed
and compared with the existing works.
4
 Fig. 4. Structure of non-polyphase SCIC decimation filter

Xin Xin 1+7z-1

88 1+161z-1+315z-2+35z-3 88
z-1
z-1
4+204z-1+284z-2+20z-3 88 2+6z-1
88
z-1
z-1
88 3+5z-1
88 10+246z-1+246z-2+10z-3
z-1
z-1
88 20+284z-1+204z-2+4z-3 88 4+4z-1 8
z-1
88 35+315z-1+161z-2+1z-3
+ z-1
88 5+3z-1
z-1
z-1
88 88 6+2z-1
56+336z-1+120z-2

z-1
z-1
88 84+344z-1+84z-2 88 7+1z-1
z-1
z-1
88 120+336z-1+56z-2 88 8

M=4;R=8 M=2;R=8

<<12 compensator

Fig. 5. Cascade of polyphase SCIC filter with passband compensator

A. ASIC Synthesis
ASIC synthesis is performed by Cadence genus RTL Com-
piler using TSMC 90nm CMOS Library (typical) utilizing a
core voltage of 1V. An input wordlength of 32-bit is used. The
corresponding results in terms of cell number and area, leakage
power, dynamic power, total power and maximum operating
frequency are listed in Table III. The synthesis results for the
proposed work at a clock frequency of 100 MHz are measured
and compared. From the ASIC synthesis results, it can be seen
that there is a 23.45% and 21.48% reduction respectively in
the dynamic and total power consumption in the polyphase
implementation when compared to the non-polyphase SCIC
design. Analyzing the timing report obtained after synthesis,

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Fig. 6. Magnitude response of compensated and uncompensated SCIC
decimation filters
TABLE III
ASIC SYNTHESIS RESULTS FOR THE NON - POLYPHASE AND THE
POLYPHASE SCIC IMPLEMENTATION
Characteristics Normal SCIC Polyphase SCIC
No: of Cells 936 1325
Cell Area (µm2 ) 11850.783 16144.677
Leakage Power (µW ) 52.17 67.79
Dynamic Power (µW ) 1334.61 1021.56
Total Power (µW ) 1386.78 1089.34
it is found that the polyphase realization can work upto
140MHz whereas the maximum operating frequency of non-
polyphase design is 135MHz. Thus polyphase architecture
provides an increase of 3% in maximum operating frequency
when compared to the non-polyphase architecture. However,
there is an increase in the number of cells and overall area
because of the added multipliers in the polyphase structure.
It can be further reduced by implementing them using adders
and shifters. Using techniques such as common sub-expression
elimination, number of shifts and additions can again be
minimized.
VI. C ONCLUSION
Low power designs are need of the hour in this technolog-
ical era. Low power polyphase implementation of minimax
Sharpened CIC decimation filter have been presented in this
paper with the following aims: i) implementation of SCIC
decimation filter with a stopband attenuation rejection of
greater than 45dB and passband droop of less than 0.05dB. ii)
reduction in power consumption. The synthesis results show
that, when compared to the non-polyphase designs, the pre-
sented polyphase based implementation technique significantly
lowers the power consumption of minimax SCIC decimation
filter. And because of this, it is useful for real-time applications
as well as other low power applications that use decimation
filters.
R EFERENCES
[1] E. B. Hogenauer, “An Economical Class of Digital Filters for Decimation
and Interpolation,” IEEE Trans. Acoust., vol. 29, no. 2, pp. 155–162,
1981, doi: 10.1109/TASSP.1981.1163535.
[2] G. J. Dolecek and fred harris, “Design of wideband CIC compensator
filter for a digital IF receiver,” Digit. Signal Process., vol. 19, no. 5, pp.
827–837, Sep. 2009, doi: 10.1016/J.DSP.2009.03.013.
[3] G. Molnar and M. Vucic, “Closed-form design of cic compensators
based on maximally flat error criterion,” IEEE Trans. Circuits Syst. II
Express Briefs, vol. 58, no. 12, pp. 926–930, 2011, doi: 10.1109/TC-
SII.2011.2172522.
[4] G. Molnar, A. Dudarin, and M. Vucic, “Design and Multiplierless
Realization of Maximally Flat Sharpened-CIC Compensators,” IEEE
Trans. Circuits Syst. II Express Briefs, vol. 65, no. 1, pp. 51–55, 2017,
doi: 10.1109/tcsii.2017.2700081.
[5] Saramaki, Tapio, and Tapani Ritoniemi. ”A modified comb filter struc-
ture for decimation.” In 1997 IEEE International Symposium on Circuits
and Systems (ISCAS), vol. 4, pp. 2353-2356. IEEE, 1997.
[6] A. Y. Kwentus, Z. Jiang, and A. N. Willson, “Application of filter sharp-
ening to cascaded integrator-comb decimation filters,” IEEE Trans. Sig-
nal Process., vol. 45, no. 2, pp. 457–467, 1997, doi: 10.1109/78.554309.
[7] J. O. Coleman, “Chebyshev stopbands for CIC decimation filters and
CIC-implemented array tapers in 1D and 2D,” IEEE Trans. Circuits
Syst. I Regul. Pap., vol. 59, no. 12, pp. 2956–2968, 2012, doi:
10.1109/TCSI.2012.2206435.
[8] Molnar, Goran, Aljosa Dudarin, and Mladen Vucic. ”Minimax design
of multiplierless sharpened CIC filters based on interval analysis.” 2016
39th International Convention on Information and Communication Tech-
nology, Electronics and Microelectronics (MIPRO), pp. 94-98. IEEE,
2016. doi: 10.1109/MIPRO.2016.7522118
[9] Vaidyanathan, P.P., ”Multirate digital filters, filter banks, polyphase
networks, and applications: a tutorial” Proceedings of the IEEE, 78(1),
pp.56-93,1990, doi:10.1109/5.52200
[10] Yang, Hong-Kui, and W. Martin Snelgrove. ”High speed polyphase
CIC decimation filters.”IEEE International Symposium on Circuits
and Systems (ISCAS), vol. 2, pp. 229-232, 1996,doi: 10.1109/IS-
CAS.1996.540394
[11] H. Aboushady, S. Member, Y. Dumonteix, and H. Mehrez, “Efficient
Polyphase Decomposition of Comb,” October, vol. 48, no. 10, pp.
898–903, 2001,doi:10.1109/82.974776
[12] Dudarin, Aljoša. ”Multiplierless decimation filters based on amplitude
sharpening and compensation.” PhD diss., University of Zagreb. Faculty
of Electrical Engineering and Computing. Department of Electronic
Systems and Information Processing, 2019.
[13] A. Dudarin, G. Molnar, and M. Vucic, “Optimum multiplierless
compensators for sharpened cascaded-integrator-comb decimation fil-
ters,” Electron. Lett., vol. 54, no. 16, pp. 971–972, 2018, doi:
10.1049/el.2018.5114.
[14] Karnati, Nikhil Reddy, Kye-Shin Lee, Joan Carletta, and Robert Veil-
lette. ”A power-efficient polyphase sharpened CIC filter for sigma-
delta ADCs.” In 2011 IEEE 54th International Midwest Symposium on
Circuits and Systems (MWSCAS), pp. 1-4. IEEE, 2011
[15] D. Gautam, K. Khare and B. P. Shrivastava, ”A Novel Approach
for Optimal Design of Sample Rate Conversion Filter Using Linear
Optimization Technique,” in IEEE Access, vol. 9, pp. 44436-44441,
2021, doi: 10.1109/ACCESS.2021.3066292.
[16] A. Dudarin, M. Vucic, and G. Molnar, “Decimation filters with minimum
number of additions per output sample,” Electron. Lett., vol. 58, no. 6,
pp. 246–248, Mar. 2022, doi: 10.1049/ell2.12415.
[17] S. Aggarwal, Improved two-stage decimator structure using Kaiser
Hamming sharpening. Circuits Syst. Signal Process.,2020, doi:
10.1007/s00034-020-01592-7
[18] S. Aggarwal, ”Efficient design of decimation filter using linear program-
ming and its FPGA implementation,” Integration 79, pp. 94–106, 2021,
doi: 10.1016/j.vlsi.2021.03.008

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