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4x4 Array Multiplier - Construction, Working and Applications
4x4 Array Multiplier - Construction, Working and Applications
4x4 Array Multiplier - Construction, Working and Applications
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Multiplication Algorithm
The common multiplication method is the “add and shift “algorithm. The multiplication alg
multiplier is shown below.
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4-by-4-multiplication
4 – by – 4 – multiplication 1
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example-2
Multiplicand = N-bits
Multiplier = M-bits
partial products = N*M.
The multiplication of two 8-bit numbers, which generates the 16-bit product.
A, B = 8 bits;
Steps in Multiplication
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If LSB of Multiplier is ‘1’. then add the multiplicand into an accumulator multiplier bit is s
the right and multiplicand bit is shifted one bit to the left.
Stop when all bits of the multiplier is zero.
Less hardware is used if partial products are added serially. We can add all PP by a pa
However, it is possible to use compression technique the number of partial products ca
before addition, is performed.
Booth Multiplier
The function of the booth’s multiplier is, to multiply 2 signed binary numbers which are re
complement form. The advantages of booths multipliers are Minimum complex, Multiplica
up. The disadvantages of booths multipliers are Power consumption is high.
Combinational Multiplier
The combinational multiplier performs multiplication of two unsigned binary numbers. The
combinational multiplier is that it can easily generate intermediate products. The main dis
combinational multiplier is it occupies large areas.
Sequential Multiplier
Multiplication is divided into the sequence of steps, where the partial product generate
accumulator partial sum now is shifted to the next step. The advantage of this is it occup
disadvantage os a sequential multiplier is it is a slow process.
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It reduces the number of partial products and uses carry select adder for the addition o
The advantage of the Wallace tree multiplier is a high speed and medium complex
disadvantage of Wallace tree multiplier is the layout design is irregular and occupies a lar
Array Multiplier
The multiplier circuit is based on the add shift algorithm. The main advantage of the arr
simple in design and regular in shape. The disadvantage of an array multiplier is the dela
power consumption.
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shift-and-add-multiplier
The design structure of the array Multiplier is regular, it is based on the add shift algorithm
where AND gates are used for the product, the summation is done using Full Adders
where the partial product is shifted according to their bit orders. In an n*n array multipli
compute the partial products and the addition of partial products can be performed by us
adders and n Half adders. The 4×4 array multiplier shown has 8 inputs and 8 outputs
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4-by-4-array-multiplier
A full adder has three input lines and two output lines, where we use this as a basic bu
array multiplier. The following is the example of a 4×4 array multiplier. The leftmost bit
partial product.
adder-block-diagram
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array-multiplier-block-diagram
The rightmost bit is the MSB bit of partial product. The partial products are now shifte
side on multiplication and they are added to get the final product. This process is repe
partial products exit for addition.
4-by-4-multiplication-1
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Where a0,a1,a2,a3 and b0,b1,b2,b3 are Multiplicand and Multiplier, summation of all p
products.The result of the sum of the partial product is a product.
For a 4×4 Array Multiplier, it needs 16 AND gates, 4 Half Adders(HAs), 8 Full Adde
Adders.
Minimum complexity
Easily scalable
Easily pipelined
Regular shape, easy to place and route
Array multiplier is used to perform the arithmetic operation, like filtering, Fourier
coding.
High-speed operation.
Thus, this is all about 4×4 array multiplier which is an advanced multiplier based on add
the performance can be easily increased using the pipeline technique with simple c
though it utilizes more logic gates where it can be implemented using Verilog. Here is
many logic gates are required to design 3*3 array multiplier?”.
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